UART selection is done with a lot of #ifdefs. This cleans things up a little.

Signed-off-by: Simon Glass sjg@chromium.org --- board/nvidia/common/board.c | 57 +++++++++++++++++++++++++----------------- 1 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 0f12de2..a5da310 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -35,6 +35,12 @@

DECLARE_GLOBAL_DATA_PTR;

+enum { + /* UARTs which we can enable */ + UARTA = 1 << 0, + UARTD = 1 << 3, +}; + const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING }; @@ -64,36 +70,32 @@ static void enable_uart(enum periph_id pid)

/* * Routine: clock_init_uart - * Description: init the PLL and clock for the UART(s) + * Description: init clock for the UART(s) */ -static void clock_init_uart(void) +static void clock_init_uart(int uart_ids) { -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - enable_uart(PERIPH_ID_UART1); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - enable_uart(PERIPH_ID_UART4); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ + if (uart_ids & UARTA) + enable_uart(PERIPH_ID_UART1); + if (uart_ids & UARTD) + enable_uart(PERIPH_ID_UART4); }

/* * Routine: pin_mux_uart * Description: setup the pin muxes/tristate values for the UART(s) */ -static void pin_mux_uart(void) +static void pin_mux_uart(int uart_ids) { -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); - - pinmux_tristate_disable(PINGRP_IRRX); - pinmux_tristate_disable(PINGRP_IRTX); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); - - pinmux_tristate_disable(PINGRP_GMC); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ + if (uart_ids & UARTA) { + pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_IRRX); + pinmux_tristate_disable(PINGRP_IRTX); + } + if (uart_ids & UARTD) { + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); + pinmux_tristate_disable(PINGRP_GMC); + } }

/* @@ -114,14 +116,23 @@ int board_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { + int uart_ids = 0; /* bit mask of which UART ids to enable */ + +#ifdef CONFIG_TEGRA2_ENABLE_UARTA + uart_ids |= UARTA; +#endif +#ifdef CONFIG_TEGRA2_ENABLE_UARTD + uart_ids |= UARTD; +#endif + /* Initialize essential common plls */ clock_early_init();

/* Initialize UART clocks */ - clock_init_uart(); + clock_init_uart(uart_ids);

/* Initialize periph pinmuxes */ - pin_mux_uart(); + pin_mux_uart(uart_ids);

/* Initialize periph GPIOs */ gpio_config_uart();

From: Tom Warren twarren.nvidia@gmail.com

This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren twarren@nvidia.com --- arch/arm/include/asm/arch-tegra2/tegra2_spi.h | 75 ++++++++ board/nvidia/common/board.c | 4 + drivers/spi/Makefile | 1 + drivers/spi/tegra2_spi.c | 245 +++++++++++++++++++++++++ 4 files changed, 325 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_spi.h create mode 100644 drivers/spi/tegra2_spi.c

diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h new file mode 100644 index 0000000..4344334 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h @@ -0,0 +1,75 @@ +/* + * NVIDIA Tegra2 SPI-FLASH controller + * + * Copyright 2010-2011 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA2_SPI_H_ +#define _TEGRA2_SPI_H_ + +#include <asm/types.h> + +#define TEGRA2_SPI_BASE 0x7000C380 + +struct spi_tegra { + u32 command; /* SPI_COMMAND_0 register */ + u32 status; /* SPI_STATUS_0 register */ + u32 rx_cmp; /* SPI_RX_CMP_0 register */ + u32 dma_ctl; /* SPI_DMA_CTL_0 register */ + u32 tx_fifo; /* SPI_TX_FIFO_0 register */ + u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ + u32 rx_fifo; /* SPI_RX_FIFO_0 register */ + +}; + +#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_ACTIVE_SCLK (1 << 26) +#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_ACTIVE_SDA (1 << 18) +#define SPI_CMD_CS_POL (1 << 16) +#define SPI_CMD_TXEN (1 << 15) +#define SPI_CMD_RXEN (1 << 14) +#define SPI_CMD_CS_VAL (1 << 13) +#define SPI_CMD_CS_SOFT (1 << 12) +#define SPI_CMD_CS_DELAY (1 << 9) +#define SPI_CMD_CS3_EN (1 << 8) +#define SPI_CMD_CS2_EN (1 << 7) +#define SPI_CMD_CS1_EN (1 << 6) +#define SPI_CMD_CS0_EN (1 << 5) +#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F + +#define SPI_STAT_BSY (1 << 31) +#define SPI_STAT_RDY (1 << 30) +#define SPI_STAT_RXF_FLUSH (1 << 29) +#define SPI_STAT_TXF_FLUSH (1 << 28) +#define SPI_STAT_RXF_UNR (1 << 27) +#define SPI_STAT_TXF_OVF (1 << 26) +#define SPI_STAT_RXF_EMPTY (1 << 25) +#define SPI_STAT_RXF_FULL (1 << 24) +#define SPI_STAT_TXF_EMPTY (1 << 23) +#define SPI_STAT_TXF_FULL (1 << 22) +#define SPI_STAT_SEL_TXRX_N (1 << 16) +#define SPI_STAT_CUR_BLKCNT (1 << 15) + +#define SPI_TIMEOUT 1000 + +#endif /* _TEGRA2_SPI_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index a2d45c1..2591ebc 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -31,6 +31,7 @@ #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> +#include <spi.h> #include "board.h"

DECLARE_GLOBAL_DATA_PTR; @@ -114,6 +115,9 @@ int board_init(void) clock_init(); clock_verify();

+#ifdef CONFIG_TEGRA2_SPI + spi_init(); +#endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 96c9642..02e7c40 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -41,6 +41,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c new file mode 100644 index 0000000..c8c20aa --- /dev/null +++ b/drivers/spi/tegra2_spi.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2010-2011 NVIDIA Corporation + * With help from the mpc8xxx SPI driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra2_spi.h> + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */ + if (bus > 0 && cs != 0) + return 0; + else + return 1; +} + + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* + * Currently, Tegra2 SFLASH uses mode 0 & a 24MHz clock. + * Use 'mode' and 'maz_hz' to change that here, if needed. + */ + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +void spi_init(void) +{ + struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; + u32 reg; + + /* Change SPI clock to 48MHz, PLLP_OUT0 source */ + clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, 48000000); + + /* Clear stale status here */ + reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; + writel(reg, &spi->status); + debug("spi_init: STATUS = %08x\n", readl(&spi->status)); + + /* + * Use sw-controlled CS, so we can clock in data after ReadID, etc. + */ + reg = readl(&spi->command); + writel(reg | SPI_CMD_CS_SOFT, &spi->command); + debug("spi_init: COMMAND = %08x\n", readl(&spi->command)); + + /* + * SPI pins on Tegra2 are muxed - change pinmux later due to UART + * issue. + */ +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; + u32 val; + + /* CS is negated on Tegra, so drive a 1 to get a 0 */ + val = readl(&spi->command); + writel(val | SPI_CMD_CS_VAL, &spi->command); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; + u32 val; + + /* CS is negated on Tegra, so drive a 0 to get a 1 */ + val = readl(&spi->command); + writel(val & ~SPI_CMD_CS_VAL, &spi->command); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; + unsigned int status; + int num_bytes = (bitlen + 7) / 8; + int i, ret, tm, bytes, bits, isRead = 0; + u32 reg, tmpdout, tmpdin = 0; + + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); + + ret = tm = 0; + + status = readl(&spi->status); + writel(status, &spi->status); /* Clear all SPI events via R/W */ + debug("spi_xfer entry: STATUS = %08x\n", status); + + reg = readl(&spi->command); + writel((reg |= (SPI_CMD_TXEN | SPI_CMD_RXEN)), &spi->command); + debug("spi_xfer: COMMAND = %08x\n", readl(&spi->command)); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + bits = (bitlen > 32) ? 32 : bitlen; + + if (dout != NULL) { + for (i = 0; i < bytes; ++i) + tmpdout = (tmpdout << 8) | ((u8 *) dout)[i]; + } + + num_bytes -= bytes; + if (dout) + dout += bytes; + bitlen -= bits; + + reg = readl(&spi->command); + reg &= ~SPI_CMD_BIT_LENGTH_MASK; + reg |= (bits - 1); + writel(reg, &spi->command); + + /* Write data to FIFO and initiate transfer */ + writel(tmpdout, &spi->tx_fifo); + writel((reg |= SPI_CMD_GO), &spi->command); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) { + status = readl(&spi->status); + + while (status & SPI_STAT_BSY) { + status = readl(&spi->status); + + tm++; + if (tm > SPI_TIMEOUT) { + tm = 0; + break; + } + } + + while (!(status & SPI_STAT_RDY)) { + status = readl(&spi->status); + + tm++; + if (tm > SPI_TIMEOUT) { + tm = 0; + break; + } + } + + if (!(status & SPI_STAT_RXF_EMPTY)) { + tmpdin = readl(&spi->rx_fifo); + isRead = 1; + status = readl(&spi->status); + + /* swap bytes read in */ + if (din != NULL) { + for (i = bytes - 1; i >= 0; --i) { + ((u8 *)din)[i] = + (tmpdin & 0xff); + tmpdin >>= 8; + } + din += bytes; + } + } + + /* We can exit when we've had both RX and TX activity */ + status = readl(&spi->status); + if (isRead && (status & SPI_STAT_TXF_EMPTY)) + break; + } + + if (tm >= SPI_TIMEOUT) + ret = -1; + + status = readl(&spi->status); + writel(status, &spi->status); /* ACK RDY, etc. bits */ + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", + tmpdin, status); + + if (ret == -1) + printf("spi_xfer: timeout during SPI transfer, tm = %d\n", tm); + + return ret; +}

This uses the SPI flash on Seaboard to store an 8KB environment.

Signed-off-by: Simon Glass sjg@chromium.org --- include/configs/harmony.h | 3 +++ include/configs/seaboard.h | 6 ++++++ include/configs/tegra2-common.h | 3 +-- 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 89e4911..ce0ae9f 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -58,4 +58,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 7e8c8cc..bd83a84 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -63,4 +63,10 @@ #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT + +/* Environment in SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET ((4 << 20) - CONFIG_ENV_SECT_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 73e0f05..2dd6fa4 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -50,8 +50,7 @@ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */

/* Environment */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */ +#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */

/* * Size of malloc() pool

The Tegra2 Seaboard has the unfortunate feature that SPI and the console UART are multiplexed on the same pins. We need to switch between one and the other during SPI and console activity.

This new file implements a switch and keeps track of which peripheral owns the pins. It also flips over the controlling GPIO as needed

Signed-off-by: Simon Glass sjg@chromium.org --- board/nvidia/common/Makefile | 53 ++++++++++++++ board/nvidia/common/uart-spi-fix.c | 140 ++++++++++++++++++++++++++++++++++++ board/nvidia/seaboard/Makefile | 1 - include/uart-spi-fix.h | 45 ++++++++++++ 4 files changed, 238 insertions(+), 1 deletions(-) create mode 100644 board/nvidia/common/Makefile create mode 100644 board/nvidia/common/uart-spi-fix.c create mode 100644 include/uart-spi-fix.h

diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile new file mode 100644 index 0000000..bf6d11a --- /dev/null +++ b/board/nvidia/common/Makefile @@ -0,0 +1,53 @@ +# Copyright (c) 2011 The Chromium OS Authors. +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).o + +COBJS-y += board.o +COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-fix.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nvidia/common/uart-spi-fix.c b/board/nvidia/common/uart-spi-fix.c new file mode 100644 index 0000000..e03857e --- /dev/null +++ b/board/nvidia/common/uart-spi-fix.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <ns16550.h> +#include "uart-spi-fix.h" +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/tegra2_spi.h> + + +/* position of the UART/SPI select switch */ +enum spi_uart_switch { + SWITCH_UNKNOWN, + SWITCH_SPI, + SWITCH_UART, + SWITCH_BOTH +}; + +/* Information about the spi/uart switch */ +struct spi_uart { + int gpio; /* GPIO to control switch */ + NS16550_t regs; /* Address of UART affected */ + u32 port; /* Port number of UART affected */ +}; + +static struct spi_uart local; +static enum spi_uart_switch switch_pos; /* Current switch position */ + + +static void get_config(struct spi_uart *config) +{ +#if defined CONFIG_SPI_CORRUPTS_UART + config->gpio = UART_DISABLE_GPIO; + config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART; + config->port = CONFIG_SPI_CORRUPTS_UART_NR; +#else + config->gpio = -1; +#endif +} + +/* + * Init the UART / SPI switch. This can be called before relocation so we must + * not access BSS. + */ +void gpio_early_init_uart(void) +{ + struct spi_uart config; + + get_config(&config); + if (config.gpio != -1) + gpio_direction_output(config.gpio, 0); + switch_pos = SWITCH_BOTH; +} + +/* + * Configure the UART / SPI switch. + */ +void gpio_config_uart(void) +{ + get_config(&local); + switch_pos = SWITCH_BOTH; + if (local.gpio != -1) { + gpio_direction_output(local.gpio, 0); + switch_pos = SWITCH_UART; + } else { + /* + * If we're here we don't have a SPI switch; go ahead and + * enable the SPI now. We didn't in spi_init() so we wouldn't + * kill the UART. + */ + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); + switch_pos = SWITCH_BOTH; + } +} + +static void spi_uart_switch(struct spi_uart *config, + enum spi_uart_switch new_pos) +{ + if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) + return; + + /* if the UART was selected, allow it to drain */ + if (switch_pos == SWITCH_UART) + NS16550_drain(config->regs, config->port); + + /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ + pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? + PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); + + /* + * On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ + gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); + switch_pos = new_pos; + + /* if the SPI was selected, clear any junk bytes in the UART */ + if (switch_pos == SWITCH_UART) { + /* TODO: What if it is part-way through clocking in junk? */ + udelay(100); + NS16550_clear(config->regs, config->port); + } +} + +void uart_enable(NS16550_t regs) +{ + /* Also prevents calling spi_uart_switch() before relocation */ + if (regs == local.regs) + spi_uart_switch(&local, SWITCH_UART); +} + +void spi_enable(void) +{ + spi_uart_switch(&local, SWITCH_SPI); +} diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index aab185e..7b67a26 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -31,7 +31,6 @@ endif LIB = $(obj)lib$(BOARD).o

COBJS := $(BOARD).o -COBJS += ../common/board.o

SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/include/uart-spi-fix.h b/include/uart-spi-fix.h new file mode 100644 index 0000000..68a7eb1 --- /dev/null +++ b/include/uart-spi-fix.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#if defined(CONFIG_SPI_UART_SWITCH) + +#ifndef __ASSEMBLY__ +/* + * Signal that we are about to use the UART. This unfortunate hack is + * required by Seaboard, which cannot use its console and SPI at the same + * time! If the board file provides this, the board config will declare it. + * Let this be a lesson for others. + */ +void uart_enable(NS16550_t regs); + +/* + * Signal that we are about the use the SPI bus. + */ +void spi_enable(void); +#endif + +#else /* not CONFIG_SPI_UART_SWITCH */ + +static inline void uart_enable(NS16550_t regs) {} +static inline void spi_enable(void) {} + +#endif