[U-Boot-Users] [Patch01]AS352X:U-Boot1.1.6 patch 1 for AS352X SOC
From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 1: Br
Signed-off-by: Thomas Luo
------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-01 17:44:42.000000000 +0800 @@ -0,0 +1,359 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Macro introduced to compensate for no support for floating point +division operation in the processor. So to get the correct value, +roundup is peformed to provide accurate results for certain conditions. */ + +#define DIVIDE_AND_ROUND_UP(dividend,divisor) \ + ( ( (dividend) + (divisor) - 1 ) / (divisor) ) + +/* For sake of completness and for easier exchanging of round-up and round-down +divisions provide also a round-down macro */ + +#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b)) + +/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A))) + +/* ------------------------defines for Dynamic Mem --------------------------- */ +#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset) + +#define AS352X_MPMC_CONTROL AS352X_SDRAM_BASE_ADDR( 0x00 ) +#define AS352X_MPMC_CONFIG AS352X_SDRAM_BASE_ADDR( 0x08 ) +#define AS352X_MPMC_DYRDCFG AS352X_SDRAM_BASE_ADDR( 0x28 ) +#define AS352X_MPMC_DYTRP AS352X_SDRAM_BASE_ADDR( 0x30 ) +#define AS352X_MPMC_DYTRAS AS352X_SDRAM_BASE_ADDR( 0x34 ) +#define AS352X_MPMC_DYTSREX AS352X_SDRAM_BASE_ADDR( 0x38 ) +#define AS352X_MPMC_DYTAPR AS352X_SDRAM_BASE_ADDR( 0x3C ) +#define AS352X_MPMC_DYTDAL AS352X_SDRAM_BASE_ADDR( 0x40 ) +#define AS352X_MPMC_DYTWR AS352X_SDRAM_BASE_ADDR( 0x44 ) +#define AS352X_MPMC_DYTRC AS352X_SDRAM_BASE_ADDR( 0x48 ) +#define AS352X_MPMC_DYTRFC AS352X_SDRAM_BASE_ADDR( 0x4C ) +#define AS352X_MPMC_DYTXSR AS352X_SDRAM_BASE_ADDR( 0x50 ) +#define AS352X_MPMC_DYTRRD AS352X_SDRAM_BASE_ADDR( 0x54 ) +#define AS352X_MPMC_DYTMRD AS352X_SDRAM_BASE_ADDR( 0x58 ) +#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104 ) +#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100 ) +#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 ) + +/* ------------------ MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM --------------------------- */ +#define MPMC_DY_TRP_IN_NS 20 +//#define MPMC_DY_TRP_IN_NS 10 + +#define MPMC_CLK_IN_MHZ_MIN 20 +#define MPMC_1_CLKCYCLE_IN_NS_MIN 50 + +#define MPMC_CLK_IN_MHZ 66 +//#define MPMC_CLK_IN_MHZ 24 +#if MPMC_CLK_IN_MHZ == 24 +#define MPMC_1_CLKCYCLE_IN_NS 42 +#elif MPMC_CLK_IN_MHZ == 66 +#define MPMC_1_CLKCYCLE_IN_NS 16 +#else +#define MPMC_1_CLKCYCLE_IN_NS 16 +#endif + +//#define MPMC_SDRAM_TCK_IN_NS 20 +#define MPMC_SDRAM_TCK_IN_NS 10 + +#define MPMC_DY_TRAS_MIN_IN_NS 50 +#define MPMC_DY_TRAS_IN_NS MPMC_DY_TRAS_MIN_IN_NS + +/* tAPR not available for micron MT48LC4M16A2 SDRAM */ +#define MPMC_DY_TAPR_INNS 0 + +#define MPMC_DY_TDAL_IN_NS (5 * (MPMC_SDRAM_TCK_IN_NS)) + +/* tWR can be minimum 15ns or 1CLK * 7ns */ +#define MPMC_DY_TWR_IN_NS (MPMC_1_CLKCYCLE_IN_NS + 8) +#define MPMC_DY_TRC_IN_NS 70 + +#define MPMC_DY_TRFC_INNS 70 + +#define MPMC_DY_TXSR_IN_NS 80 + +#define MPMC_DY_TRRD_IN_NS 20 +#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS)) + +#define MPMC_SDRAM_CAS 0x2 +#define MPMC_SDRAM_RAS 0x2 /* hha??? */ + +/* Low Power device bit settings */ +/* Device Type for APP Board 2.0 and 1.0 */ +/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power */ +#define MPMC_SDRAM_DEVICE_TYPE (0 << 3) + +/*ROW and COLUMN size mapping for mpmc SoC device */ + +/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#define MPMC_SDRAM_ADDR_MAPPING (0x11 << 7) + +#define MPMC_SDRAM_32BIT_EXTBUS (0 <<14) +#define MPMC_SDRAM_BUFFER_DISABLE (0 <<19) +#define MPMC_SDRAM_BUFFER_ENABLE (1 <<19) +#define MPMC_SDRAM_WP_ENABLE (0 <<20) + +#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \ + (MPMC_SDRAM_ADDR_MAPPING) | \ + (MPMC_SDRAM_32BIT_EXTBUS) | \ + (MPMC_SDRAM_BUFFER_DISABLE) | \ + (MPMC_SDRAM_WP_ENABLE)) + +#define MPMC_SDRAM_START_2_REF_CYCLES 2 +/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +/*64ms divided by 8192 */ +#define MPMC_SDRAM_tREF_inNs 7812 + + +#define MPMC_SDRAM_DYNAMIC_REF ((MPMC_SDRAM_tREF_inNs) / (MPMC_1_CLKCYCLE_IN_NS_MIN)) + + + +/* CAS Latency for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#if MPMC_SDRAM_CAS == 2 +#define MPMC_SDRAM_MODEVALUE (0x23 << 13) +#else +#define MPMC_SDRAM_MODEVALUE (0x33 << 13) +#endif + +/* ----------------------------------- functions --------------------------- */ + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} +void sdram_init(void ) +{ + volatile u32 Temp; + + + + *(volatile u32 *)AS352X_MPMC_CONTROL = 0x00000001; + + *(volatile u32 *)(AS352X_MPMC_CONFIG) = 0x00000000; + + *(volatile u32 *)(AS352X_MPMC_DYRDCFG) = 0x00000001; + + /* MPMCDynamicRP setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRP) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRP_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)) ; + + /* MPMCDytRAS setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRAS) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRAS_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamicSREX */ + *(volatile u32 *)(AS352X_MPMC_DYTSREX) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictAPR */ + *(volatile u32 *)(AS352X_MPMC_DYTAPR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TAPR_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + *(volatile u32 *)(AS352X_MPMC_DYTDAL) = + (1+(DIVIDE_AND_ROUND_UP((MPMC_DY_TDAL_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)))); + + /* Setup MPMCDynamictWR */ + *(volatile u32 *)(AS352X_MPMC_DYTWR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TWR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRC */ + *(volatile u32 *)(AS352X_MPMC_DYTRC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRC_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRFC */ + *(volatile u32 *)(AS352X_MPMC_DYTRFC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRFC_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictXSR */ + *(volatile u32 *)(AS352X_MPMC_DYTXSR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRRD */ + *(volatile u32 *)(AS352X_MPMC_DYTRRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictMRD */ + *(volatile u32 *)(AS352X_MPMC_DYTMRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TMRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + + *(volatile u32 *)(AS352X_MPMC_DYRASCAS0) = + ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS)); + + + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG; + + /*wait for 200uS by performing dummy read operation which consumes two */ + /* clock cycles for each operation */ + delay(50); + + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000183; /* apply NOP */ + + delay(1); + + /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000103; + + delay(100); + + /* start two auto refresh */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_START_2_REF_CYCLES ; + + /*- wait for 64 clk cycles of HCLK-*/ + delay(128); + + /* Program the operational value of the Refresh cycles, depending upon the + device specified period */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_DYNAMIC_REF / 16; + + /* Send the Mode set command to SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000083; + + /*---------------------------------------------------------------------- */ + + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_MODEVALUE) ; + + /* Merged with S.U. */ +#ifdef SDRAM_MT48H8M16LF + /* Device Type for APP Board 2.0 (MT48H8M16LF - 128Mbit - Low Power) */ + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE) ; +#endif /*SDRAM_MT48H8M16LF*/ + + /*---------------------------------------------------------------------- */ + /* Send the Normal mode set command to the SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000003; + + /* Enable the buffer for the SDRAM */ + Temp = *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) ; + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = + Temp | (MPMC_SDRAM_BUFFER_ENABLE); + +} +#define CCU_COUNT_MIN_10_MICROSEC 640 +/* +* Miscellaneous platform dependent initialisations +*/ + +void ccu_reset_device +( u32 deviceMask + ) +{ + int i; + + /* reset devices */ + wreg32( CCU_SRC, deviceMask ); + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + + /* hold the reset for at least 10 microseconds */ + for ( i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i-- ) + { + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + } + + /* remove lock */ + wreg32( CCU_SRL, 0 ); + wreg32( CCU_SRC, 0 ); +} + +void clk_set_async_mode() +{ + unsigned long i; + /* read CP15 register 1 into r0*/ + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); + /*enable asynchronous clocking mode*/ + asm("orr r0, %0, #(0x3 <<30) ": :"r"(i)); + /* write cp15 register 1*/ + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); +} + + +int board_init (void) +{ + ccu_reset_device( CCU_RESET_ALL_BUT_MEMORY ); + + wreg32(CGU_REG_PERI, 0x0F802000); + wreg32(CGU_REG_PROC,0); + wreg32(CGU_REG_AUDIO,0); + wreg32(CGU_REG_USB,0); + wreg32(CGU_REG_INTCTRL,0); + + wreg32(CGU_REG_COUNTA,0); + wreg32(CGU_REG_COUNTB,0); + wreg32(CGU_REG_IDE,0); + wreg32(CGU_REG_MEMSTICK,0); + wreg32(CGU_REG_DBOP,0); + + + wreg32(CGU_REG_PLLASUP,0x8); + wreg32(CGU_REG_PLLBSUP,0x8); + + wreg32(CGU_REG_PLLA,0); + wreg32(CGU_REG_PLLB,0); + + clk_set_async_mode(); + //set cpu and bus default clock + //plla 384M, CPU 192M,mpmc 64M,pclk 64M + + wreg32(CGU_REG_PLLA,0x2630); + wreg32(CGU_REG_PLLASUP,0); + wreg32(CGU_REG_COUNTA,CGU_LOCK_CNT); + while (!(rreg32(CGU_REG_INTCTRL)&1)) ; + + wreg32( CGU_REG_PROC, 0x011); + wreg32(CGU_REG_PERI,0x0EF2E295); + + + + //ccuResetDevice( CCU_RESET_ALL_BUT_MEMORY ); + + /* arch number of AS352X-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AS352X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + sdram_init(); + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff -urN u-boot-1.1.6.org/board/as352xpb/config.mk u-boot-1.1.6/board/as352xpb/config.mk --- u-boot-1.1.6.org/board/as352xpb/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/config.mk 2006-11-24 10:08:10.000000000 +0800 @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# David Mueller, ELSOFT AG, d.mueller@elsoft.ch +# +# AMS AS352XPB board with AS352X (ARM922T) cpu +# +# see http://www.austriamicrosystems.com for more information +# +# +# AS352X has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 0000'0000 +# +# download area is 3300'0000 +# + +TEXT_BASE = 0x00000000 diff -urN u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S u-boot-1.1.6/board/as352xpb/lowlevel_init.S --- u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/lowlevel_init.S 2006-11-30 10:24:49.000000000 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +/* some parameters for the board */ + +/* + * + */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ diff -urN u-boot-1.1.6.org/board/as352xpb/Makefile u-boot-1.1.6/board/as352xpb/Makefile --- u-boot-1.1.6.org/board/as352xpb/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/Makefile 2006-11-29 16:02:27.000000000 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := as352xpb.o nandas.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/board/as352xpb/nandas.c u-boot-1.1.6/board/as352xpb/nandas.c --- u-boot-1.1.6.org/board/as352xpb/nandas.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/nandas.c 2006-12-01 17:47:46.000000000 +0800 @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <asm/errno.h> +/* + * hardware specific access to control-lines + */ + +#define NAF_X8_X16_CODE 0x03 /* only for big block nand */ + +/** + * Power bit in NAF mode register. + **/ +#define NAF_POWER_ON 0x0C +#define NAF_POWER_OFF 0x00 + +/** + * NAF Config register bits. + **/ +#define NAF_X16 0x00000001 +#define NAF_FIFO_ENABLE 0x00000004 +#define NAF_DMA_ON 0x00000008 + +#define NAF_READ_STROBE_H 0x00000020 /* read strobe high is 4 PLCK cycles */ +#define NAF_READ_STROBE_L 0x00000400 /* read strobe low is 5 PLCK cycles */ +#define NAF_WRITE_STROBE_H 0x00003000 /* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_L 0x00040000 /* write strobe high is 4 PCLK cycles */ + +#define NAF_STROBE_CONFIG \ + ( NAF_READ_STROBE_H | NAF_READ_STROBE_L | NAF_WRITE_STROBE_H | NAF_WRITE_STROBE_L ) + + +/** + * NAF modi + **/ +#define NAF_MODE_CLE 1<<0 +#define NAF_MODE_ALE 1<<1 +#define NAF_MODE_NCE 1<<4 +#define NAF_MODE_WP 1<<7 + +#define NAF_MODE_DATA_READ_NO_ECC 0x14 +#define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4 +#define NAF_MODE_DATA_WRITE_NO_ECC 0x94 +/* + * chip R/B detection + */ +static int as352x_read_status; + +static int as352x_nand_ready(struct mtd_info *mtd) +{ + return ( ( rreg16( NAF_STATUS ) & 0x0080 ) == 0x0080 ); + +} +static int as352x_nand_strobe() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0100 ) == 0x0100 ); +} +static int as352x_fifo_isfull() +{ + return ( ( rreg16( NAF_STATUS ) & 0x01000 ) ); +} + +static int as352x_fifo_isempty() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0200 ) ); +} +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char as352x_nand_read_byte(struct mtd_info *mtd) +{ + u_char data; + wreg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */ + while (!as352x_nand_strobe(mtd)); + data = rreg16( NAF_DATA ); + if (as352x_read_status) + data |= 0x80; + return data; +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void as352x_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + + wreg16( NAF_DATA, byte ); + while (!as352x_nand_strobe(mtd)); +} + +void as352x_nand_wait_fifo_empty( ) +{ + while ( ( rreg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; /* wait for got empty and ready */ +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void as352x_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + u32 *p =(u32 *)buf; + struct nand_chip *this = mtd->priv; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isfull()); + wreg32( NAF_FIFODATA, p[i] ); + } + as352x_nand_wait_fifo_empty(); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void as352x_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p =(u32 *)buf; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isempty()); + p[i] = rreg32( NAF_FIFODATA ); + } + as352x_nand_wait_fifo_empty( ); +} +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != as352x_nand_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void as352x_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + + struct nand_chip *this = mtd->priv; +// ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + switch (cmd) + { + case NAND_CTL_SETCLE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE ); + } + break; + case NAND_CTL_CLRCLE: + clr_reg_bits16( NAF_MODE, NAF_MODE_CLE ); + break; + case NAND_CTL_SETALE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE ); + + } + break; + case NAND_CTL_CLRALE: + clr_reg_bits16( NAF_MODE, NAF_MODE_ALE ); + break; + case NAND_CTL_SETNCE: + set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_CLRNCE: + clr_reg_bits16( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_SETWP: + set_reg_bits16 ( NAF_MODE, NAF_MODE_WP ); + break; + case NAND_CTL_CLRWP: + clr_reg_bits16( NAF_MODE, NAF_MODE_WP ); + break; + + } +} +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ + +static void as352x_nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + as352x_read_status =0; + switch (command) + { + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + { + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + } + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + { + this->hwcontrol(mtd, NAND_CTL_SETWP); + } + break; + case NAND_CMD_READ0: + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC); + default: + this->hwcontrol(mtd, NAND_CTL_CLRWP); + } + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_SEQIN: + { + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET ); + break; + } + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + as352x_read_status =1; + break; + case NAND_CMD_CACHEDPROG: + + case NAND_CMD_PAGEPROG: + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC ); + break; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (1000); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + + +void board_nand_init(struct nand_chip *nand) +{ + // clear all NAF chip select bits + clr_reg_bits32( CCU_IO , ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1 + | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3 ) ); + set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 ); + + /* configure NAF */ + wreg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */ + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */ + + /* configure fifo on but dma still off */ + wreg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG ); + + /* 2. change into read mode */ + wreg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC ); + + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = as352x_nand_hwcontrol; + nand->dev_ready = as352x_nand_ready; + nand->chip_delay = 18; + nand->read_byte = as352x_nand_read_byte; + nand->write_byte = as352x_nand_write_byte; + nand->read_buf = as352x_nand_read_buf; + nand->write_buf = as352x_nand_write_buf; + nand->cmdfunc = as352x_nand_command_lp; +} +#endif diff -urN u-boot-1.1.6.org/board/as352xpb/u-boot.lds u-boot-1.1.6/board/as352xpb/u-boot.lds --- u-boot-1.1.6.org/board/as352xpb/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/u-boot.lds 2006-11-23 16:27:49.000000000 +0800 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm922t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -urN u-boot-1.1.6.org/common/env_nand.c u-boot-1.1.6/common/env_nand.c --- u-boot-1.1.6.org/common/env_nand.c 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/common/env_nand.c 2006-11-30 09:35:19.000000000 +0800 @@ -162,9 +162,13 @@
if(gd->env_valid == 1) { puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) - return 1; +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; +#endif puts ("Writing to redundant Nand... "); ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, (u_char*) env_ptr); @@ -192,9 +196,13 @@ int ret = 0;
puts ("Erasing Nand..."); +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) return 1; - +#endif puts ("Writing to Nand... "); total = CFG_ENV_SIZE; ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c 2006-12-01 17:43:30.000000000 +0800 @@ -0,0 +1,196 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger mgroeger@sysgo.de +* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Alex Zuepke azu@sysgo.de +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, gj@denx.de +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <arm922t.h> +#include <as352x.h> + +#if defined(CONFIG_AS352X) +#define TIMER_LOAD_VAL 0xffffffff +static ulong timestamp; +static ulong lastdec; +#define CFG_TIMER_INTERVAL 1500000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL) + +int interrupt_init (void) +{ + u32 val = rreg32(CGU_REG_PERI); + + wreg32(val|CGU_TIMER1_CLOCK_ENABLE ,CGU_REG_PERI); + + /* + * Initialise to a known state (all timers off) + */ + wreg32(TIMER_CONTROL,0); + wreg32(TIMER_CONTROL,0); + + wreg32(TIMER_INTCLR,1); + wreg32(TIMER_INTCLR,1); + + wreg32(TIMER_LOAD,CFG_TIMER_RELOAD ); + wreg32(TIMER_VALUE,CFG_TIMER_RELOAD); + + wreg32(TIMER_CONTROL,TIMER_PRESCALE_1 | TIMER_ENABLE |TIMER_32_BIT ); + + reset_timer_masked(); + return (0); +} + + + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = rreg32(TIMER_VALUE); /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = rreg32(TIMER_VALUE); /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* +* This function is derived from PowerPC code (read timebase as long long). +* On ARM it just returns the timer value. +*/ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + + +/* +* reset the cpu by setting up the watchdog timer and let him time out +*/ +void reset_cpu (ulong ignored) +{ + + /* Disable watchdog */ + + /* Initialize watchdog timer count register */ + + /* Enable watchdog timer; assert reset at timer timeout */ + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_AS352X) */
Thomas,
in message 2ECBC2365E331640B5BC8FBE829192A3013B586F@SUX2119.office.amsiag.com you wrote:
U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 1:
I told you before that your mailer is wrapping long lines, which corrupts your patches. And you just did it again:
...
+/* For sake of completness and for easier exchanging of round-up and round-down
^^^^^^^^^^^^
+divisions provide also a round-down macro */
+#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b))
+/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A)))
+/* ------------------------defines for Dynamic Mem --------------------------- */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ...
+#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 )
+/* ------------------ MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM --------------------------- */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is not usable:
-> patch -p1 --dry-run </tmp/patch patching file board/as352xpb/as352xpb.c patch: **** malformed patch at line 48: */
All your patches are corrupted. AND I TOLD YOU BEFORE.
Rejected.
Best regards,
Wolfgang Denk
Dear Wolfgang: i'm so sorry, i didn't care about the mailer. i will send it by gmail. Br Thomas 2006/12/1, Luo Thomas Thomas.Luo@austriamicrosystems.com:
From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 1: Br
Signed-off-by: Thomas Luo
diff -urN u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-01 17:44:42.000000000 +0800 @@ -0,0 +1,359 @@ +/*
From:thomas.luo@ieee.org U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525.... Part 1: Br
Signed-off-by: Thomas Luothomas.luo@austriamicrosystems.com
-------------------------------------------------------------------------------
diff -urN u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-01 17:44:42.000000000 +0800 @@ -0,0 +1,359 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Macro introduced to compensate for no support for floating point +division operation in the processor. So to get the correct value, +roundup is peformed to provide accurate results for certain conditions. */ + +#define DIVIDE_AND_ROUND_UP(dividend,divisor) \ + ( ( (dividend) + (divisor) - 1 ) / (divisor) ) + +/* For sake of completness and for easier exchanging of round-up and round-down +divisions provide also a round-down macro */ + +#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b)) + +/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A))) + +/* ------------------------defines for Dynamic Mem --------------------------- */ +#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset) + +#define AS352X_MPMC_CONTROL AS352X_SDRAM_BASE_ADDR( 0x00 ) +#define AS352X_MPMC_CONFIG AS352X_SDRAM_BASE_ADDR( 0x08 ) +#define AS352X_MPMC_DYRDCFG AS352X_SDRAM_BASE_ADDR( 0x28 ) +#define AS352X_MPMC_DYTRP AS352X_SDRAM_BASE_ADDR( 0x30 ) +#define AS352X_MPMC_DYTRAS AS352X_SDRAM_BASE_ADDR( 0x34 ) +#define AS352X_MPMC_DYTSREX AS352X_SDRAM_BASE_ADDR( 0x38 ) +#define AS352X_MPMC_DYTAPR AS352X_SDRAM_BASE_ADDR( 0x3C ) +#define AS352X_MPMC_DYTDAL AS352X_SDRAM_BASE_ADDR( 0x40 ) +#define AS352X_MPMC_DYTWR AS352X_SDRAM_BASE_ADDR( 0x44 ) +#define AS352X_MPMC_DYTRC AS352X_SDRAM_BASE_ADDR( 0x48 ) +#define AS352X_MPMC_DYTRFC AS352X_SDRAM_BASE_ADDR( 0x4C ) +#define AS352X_MPMC_DYTXSR AS352X_SDRAM_BASE_ADDR( 0x50 ) +#define AS352X_MPMC_DYTRRD AS352X_SDRAM_BASE_ADDR( 0x54 ) +#define AS352X_MPMC_DYTMRD AS352X_SDRAM_BASE_ADDR( 0x58 ) +#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104 ) +#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100 ) +#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 ) + +/* ------------------ MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM --------------------------- */ +#define MPMC_DY_TRP_IN_NS 20 +//#define MPMC_DY_TRP_IN_NS 10 + +#define MPMC_CLK_IN_MHZ_MIN 20 +#define MPMC_1_CLKCYCLE_IN_NS_MIN 50 + +#define MPMC_CLK_IN_MHZ 66 +//#define MPMC_CLK_IN_MHZ 24 +#if MPMC_CLK_IN_MHZ == 24 +#define MPMC_1_CLKCYCLE_IN_NS 42 +#elif MPMC_CLK_IN_MHZ == 66 +#define MPMC_1_CLKCYCLE_IN_NS 16 +#else +#define MPMC_1_CLKCYCLE_IN_NS 16 +#endif + +//#define MPMC_SDRAM_TCK_IN_NS 20 +#define MPMC_SDRAM_TCK_IN_NS 10 + +#define MPMC_DY_TRAS_MIN_IN_NS 50 +#define MPMC_DY_TRAS_IN_NS MPMC_DY_TRAS_MIN_IN_NS + +/* tAPR not available for micron MT48LC4M16A2 SDRAM */ +#define MPMC_DY_TAPR_INNS 0 + +#define MPMC_DY_TDAL_IN_NS (5 * (MPMC_SDRAM_TCK_IN_NS)) + +/* tWR can be minimum 15ns or 1CLK * 7ns */ +#define MPMC_DY_TWR_IN_NS (MPMC_1_CLKCYCLE_IN_NS + 8) +#define MPMC_DY_TRC_IN_NS 70 + +#define MPMC_DY_TRFC_INNS 70 + +#define MPMC_DY_TXSR_IN_NS 80 + +#define MPMC_DY_TRRD_IN_NS 20 +#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS)) + +#define MPMC_SDRAM_CAS 0x2 +#define MPMC_SDRAM_RAS 0x2 /* hha??? */ + +/* Low Power device bit settings */ +/* Device Type for APP Board 2.0 and 1.0 */ +/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power */ +#define MPMC_SDRAM_DEVICE_TYPE (0 << 3) + +/*ROW and COLUMN size mapping for mpmc SoC device */ + +/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#define MPMC_SDRAM_ADDR_MAPPING (0x11 << 7) + +#define MPMC_SDRAM_32BIT_EXTBUS (0 <<14) +#define MPMC_SDRAM_BUFFER_DISABLE (0 <<19) +#define MPMC_SDRAM_BUFFER_ENABLE (1 <<19) +#define MPMC_SDRAM_WP_ENABLE (0 <<20) + +#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \ + (MPMC_SDRAM_ADDR_MAPPING) | \ + (MPMC_SDRAM_32BIT_EXTBUS) | \ + (MPMC_SDRAM_BUFFER_DISABLE) | \ + (MPMC_SDRAM_WP_ENABLE)) + +#define MPMC_SDRAM_START_2_REF_CYCLES 2 +/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +/*64ms divided by 8192 */ +#define MPMC_SDRAM_tREF_inNs 7812 + + +#define MPMC_SDRAM_DYNAMIC_REF ((MPMC_SDRAM_tREF_inNs) / (MPMC_1_CLKCYCLE_IN_NS_MIN)) + + + +/* CAS Latency for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#if MPMC_SDRAM_CAS == 2 +#define MPMC_SDRAM_MODEVALUE (0x23 << 13) +#else +#define MPMC_SDRAM_MODEVALUE (0x33 << 13) +#endif + +/* ----------------------------------- functions --------------------------- */ + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} +void sdram_init(void ) +{ + volatile u32 Temp; + + + + *(volatile u32 *)AS352X_MPMC_CONTROL = 0x00000001; + + *(volatile u32 *)(AS352X_MPMC_CONFIG) = 0x00000000; + + *(volatile u32 *)(AS352X_MPMC_DYRDCFG) = 0x00000001; + + /* MPMCDynamicRP setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRP) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRP_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)) ; + + /* MPMCDytRAS setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRAS) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRAS_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamicSREX */ + *(volatile u32 *)(AS352X_MPMC_DYTSREX) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictAPR */ + *(volatile u32 *)(AS352X_MPMC_DYTAPR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TAPR_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + *(volatile u32 *)(AS352X_MPMC_DYTDAL) = + (1+(DIVIDE_AND_ROUND_UP((MPMC_DY_TDAL_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)))); + + /* Setup MPMCDynamictWR */ + *(volatile u32 *)(AS352X_MPMC_DYTWR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TWR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRC */ + *(volatile u32 *)(AS352X_MPMC_DYTRC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRC_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRFC */ + *(volatile u32 *)(AS352X_MPMC_DYTRFC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRFC_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictXSR */ + *(volatile u32 *)(AS352X_MPMC_DYTXSR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRRD */ + *(volatile u32 *)(AS352X_MPMC_DYTRRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictMRD */ + *(volatile u32 *)(AS352X_MPMC_DYTMRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TMRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + + *(volatile u32 *)(AS352X_MPMC_DYRASCAS0) = + ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS)); + + + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG; + + /*wait for 200uS by performing dummy read operation which consumes two */ + /* clock cycles for each operation */ + delay(50); + + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000183; /* apply NOP */ + + delay(1); + + /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000103; + + delay(100); + + /* start two auto refresh */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_START_2_REF_CYCLES ; + + /*- wait for 64 clk cycles of HCLK-*/ + delay(128); + + /* Program the operational value of the Refresh cycles, depending upon the + device specified period */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_DYNAMIC_REF / 16; + + /* Send the Mode set command to SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000083; + + /*----------------------------------------------------------------------*/ + + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_MODEVALUE) ; + + /* Merged with S.U. */ +#ifdef SDRAM_MT48H8M16LF + /* Device Type for APP Board 2.0 (MT48H8M16LF - 128Mbit - Low Power) */ + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE) ; +#endif /*SDRAM_MT48H8M16LF*/ + + /*----------------------------------------------------------------------*/ + /* Send the Normal mode set command to the SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000003; + + /* Enable the buffer for the SDRAM */ + Temp = *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) ; + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = + Temp | (MPMC_SDRAM_BUFFER_ENABLE); + +} +#define CCU_COUNT_MIN_10_MICROSEC 640 +/* +* Miscellaneous platform dependent initialisations +*/ + +void ccu_reset_device +( u32 deviceMask + ) +{ + int i; + + /* reset devices */ + wreg32( CCU_SRC, deviceMask ); + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + + /* hold the reset for at least 10 microseconds */ + for ( i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i-- ) + { + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + } + + /* remove lock */ + wreg32( CCU_SRL, 0 ); + wreg32( CCU_SRC, 0 ); +} + +void clk_set_async_mode() +{ + unsigned long i; + /* read CP15 register 1 into r0*/ + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); + /*enable asynchronous clocking mode*/ + asm("orr r0, %0, #(0x3 <<30) ": :"r"(i)); + /* write cp15 register 1*/ + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); +} + + +int board_init (void) +{ + ccu_reset_device( CCU_RESET_ALL_BUT_MEMORY ); + + wreg32(CGU_REG_PERI, 0x0F802000); + wreg32(CGU_REG_PROC,0); + wreg32(CGU_REG_AUDIO,0); + wreg32(CGU_REG_USB,0); + wreg32(CGU_REG_INTCTRL,0); + + wreg32(CGU_REG_COUNTA,0); + wreg32(CGU_REG_COUNTB,0); + wreg32(CGU_REG_IDE,0); + wreg32(CGU_REG_MEMSTICK,0); + wreg32(CGU_REG_DBOP,0); + + + wreg32(CGU_REG_PLLASUP,0x8); + wreg32(CGU_REG_PLLBSUP,0x8); + + wreg32(CGU_REG_PLLA,0); + wreg32(CGU_REG_PLLB,0); + + clk_set_async_mode(); + //set cpu and bus default clock + //plla 384M, CPU 192M,mpmc 64M,pclk 64M + + wreg32(CGU_REG_PLLA,0x2630); + wreg32(CGU_REG_PLLASUP,0); + wreg32(CGU_REG_COUNTA,CGU_LOCK_CNT); + while (!(rreg32(CGU_REG_INTCTRL)&1)) ; + + wreg32( CGU_REG_PROC, 0x011); + wreg32(CGU_REG_PERI,0x0EF2E295); + + + + //ccuResetDevice( CCU_RESET_ALL_BUT_MEMORY ); + + /* arch number of AS352X-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AS352X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + sdram_init(); + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff -urN u-boot-1.1.6.org/board/as352xpb/config.mk u-boot-1.1.6/board/as352xpb/config.mk --- u-boot-1.1.6.org/board/as352xpb/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/config.mk 2006-11-24 10:08:10.000000000 +0800 @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# David Mueller, ELSOFT AG, d.mueller@elsoft.ch +# +# AMS AS352XPB board with AS352X (ARM922T) cpu +# +# see http://www.austriamicrosystems.com for more information +# +# +# AS352X has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 0000'0000 +# +# download area is 3300'0000 +# + +TEXT_BASE = 0x00000000 diff -urN u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S u-boot-1.1.6/board/as352xpb/lowlevel_init.S --- u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/lowlevel_init.S 2006-11-30 10:24:49.000000000 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +/* some parameters for the board */ + +/* + * + */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ diff -urN u-boot-1.1.6.org/board/as352xpb/Makefile u-boot-1.1.6/board/as352xpb/Makefile --- u-boot-1.1.6.org/board/as352xpb/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/Makefile 2006-11-29 16:02:27.000000000 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := as352xpb.o nandas.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -urN u-boot-1.1.6.org/board/as352xpb/nandas.c u-boot-1.1.6/board/as352xpb/nandas.c --- u-boot-1.1.6.org/board/as352xpb/nandas.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/nandas.c 2006-12-01 17:47:46.000000000 +0800 @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <asm/errno.h> +/* + * hardware specific access to control-lines + */ + +#define NAF_X8_X16_CODE 0x03 /* only for big block nand */ + +/** + * Power bit in NAF mode register. + **/ +#define NAF_POWER_ON 0x0C +#define NAF_POWER_OFF 0x00 + +/** + * NAF Config register bits. + **/ +#define NAF_X16 0x00000001 +#define NAF_FIFO_ENABLE 0x00000004 +#define NAF_DMA_ON 0x00000008 + +#define NAF_READ_STROBE_H 0x00000020 /* read strobe high is 4 PLCK cycles */ +#define NAF_READ_STROBE_L 0x00000400 /* read strobe low is 5 PLCK cycles */ +#define NAF_WRITE_STROBE_H 0x00003000 /* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_L 0x00040000 /* write strobe high is 4 PCLK cycles */ + +#define NAF_STROBE_CONFIG \ + ( NAF_READ_STROBE_H | NAF_READ_STROBE_L | NAF_WRITE_STROBE_H | NAF_WRITE_STROBE_L ) + + +/** + * NAF modi + **/ +#define NAF_MODE_CLE 1<<0 +#define NAF_MODE_ALE 1<<1 +#define NAF_MODE_NCE 1<<4 +#define NAF_MODE_WP 1<<7 + +#define NAF_MODE_DATA_READ_NO_ECC 0x14 +#define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4 +#define NAF_MODE_DATA_WRITE_NO_ECC 0x94 +/* + * chip R/B detection + */ +static int as352x_read_status; + +static int as352x_nand_ready(struct mtd_info *mtd) +{ + return ( ( rreg16( NAF_STATUS ) & 0x0080 ) == 0x0080 ); + +} +static int as352x_nand_strobe() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0100 ) == 0x0100 ); +} +static int as352x_fifo_isfull() +{ + return ( ( rreg16( NAF_STATUS ) & 0x01000 ) ); +} + +static int as352x_fifo_isempty() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0200 ) ); +} +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char as352x_nand_read_byte(struct mtd_info *mtd) +{ + u_char data; + wreg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */ + while (!as352x_nand_strobe(mtd)); + data = rreg16( NAF_DATA ); + if (as352x_read_status) + data |= 0x80; + return data; +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void as352x_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + + wreg16( NAF_DATA, byte ); + while (!as352x_nand_strobe(mtd)); +} + +void as352x_nand_wait_fifo_empty( ) +{ + while ( ( rreg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; /* wait for got empty and ready */ +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void as352x_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + u32 *p =(u32 *)buf; + struct nand_chip *this = mtd->priv; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isfull()); + wreg32( NAF_FIFODATA, p[i] ); + } + as352x_nand_wait_fifo_empty(); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void as352x_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p =(u32 *)buf; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isempty()); + p[i] = rreg32( NAF_FIFODATA ); + } + as352x_nand_wait_fifo_empty( ); +} +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != as352x_nand_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void as352x_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + + struct nand_chip *this = mtd->priv; +// ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + switch (cmd) + { + case NAND_CTL_SETCLE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE ); + } + break; + case NAND_CTL_CLRCLE: + clr_reg_bits16( NAF_MODE, NAF_MODE_CLE ); + break; + case NAND_CTL_SETALE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE ); + + } + break; + case NAND_CTL_CLRALE: + clr_reg_bits16( NAF_MODE, NAF_MODE_ALE ); + break; + case NAND_CTL_SETNCE: + set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_CLRNCE: + clr_reg_bits16( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_SETWP: + set_reg_bits16 ( NAF_MODE, NAF_MODE_WP ); + break; + case NAND_CTL_CLRWP: + clr_reg_bits16( NAF_MODE, NAF_MODE_WP ); + break; + + } +} +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ + +static void as352x_nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + as352x_read_status =0; + switch (command) + { + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + { + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + } + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + { + this->hwcontrol(mtd, NAND_CTL_SETWP); + } + break; + case NAND_CMD_READ0: + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC); + default: + this->hwcontrol(mtd, NAND_CTL_CLRWP); + } + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_SEQIN: + { + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET ); + break; + } + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + as352x_read_status =1; + break; + case NAND_CMD_CACHEDPROG: + + case NAND_CMD_PAGEPROG: + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC ); + break; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (1000); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + + +void board_nand_init(struct nand_chip *nand) +{ + // clear all NAF chip select bits + clr_reg_bits32( CCU_IO , ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1 + | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3 ) ); + set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 ); + + /* configure NAF */ + wreg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */ + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */ + + /* configure fifo on but dma still off */ + wreg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG ); + + /* 2. change into read mode */ + wreg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC ); + + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = as352x_nand_hwcontrol; + nand->dev_ready = as352x_nand_ready; + nand->chip_delay = 18; + nand->read_byte = as352x_nand_read_byte; + nand->write_byte = as352x_nand_write_byte; + nand->read_buf = as352x_nand_read_buf; + nand->write_buf = as352x_nand_write_buf; + nand->cmdfunc = as352x_nand_command_lp; +} +#endif
Thomas,
in message 008a01c7161f$48904480$6507a8c0@228fd4981e4b4dc you wrote:
From:thomas.luo@ieee.org U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525.... Part 1:
This is the third time you are submitting this. And it is the third time I have to ask you to clean up your code before posting.
Did you bother to read my messages? Do you remember this:
------- Forwarded Message
Date: Fri, 01 Dec 2006 10:19:35 +0100 From: Wolfgang Denk wd@denx.de To: "Luo Thomas" Thomas.Luo@austriamicrosystems.com Subject: Re: [Patch]U-Boot1.1.6 for AS352X
... First, you should clean up your code and fix at least the following problems: ... * You violate the coding style in *many* places (indentation, C++ comments, indentation not by TABs, trailing white space, line length, brace style, ...) ...
------- End of Forwarded Message
I hereby reject your patch(es) because you did not clean up these problems.
Best regards,
Wolfgang Denk
From:thomas.luo@ieee.org U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525.... Part 3: Br
Signed-off-by: Thomas Luothomas.luo@austriamicrosystems.com
-------------------------------------------------------------------------------
diff -urN u-boot-1.1.6.org/include/arm922t.h u-boot-1.1.6/include/arm922t.h --- u-boot-1.1.6.org/include/arm922t.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/arm922t.h 2006-11-23 16:30:48.000000000 +0800 @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm922t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM922T_H__ +#define __ARM922T_H__ + + +#endif /*__ARM922T_H__*/ diff -urN u-boot-1.1.6.org/include/as352x.h u-boot-1.1.6/include/as352x.h --- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/as352x.h 2006-12-01 17:42:16.000000000 +0800 @@ -0,0 +1,352 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#ifndef __AS352X_H__ +#define __AS352X_H__ + +#define AS352X_UART_CHANNELS 1 + +/* AS352X only supports 512 Byte HW ECC */ +#define AS352X_ECCSIZE 512 +#define AS352X_ECCBYTES 3 + + +/* AS352X device base addresses */ + + +/* ------------------------------------------------------------------------ +* AS352X Registers +* ------------------------------------------------------------------------ +* +*/ + + +/* AHB */ +#define AS352X_USB_BASE 0xC6000000 +#define AS352X_VIC_BASE 0xC6010000 +#define AS352X_DMAC_BASE 0xC6020000 +#define AS352X_MPMC_BASE 0xC6030000 +#define AS352X_MEMSTICK_BASE 0xC6040000 +#define AS352X_CF_IDE_BASE 0xC6050000 + +/* APB */ +#define AS352X_NAND_FLASH_BASE 0xC8000000 +#define AS352X_BIST_MANAGER_BASE 0xC8010000 +#define AS352X_SD_MCI_BASE 0xC8020000 +#define AS352X_TIMER_BASE 0xC8040000 +#define AS352X_WDT_BASE 0xC8050000 +#define AS352X_I2C_MS_BASE 0xC8060000 +#define AS352X_I2C_AUDIO_BASE 0xC8070000 +#define AS352X_SSP_BASE 0xC8080000 +#define AS352X_I2SIN_BASE 0xC8090000 +#define AS352X_I2SOUT_BASE 0xC80A0000 +#define AS352X_GPIO1_BASE 0xC80B0000 +#define AS352X_GPIO2_BASE 0xC80C0000 +#define AS352X_GPIO3_BASE 0xC80D0000 +#define AS352X_GPIO4_BASE 0xC80E0000 +#define AS352X_CGU_BASE 0xC80F0000 +#define AS352X_CCU_BASE 0xC8100000 +#define AS352X_UART0_BASE 0xC8110000 +#define AS352X_DBOP_BASE 0xC8120000 + + + + + + + + +/* ------------------------------------------------------------------------ +* AS352X control registers +* ------------------------------------------------------------------------ +*/ + +#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00) +#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04) +#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08) +#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C) +#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10) +#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14) + + +/** +* Reset Control Lines in CCU_SRC register +**/ +#define CCU_SRC_DBOP_EN ( 1 << 24 ) +#define CCU_SRC_SPDIF_EN ( 1 << 22 ) +#define CCU_SRC_TIMER_EN ( 1 << 21 ) +#define CCU_SRC_SSP_EN ( 1 << 20 ) +#define CCU_SRC_WDO_EN ( 1 << 19 ) +#define CCU_SRC_IDE_EN ( 1 << 18 ) +#define CCU_SRC_IDE_AHB_EN ( 1 << 17 ) +#define CCU_SRC_UART0 ( 1 << 16 ) +#define CCU_SRC_NAF_EN ( 1 << 15 ) +#define CCU_SRC_SDMCI_EN ( 1 << 14 ) +#define CCU_SRC_GPIO_EN ( 1 << 13 ) +#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 ) +#define CCU_SRC_I2C_EN ( 1 << 11 ) +#define CCU_SRC_MST_EN ( 1 << 10 ) +#define CCU_SRC_I2SIN ( 1 << 9 ) +#define CCU_SRC_I2SOUT ( 1 << 8 ) +#define CCU_SRC_USB_AHB_EN ( 1 << 7 ) +#define CCU_SRC_USB_PHY_EN ( 1 << 6 ) +#define CCU_SRC_DMAC_EN ( 1 << 5 ) +#define CCU_SRC_VIC_EN ( 1 << 4 ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART0 ( 1 << 0 ) + + +#define CCU_RESET_ALL_BUT_MEMORY \ + ( CCU_SRC_DBOP_EN \ + | CCU_SRC_SPDIF_EN \ + | CCU_SRC_TIMER_EN \ + | CCU_SRC_SSP_EN \ + | CCU_SRC_WDO_EN \ + | CCU_SRC_IDE_EN \ + | CCU_SRC_IDE_AHB_EN \ + | CCU_SRC_UART0 \ + | CCU_SRC_NAF_EN \ + | CCU_SRC_SDMCI_EN \ + | CCU_SRC_GPIO_EN \ + | CCU_SRC_I2C_AUDIO_EN \ + | CCU_SRC_I2C_EN \ + | CCU_SRC_MST_EN \ + | CCU_SRC_I2SIN \ + | CCU_SRC_I2SOUT \ + | CCU_SRC_USB_AHB_EN \ + | CCU_SRC_USB_PHY_EN \ + | CCU_SRC_DMAC_EN \ + | CCU_SRC_VIC_EN \ + ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART ( 1 << 0 ) +/* ------------------------------------------------------------------------ +* AS352X clock control registers +* ------------------------------------------------------------------------ +*/ + +#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 ) +#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 ) +#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 ) +#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C ) +#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 ) +#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 ) +#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 ) +#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C ) +#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 ) +#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 ) +#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 ) +#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C ) +#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 ) +#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 ) +#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 ) + + +/* --- are disabled after reset --- */ +#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */ +#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */ +#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */ +#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */ +#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c master/slave */ +#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio master */ +#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */ +#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */ +#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */ +#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */ +#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog counter */ +#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog timer module */ +#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */ +#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */ +#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */ +#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer interface */ + +/** ------------------------------------------------------------------ +* Number of cycles to wait before cgu is safely locked. +**/ +#define CGU_LOCK_CNT 0xFF + +/* FIFO depth is 16 for tx and rx fifo */ +#define UART_FIFO_DEPTH 16 + +/* ------------------- UART Line Control Register bit fields -------------------- */ + +#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */ + + +/* -------------- UART Interrupt Control Register bit fields --------------- */ + +#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */ +#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */ +#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */ + +/* ------------------- UART Line Status Register bit fields -------------------- */ + +#define UART_ERRORBITS 0x1E +#define UART_RX_DATA_READY (1 << 0) +#define UART_TX_HOLD_REG_EMPTY (1 << 5) + +/* ------------------- FIFO CNTL Register contants -------------------*/ + +#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */ +#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */ +#define UART_RX_FIFO_RST (1 << 2) +#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */ +#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */ +#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */ +#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */ + + +/* ------------------- FIFO status Register contants ------------------*/ +#define UART_TX_FIFO_FULL (1 << 0) +#define UART_RX_FIFO_FULL (1 << 1) +#define UART_TX_FIFO_EMPTY (1 << 2) +#define UART_RX_FIFO_EMPTY (1 << 3) + + +/* ----------------------- defines ---------------------------------------- */ + +#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Data register */ +#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Clock divider(lower byte) register */ +#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Clock divider(higher byte) register */ +#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Interrupt enable register */ +#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) /* Interrupt status register */ +#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo control register */ +#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo status register */ +#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) /* Line control register */ +#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) /* Line status register */ + + +#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) /* 32-bit width */ +#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) /* 32 bit width */ +#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) /* 8 bit width */ +#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) /* clears ir by write access */ +#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) /* 1 bit width */ +#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) /* 1 bit width */ + +/** +* Counter/Timer control register bits +**/ +#define TIMER_ENABLE 0x80 +#define TIMER_PERIODIC 0x40 +#define TIMER_INT_ENABLE 0x20 +#define TIMER_32_BIT 0x02 +#define TIMER_ONE_SHOT 0x01 +#define TIMER_PRESCALE_1 0x00 +#define TIMER_PRESCALE_16 0x04 +#define TIMER_PRESCALE_256 0x08 + + + +#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 ) +#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 ) +#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 ) +#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C ) +#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 ) +#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 ) +#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 ) +#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C ) +#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 ) +#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 ) +#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 ) + + + +#define set_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) ) + + +#define clr_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) ) ) ) + +#define rreg32( registerAddress ) \ + ( *( ( const volatile u32 * )( registerAddress ) ) ) + +#define wreg32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) ) + + + +#define rreg16( registerAddress ) \ + ( *( ( const volatile u16 * )( registerAddress ) ) ) + +#define wreg16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) ) + +#define set_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) ) + +#define clr_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) ) ) ) + + +#define rreg8( registerAddress ) \ + ( *( ( const volatile u8 * )( registerAddress ) ) ) + +#define wreg8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) ) + +#define set_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) ) + +#define clr_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) ) ) +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__AS352X_H__*/ diff -urN u-boot-1.1.6.org/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01 17:49:35.000000000 +0800 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01 18:01:45.000000000 +0800 @@ -737,6 +737,7 @@ #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AS352X 1166
#ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6054,7 +6055,7 @@ # define machine_is_ess710() (0) #endif
-#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type @@ -9401,6 +9402,18 @@ #else # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif +
/* * These have not yet been registered diff -urN u-boot-1.1.6.org/include/configs/as352xpb.h u-boot-1.1.6/include/configs/as352xpb.h --- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-01 17:42:50.000000000 +0800 @@ -0,0 +1,218 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +* (easy to change) +*/ +#define CONFIG_ARM922T 1 /* This is an ARM922T Core */ +#define CONFIG_AS352X 1 /* in a AS352X SoC */ +#define CONFIG_AS352XPB 1 /* on a AS352XPB Board */ +#define CFG_NO_FLASH 1 + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 24000000/* the AS352XPB has 24MHz input clock */ + + +#define USE_922T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* +* Size of malloc() pool +*/ +#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1) /0x4000)*0x4000) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* +* Hardware drivers +*/ + +/* +* select serial console configuration +*/ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB */ + +/************************************************************ +* RTC +************************************************************/ +#define CONFIG_RTC_AS352X 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** +* Command definition +***********************************************************/ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + /* CFG_CMD_CACHE |*/ \ + CFG_CMD_NAND | \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO \ + /*CFG_CMD_ELF*/ )& ~(CFG_CMD_FLASH|CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG)) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc console=ttyS0 mem=64M" +#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000; nand read 0x32000000 0x280000 0x200000;bootm 0x30007FC0 0x32000000" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +/*#define CONFIG_NETMASK 255.255.255.0*/ +/*#define CONFIG_IPADDR 10.0.0.110*/ +/*#define CONFIG_SERVERIP 10.0.0.1*/ +/*#define CONFIG_BOOTFILE "" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +#undef CFG_ENV_IS_IN_FLASH +/* +* Miscellaneous configurable options +*/ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "AS352X # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x30008000 /* default load address */ + +#define CFG_HZ 1500000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ENV_IS_IN_NAND 1 + +#define CFG_ENV_NAND_ERASE_SIZE 0x20000 +#define CFG_ENV_SIZE 0x800 /* Total Size of Environment Sector */ +#if CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 + +#endif +/*----------------------------------------------------------------------- +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- +* FLASH and environment organization +*/ + +#define CONFIG_AMD_LV400 0 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + + +#define NAND_DISABLE_CE(nand) do { } while(0) +#define NAND_ENABLE_CE(nand) do { } while(0) + +#define NAND_WAIT_READY(nand) + +#define WRITE_NAND_COMMAND(d, adr) do{ } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0) +#define WRITE_NAND(d, adr) do{} while(0) +#define READ_NAND(adr) () +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + + + + + + +#include <as352x.h> +#define CFG_NAND_BASE NAF_DATA +#include <cmd_confdefs.h> + +#define NAND_ALLOW_ERASE_ALL + + + +#endif /* __CONFIG_H */ diff -urN u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS --- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAINTAINERS 2006-11-30 09:40:51.000000000 +0800 @@ -566,6 +566,17 @@ Haavard Skinnemoen hskinnemoen@atmel.com
ATSTK1000 AT32AP7000 +######################################################################### +# AS352X Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Thomas Luo thomas.luo@austriamicrosystems.com + + AS352XPB AS352X +
######################################################################### # End of MAINTAINERS list # diff -urN u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL --- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAKEALL 2006-11-30 09:33:22.000000000 +0800 @@ -189,13 +189,13 @@ LIST_ARM9=" \ at91rm9200dk cmc_pu2 \ ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ + ap966 cp920t cp922t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue as3525pb \ "
######################################################################### diff -urN u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/Makefile 2006-11-30 09:38:22.000000000 +0800 @@ -2253,6 +2253,9 @@ @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
######################################################################### +as352xpb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x + ######################################################################### #########################################################################
participants (4)
-
Luo Thomas -
luo thomas -
thomas -
Wolfgang Denk