[U-Boot] [PATCH] sifive: riscv: streamline HiFive Unleashed configuration infrastructure
This patch is intended to update the current configuration implementation of HiFive Unleashed board so that it is as per the guidelines provided in U-boot's doc/README.kconfig. The board has a FU540-C000 SoC built around U54-MC Core complex.
This patch is based on the commit 75551c8bfc95 ("Merge branch '2019-07-26-ti-imports'") in master branch of repo[1] and is tested with OpenSBI to use the dtb passed as argument in FW_PAYLOAD_FDT_PATH from the mainline kernel and boot's linux image over tftp. The patch is available for testing at dev/sagark/sifive_u540defconfig branch here [2].
[1] http://git.denx.de/u-boot-riscv.git [2] https://github.com/sagsifive/u-boot
Summary: -Update TARGET in board select menu. -Update SYS_CPU from generic to u54-mc. -Added SYS_SOC. -Update SYS_BOARD from fu540 to hifive_unleashed. -Update SYS_CONFIG_NAME from sifive-u540 to hifive_unleashed . -Update MAINTAINERS file with relevant entries corresponding to the above changes.
This patch will conflict with few patches which are already submitted for review, it would be good if U-boot folks would suggest something accordingly.
Sagar Shrikant Kadam (1): sifive: riscv: update Hifive Unleashed configuration infrastructure
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com --- arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8cfc7d0..82891fd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -17,7 +17,7 @@ config TARGET_MICROCHIP_ICICLE config TARGET_QEMU_VIRT bool "Support QEMU Virt Board"
-config TARGET_SIFIVE_FU540 +config TARGET_SIFIVE_HIFIVE_UNLEASHED bool "Support SiFive FU540 Board"
endchoice @@ -52,11 +52,11 @@ config SPL_SYS_DCACHE_OFF source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" -source "board/sifive/fu540/Kconfig" +source "board/sifive/hifive_unleashed/Kconfig"
# platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" -source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/u54-mc/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig deleted file mode 100644 index 1d6ab50..0000000 --- a/arch/riscv/cpu/generic/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com - -config GENERIC_RISCV - bool - select ARCH_EARLY_INIT_R - imply CPU - imply CPU_RISCV - imply RISCV_TIMER - imply SIFIVE_CLINT if RISCV_MMODE - imply CMD_CPU diff --git a/arch/riscv/cpu/generic/Makefile b/arch/riscv/cpu/generic/Makefile deleted file mode 100644 index 258e462..0000000 --- a/arch/riscv/cpu/generic/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com - -obj-y += dram.o -obj-y += cpu.o diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c deleted file mode 100644 index ad2950c..0000000 --- a/arch/riscv/cpu/generic/cpu.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com - */ - -#include <common.h> -#include <dm.h> - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} - -/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ -static const struct udevice_id riscv_virtio_soc_ids[] = { - { .compatible = "riscv-virtio-soc" }, - { } -}; - -U_BOOT_DRIVER(riscv_virtio_soc) = { - .name = "riscv_virtio_soc", - .id = UCLASS_SIMPLE_BUS, - .of_match = riscv_virtio_soc_ids, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c deleted file mode 100644 index b7b1207..0000000 --- a/arch/riscv/cpu/generic/dram.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com - */ - -#include <common.h> -#include <fdtdec.h> -#include <linux/sizes.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -ulong board_get_usable_ram_top(ulong total_size) -{ -#ifdef CONFIG_64BIT - /* - * Ensure that we run from first 4GB so that all - * addresses used by U-Boot are 32bit addresses. - * - * This in-turn ensures that 32bit DMA capable - * devices work fine because DMA mapping APIs will - * provide 32bit DMA addresses only. - */ - if (gd->ram_top > SZ_4G) - return SZ_4G; -#endif - return gd->ram_top; -} diff --git a/arch/riscv/cpu/u54-mc/Kconfig b/arch/riscv/cpu/u54-mc/Kconfig new file mode 100644 index 0000000..60189a7 --- /dev/null +++ b/arch/riscv/cpu/u54-mc/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + +config U54_MC_RISCV + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply SIFIVE_CLINT if RISCV_MMODE + imply CMD_CPU diff --git a/arch/riscv/cpu/u54-mc/Makefile b/arch/riscv/cpu/u54-mc/Makefile new file mode 100644 index 0000000..258e462 --- /dev/null +++ b/arch/riscv/cpu/u54-mc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/u54-mc/cpu.c b/arch/riscv/cpu/u54-mc/cpu.c new file mode 100644 index 0000000..ad2950c --- /dev/null +++ b/arch/riscv/cpu/u54-mc/cpu.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + */ + +#include <common.h> +#include <dm.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} + +/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ +static const struct udevice_id riscv_virtio_soc_ids[] = { + { .compatible = "riscv-virtio-soc" }, + { } +}; + +U_BOOT_DRIVER(riscv_virtio_soc) = { + .name = "riscv_virtio_soc", + .id = UCLASS_SIMPLE_BUS, + .of_match = riscv_virtio_soc_ids, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/riscv/cpu/u54-mc/dram.c b/arch/riscv/cpu/u54-mc/dram.c new file mode 100644 index 0000000..b7b1207 --- /dev/null +++ b/arch/riscv/cpu/u54-mc/dram.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + */ + +#include <common.h> +#include <fdtdec.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_64BIT + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > SZ_4G) + return SZ_4G; +#endif + return gd->ram_top; +} diff --git a/arch/riscv/include/asm/arch-fu540-c000/clk.h b/arch/riscv/include/asm/arch-fu540-c000/clk.h new file mode 100644 index 0000000..1631f5f --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540-c000/clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel anup.patel@wdc.com + */ + +#ifndef __ASM_RISCV_ARCH_CLK_H +#define __ASM_RISCV_ARCH_CLK_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif diff --git a/arch/riscv/include/asm/arch-generic/clk.h b/arch/riscv/include/asm/arch-generic/clk.h deleted file mode 100644 index 1631f5f..0000000 --- a/arch/riscv/include/asm/arch-generic/clk.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel anup.patel@wdc.com - */ - -#ifndef __ASM_RISCV_ARCH_CLK_H -#define __ASM_RISCV_ARCH_CLK_H - -/* Note: This is a placeholder header for driver compilation. */ - -#endif diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig deleted file mode 100644 index 5d65080..0000000 --- a/board/sifive/fu540/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -if TARGET_SIFIVE_FU540 - -config SYS_BOARD - default "fu540" - -config SYS_VENDOR - default "sifive" - -config SYS_CPU - default "generic" - -config SYS_CONFIG_NAME - default "sifive-fu540" - -config SYS_TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select GENERIC_RISCV - imply CMD_DHCP - imply CMD_EXT2 - imply CMD_EXT4 - imply CMD_FAT - imply CMD_FS_GENERIC - imply CMD_NET - imply CMD_PING - imply CLK_SIFIVE - imply CLK_SIFIVE_FU540_PRCI - imply DOS_PARTITION - imply EFI_PARTITION - imply IP_DYN - imply ISO_PARTITION - imply MACB - imply MII - imply NET_RANDOM_ETHADDR - imply PHY_LIB - imply PHY_MSCC - imply SIFIVE_SERIAL - imply SPI - imply SPI_SIFIVE - imply MMC - imply MMC_SPI - imply MMC_BROKEN_CD - imply CMD_MMC - imply SMP - -endif diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS deleted file mode 100644 index 702d803..0000000 --- a/board/sifive/fu540/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -SiFive FU540 BOARD -M: Paul Walmsley paul.walmsley@sifive.com -M: Palmer Dabbelt palmer@sifive.com -M: Anup Patel anup.patel@wdc.com -M: Atish Patra atish.patra@wdc.com -S: Maintained -F: board/sifive/fu540/ -F: include/configs/sifive-fu540.h -F: configs/sifive_fu540_defconfig diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile deleted file mode 100644 index 6e1862c..0000000 --- a/board/sifive/fu540/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2019 Western Digital Corporation or its affiliates. - -obj-y += fu540.o diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c deleted file mode 100644 index 11daf1a..0000000 --- a/board/sifive/fu540/fu540.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel anup.patel@wdc.com - */ - -#include <common.h> -#include <dm.h> -#include <linux/delay.h> -#include <linux/io.h> - -#ifdef CONFIG_MISC_INIT_R - -#define FU540_OTP_BASE_ADDR 0x10070000 - -struct fu540_otp_regs { - u32 pa; /* Address input */ - u32 paio; /* Program address input */ - u32 pas; /* Program redundancy cell selection input */ - u32 pce; /* OTP Macro enable input */ - u32 pclk; /* Clock input */ - u32 pdin; /* Write data input */ - u32 pdout; /* Read data output */ - u32 pdstb; /* Deep standby mode enable input (active low) */ - u32 pprog; /* Program mode enable input */ - u32 ptc; /* Test column enable input */ - u32 ptm; /* Test mode enable input */ - u32 ptm_rep;/* Repair function test mode enable input */ - u32 ptr; /* Test row enable input */ - u32 ptrim; /* Repair function enable input */ - u32 pwe; /* Write enable input (defines program cycle) */ -} __packed; - -#define BYTES_PER_FUSE 4 -#define NUM_FUSES 0x1000 - -static int fu540_otp_read(int offset, void *buf, int size) -{ - struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR; - unsigned int i; - int fuseidx = offset / BYTES_PER_FUSE; - int fusecount = size / BYTES_PER_FUSE; - u32 fusebuf[fusecount]; - - /* check bounds */ - if (offset < 0 || size < 0) - return -EINVAL; - if (fuseidx >= NUM_FUSES) - return -EINVAL; - if ((fuseidx + fusecount) > NUM_FUSES) - return -EINVAL; - - /* init OTP */ - writel(0x01, ®s->pdstb); /* wake up from stand-by */ - writel(0x01, ®s->ptrim); /* enable repair function */ - writel(0x01, ®s->pce); /* enable input */ - - /* read all requested fuses */ - for (i = 0; i < fusecount; i++, fuseidx++) { - writel(fuseidx, ®s->pa); - - /* cycle clock to read */ - writel(0x01, ®s->pclk); - mdelay(1); - writel(0x00, ®s->pclk); - mdelay(1); - - /* read the value */ - fusebuf[i] = readl(®s->pdout); - } - - /* shut down */ - writel(0, ®s->pce); - writel(0, ®s->ptrim); - writel(0, ®s->pdstb); - - /* copy out */ - memcpy(buf, fusebuf, size); - - return 0; -} - -static u32 fu540_read_serialnum(void) -{ - int ret; - u32 serial[2] = {0}; - - for (int i = 0xfe * 4; i > 0; i -= 8) { - ret = fu540_otp_read(i, serial, sizeof(serial)); - if (ret) { - printf("%s: error reading from OTP\n", __func__); - break; - } - if (serial[0] == ~serial[1]) - return serial[0]; - } - - return 0; -} - -static void fu540_setup_macaddr(u32 serialnum) -{ - /* Default MAC address */ - unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 }; - - /* - * We derive our board MAC address by ORing last three bytes - * of board serial number to above default MAC address. - * - * This logic of deriving board MAC address is taken from - * SiFive FSBL and is kept unchanged. - */ - mac[5] |= (serialnum >> 0) & 0xff; - mac[4] |= (serialnum >> 8) & 0xff; - mac[3] |= (serialnum >> 16) & 0xff; - - /* Update environment variable */ - eth_env_set_enetaddr("ethaddr", mac); -} - -int misc_init_r(void) -{ - /* Set ethaddr environment variable if not set */ - if (!env_get("ethaddr")) - fu540_setup_macaddr(fu540_read_serialnum()); - - return 0; -} - -#endif - -int board_init(void) -{ - /* For now nothing to do here. */ - - return 0; -} diff --git a/board/sifive/hifive_unleashed/Kconfig b/board/sifive/hifive_unleashed/Kconfig new file mode 100644 index 0000000..484b262 --- /dev/null +++ b/board/sifive/hifive_unleashed/Kconfig @@ -0,0 +1,52 @@ +if TARGET_SIFIVE_HIFIVE_UNLEASHED + +config SYS_BOARD + default "hifive_unleashed" + +config SYS_VENDOR + default "sifive" + +config SYS_SOC + default "fu540-c000" + +config SYS_CPU + default "u54-mc" + +config SYS_CONFIG_NAME + default "hifive_unleashed" + +config SYS_TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select U54_MC_RISCV + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CLK_SIFIVE + imply CLK_SIFIVE_FU540_PRCI + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply NET_RANDOM_ETHADDR + imply PHY_LIB + imply PHY_MSCC + imply SIFIVE_SERIAL + imply SPI + imply SPI_SIFIVE + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC + imply SMP + +endif diff --git a/board/sifive/hifive_unleashed/MAINTAINERS b/board/sifive/hifive_unleashed/MAINTAINERS new file mode 100644 index 0000000..94539dd --- /dev/null +++ b/board/sifive/hifive_unleashed/MAINTAINERS @@ -0,0 +1,9 @@ +SiFive HIFIVE UNLEASHED BOARD +M: Paul Walmsley paul.walmsley@sifive.com +M: Palmer Dabbelt palmer@sifive.com +M: Anup Patel anup.patel@wdc.com +M: Atish Patra atish.patra@wdc.com +S: Maintained +F: board/sifive/hifive_unleashed/ +F: include/configs/hifive_unleashed.h +F: configs/hifive_unleashed_defconfig diff --git a/board/sifive/hifive_unleashed/Makefile b/board/sifive/hifive_unleashed/Makefile new file mode 100644 index 0000000..6e1862c --- /dev/null +++ b/board/sifive/hifive_unleashed/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. + +obj-y += fu540.o diff --git a/board/sifive/hifive_unleashed/fu540.c b/board/sifive/hifive_unleashed/fu540.c new file mode 100644 index 0000000..11daf1a --- /dev/null +++ b/board/sifive/hifive_unleashed/fu540.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel anup.patel@wdc.com + */ + +#include <common.h> +#include <dm.h> +#include <linux/delay.h> +#include <linux/io.h> + +#ifdef CONFIG_MISC_INIT_R + +#define FU540_OTP_BASE_ADDR 0x10070000 + +struct fu540_otp_regs { + u32 pa; /* Address input */ + u32 paio; /* Program address input */ + u32 pas; /* Program redundancy cell selection input */ + u32 pce; /* OTP Macro enable input */ + u32 pclk; /* Clock input */ + u32 pdin; /* Write data input */ + u32 pdout; /* Read data output */ + u32 pdstb; /* Deep standby mode enable input (active low) */ + u32 pprog; /* Program mode enable input */ + u32 ptc; /* Test column enable input */ + u32 ptm; /* Test mode enable input */ + u32 ptm_rep;/* Repair function test mode enable input */ + u32 ptr; /* Test row enable input */ + u32 ptrim; /* Repair function enable input */ + u32 pwe; /* Write enable input (defines program cycle) */ +} __packed; + +#define BYTES_PER_FUSE 4 +#define NUM_FUSES 0x1000 + +static int fu540_otp_read(int offset, void *buf, int size) +{ + struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR; + unsigned int i; + int fuseidx = offset / BYTES_PER_FUSE; + int fusecount = size / BYTES_PER_FUSE; + u32 fusebuf[fusecount]; + + /* check bounds */ + if (offset < 0 || size < 0) + return -EINVAL; + if (fuseidx >= NUM_FUSES) + return -EINVAL; + if ((fuseidx + fusecount) > NUM_FUSES) + return -EINVAL; + + /* init OTP */ + writel(0x01, ®s->pdstb); /* wake up from stand-by */ + writel(0x01, ®s->ptrim); /* enable repair function */ + writel(0x01, ®s->pce); /* enable input */ + + /* read all requested fuses */ + for (i = 0; i < fusecount; i++, fuseidx++) { + writel(fuseidx, ®s->pa); + + /* cycle clock to read */ + writel(0x01, ®s->pclk); + mdelay(1); + writel(0x00, ®s->pclk); + mdelay(1); + + /* read the value */ + fusebuf[i] = readl(®s->pdout); + } + + /* shut down */ + writel(0, ®s->pce); + writel(0, ®s->ptrim); + writel(0, ®s->pdstb); + + /* copy out */ + memcpy(buf, fusebuf, size); + + return 0; +} + +static u32 fu540_read_serialnum(void) +{ + int ret; + u32 serial[2] = {0}; + + for (int i = 0xfe * 4; i > 0; i -= 8) { + ret = fu540_otp_read(i, serial, sizeof(serial)); + if (ret) { + printf("%s: error reading from OTP\n", __func__); + break; + } + if (serial[0] == ~serial[1]) + return serial[0]; + } + + return 0; +} + +static void fu540_setup_macaddr(u32 serialnum) +{ + /* Default MAC address */ + unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 }; + + /* + * We derive our board MAC address by ORing last three bytes + * of board serial number to above default MAC address. + * + * This logic of deriving board MAC address is taken from + * SiFive FSBL and is kept unchanged. + */ + mac[5] |= (serialnum >> 0) & 0xff; + mac[4] |= (serialnum >> 8) & 0xff; + mac[3] |= (serialnum >> 16) & 0xff; + + /* Update environment variable */ + eth_env_set_enetaddr("ethaddr", mac); +} + +int misc_init_r(void) +{ + /* Set ethaddr environment variable if not set */ + if (!env_get("ethaddr")) + fu540_setup_macaddr(fu540_read_serialnum()); + + return 0; +} + +#endif + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} diff --git a/configs/hifive_unleashed_defconfig b/configs/hifive_unleashed_defconfig new file mode 100644 index 0000000..5a3b421 --- /dev/null +++ b/configs/hifive_unleashed_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TARGET_SIFIVE_HIFIVE_UNLEASHED=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_MISC_INIT_R=y +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig deleted file mode 100644 index f192037..0000000 --- a/configs/sifive_fu540_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_RISCV=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_TARGET_SIFIVE_FU540=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_SMODE=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_MISC_INIT_R=y -CONFIG_OF_PRIOR_STAGE=y diff --git a/include/configs/hifive_unleashed.h b/include/configs/hifive_unleashed.h new file mode 100644 index 0000000..858b7a7 --- /dev/null +++ b/include/configs/hifive_unleashed.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel anup.patel@wdc.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +/* Environment options */ +#define CONFIG_ENV_SIZE SZ_128K + +#define BOOT_TARGET_DEVICES(func) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + BOOTENV + +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" + +#endif /* __CONFIG_H */ diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h deleted file mode 100644 index 858b7a7..0000000 --- a/include/configs/sifive-fu540.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel anup.patel@wdc.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - -/* Environment options */ -#define CONFIG_ENV_SIZE SZ_128K - -#define BOOT_TARGET_DEVICES(func) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - BOOTENV - -#define CONFIG_PREBOOT \ - "setenv fdt_addr ${fdtcontroladdr};" \ - "fdt addr ${fdtcontroladdr};" - -#endif /* __CONFIG_H */
Hi,
On Mon, Jul 29, 2019 at 8:42 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Can you please explain why these changes are needed? It looks that the changes are only to rename the "generic" cpu name to "u54-mc", and rename the board name "fu540" to "hifive_unleashed"?
This breaks the QEMU virt boards.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c
It looks that you did not use "git mv" command.
create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
Regards, Bin
Hello Bin,
On Mon, Jul 29, 2019 at 7:15 PM Bin Meng bmeng.cn@gmail.com wrote:
Hi,
On Mon, Jul 29, 2019 at 8:42 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Can you please explain why these changes are needed? It looks that the changes are only to rename the "generic" cpu name to "u54-mc", and rename the board name "fu540" to "hifive_unleashed"?
This patch is intended to update the naming convention which U-boot mentions in doc/README.kconfig. As we know that FU540-C000 has a U54-MC CPU core, I thought of naming it as u54-mc and board name from fu540 to hifive_unleashed which is the actual case.
This breaks the QEMU virt boards.
Unfortunately yes. Hence I raised a request in the cover letter for suggestions accordingly.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c
It looks that you did not use "git mv" command.
I do remember using "git mv" here. Probably adding '-M' (detect renames) switch to git format-patch would have helped to include the renamed files instead of delete and create information. Next time I will ensure to include it. Thanks for pointing this.
BR, Sagar Kadam
create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
Regards, Bin
On Jul 30 2019, Sagar Kadam sagar.kadam@sifive.com wrote:
I do remember using "git mv" here.
git mv is identical to git rm + git add. A git repository has no concept of file renames.
Andreas.
Hi Andreas,
On Wed, Jul 31, 2019 at 2:02 PM Andreas Schwab schwab@suse.de wrote:
On Jul 30 2019, Sagar Kadam sagar.kadam@sifive.com wrote:
I do remember using "git mv" here.
git mv is identical to git rm + git add. A git repository has no concept of file renames.
Andreas.
Thanks, for clarifying.
Regards, Sagar Kadam
-- Andreas Schwab, SUSE Labs, schwab@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Other board support renaming is fine but there is lot of documentation in U-Boot, OpenSBI and other places which needs to be also updated.
Regards, Anup
Hello Anup,
On Tue, Jul 30, 2019 at 9:12 AM Anup Patel anup@brainfault.org wrote:
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Yes, your points are valid. I am Ok with it. My intent here was that as the support for riscv in U-boot is in its early stages and doing it now would be better as minimum changes will be required and going ahead as other CPU vendors introduce their CPU under arch/riscv/ we could isolate a generic CPU code as it grows.
Other board support renaming is fine but there is lot of documentation
If board support renaming is fine. Shall I submit another patch excluding the CPU changes?
Thanks & BR, Sagar Kadam
in U-Boot, OpenSBI and other places which needs to be also updated.
Regards, Anup
On Tue, Jul 30, 2019 at 11:01 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Anup,
On Tue, Jul 30, 2019 at 9:12 AM Anup Patel anup@brainfault.org wrote:
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Yes, your points are valid. I am Ok with it. My intent here was that as the support for riscv in U-boot is in its early stages and doing it now would be better as minimum changes will be required and going ahead as other CPU vendors introduce their CPU under arch/riscv/ we could isolate a generic CPU code as it grows.
Thanks.
Let's try to make arch/riscv/cpu/generic extensible from start itself so that it is relatively easy to fit newer RISC-V SOCs and boards.
Other board support renaming is fine but there is lot of documentation
If board support renaming is fine. Shall I submit another patch excluding the CPU changes?
Yes, please send another revision.
Also have consider updating U-Boot and OpenSBI documentation as separate patches.
Regards, Anup
Hi Anup,
On Wed, Jul 31, 2019 at 1:50 PM Anup Patel anup@brainfault.org wrote:
On Tue, Jul 30, 2019 at 11:01 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Anup,
On Tue, Jul 30, 2019 at 9:12 AM Anup Patel anup@brainfault.org wrote:
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Yes, your points are valid. I am Ok with it. My intent here was that as the support for riscv in U-boot is in its early stages and doing it now would be better as minimum changes will be required and going ahead as other CPU vendors introduce their CPU under arch/riscv/ we could isolate a generic CPU code as it grows.
Thanks.
Let's try to make arch/riscv/cpu/generic extensible from start itself so that it is relatively easy to fit newer RISC-V SOCs and boards.
Thanks. So can I assume that we agree on adding new CPU support under arch/riscv. Will provide a new patch for the same.
Other board support renaming is fine but there is lot of documentation
If board support renaming is fine. Shall I submit another patch excluding the CPU changes?
Yes, please send another revision.
Yes, I will do send another revision.
Also have consider updating U-Boot and OpenSBI documentation as separate patches.
Yes, I will also update the docs accordingly.
Thanks & BR, Sagar Kadam
Regards, Anup
On Thu, Aug 1, 2019 at 8:26 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Anup,
On Wed, Jul 31, 2019 at 1:50 PM Anup Patel anup@brainfault.org wrote:
On Tue, Jul 30, 2019 at 11:01 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Anup,
On Tue, Jul 30, 2019 at 9:12 AM Anup Patel anup@brainfault.org wrote:
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Yes, your points are valid. I am Ok with it. My intent here was that as the support for riscv in U-boot is in its early stages and doing it now would be better as minimum changes will be required and going ahead as other CPU vendors introduce their CPU under arch/riscv/ we could isolate a generic CPU code as it grows.
Thanks.
Let's try to make arch/riscv/cpu/generic extensible from start itself so that it is relatively easy to fit newer RISC-V SOCs and boards.
Thanks. So can I assume that we agree on adding new CPU support under arch/riscv. Will provide a new patch for the same.
I think you misunderstood my previous comment.
We should use the generic CPU support from start itself and promote use of generic CPU support as much as possible.
Adding specific CPU support under arch/riscv will require strong justification about why generic CPU support is not suitable for particular SOC.
Regards, Anup
Other board support renaming is fine but there is lot of documentation
If board support renaming is fine. Shall I submit another patch excluding the CPU changes?
Yes, please send another revision.
Yes, I will do send another revision.
Also have consider updating U-Boot and OpenSBI documentation as separate patches.
Yes, I will also update the docs accordingly.
Thanks & BR, Sagar Kadam
Regards, Anup
Hi Anup,
On Thu, Aug 1, 2019 at 9:26 PM Anup Patel anup@brainfault.org wrote:
On Thu, Aug 1, 2019 at 8:26 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Anup,
On Wed, Jul 31, 2019 at 1:50 PM Anup Patel anup@brainfault.org wrote:
On Tue, Jul 30, 2019 at 11:01 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Anup,
On Tue, Jul 30, 2019 at 9:12 AM Anup Patel anup@brainfault.org wrote:
On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
This patch aligns the current implementation of HiFive Unleashed board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h
I agree with Bin's concerns.
Please don't rename generic CPU support under arch/riscv
We should think long-term here. If every SOC vendor starts adding their CPU support directory under arch/riscv then U-Boot RISC port will be eventually difficult to manage and we will also have duplicate code across various CPU support.
IMHO, we should avoid adding new CPU support under arch/riscv as much as possible. We can call weak functions from generic CPU support and board support code can implement it. We should only add new CPU support under arch/riscv when we are not able to re-use generic CPU support.
Yes, your points are valid. I am Ok with it. My intent here was that as the support for riscv in U-boot is in its early stages and doing it now would be better as minimum changes will be required and going ahead as other CPU vendors introduce their CPU under arch/riscv/ we could isolate a generic CPU code as it grows.
Thanks.
Let's try to make arch/riscv/cpu/generic extensible from start itself so that it is relatively easy to fit newer RISC-V SOCs and boards.
Thanks. So can I assume that we agree on adding new CPU support under arch/riscv. Will provide a new patch for the same.
I think you misunderstood my previous comment.
We should use the generic CPU support from start itself and promote use of generic CPU support as much as possible.
Ohh, Ok, thanks for clarifying my assumption.
Adding specific CPU support under arch/riscv will require strong justification about why generic CPU support is not suitable for particular SOC.
Regards, Anup
Regards, Sagar
Other board support renaming is fine but there is lot of documentation
If board support renaming is fine. Shall I submit another patch excluding the CPU changes?
Yes, please send another revision.
Yes, I will do send another revision.
Also have consider updating U-Boot and OpenSBI documentation as separate patches.
Yes, I will also update the docs accordingly.
Thanks & BR, Sagar Kadam
Regards, Anup
participants (5)
-
Andreas Schwab -
Anup Patel -
Bin Meng -
Sagar Kadam -
Sagar Shrikant Kadam