[PATCH 0/4] clk/qcom: implement clk dump callback
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c.
If your SoC doesn't yet define the debug data for clocks, it can be added using the Linux driver as a reference.
The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets).
GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter.
== Example output ==
=> clk dump Rate Usecnt Name ------------------------------------------ 38400000 0 |-- xo-board 32764 0 |-- sleep-clk
qcom_clk qcom_clk: Gate Clocks: GCC_AGGRE_USB3_SEC_AXI_CLK : GCC_CFG_NOC_USB3_SEC_AXI_CLK : GCC_QUPV3_WRAP0_S0_CLK : GCC_QUPV3_WRAP0_S1_CLK : GCC_QUPV3_WRAP0_S2_CLK : GCC_QUPV3_WRAP0_S3_CLK : GCC_QUPV3_WRAP0_S4_CLK : GCC_QUPV3_WRAP0_S5_CLK : GCC_QUPV3_WRAP0_S6_CLK : GCC_QUPV3_WRAP0_S7_CLK : GCC_QUPV3_WRAP1_S0_CLK : GCC_QUPV3_WRAP1_S1_CLK : ON GCC_QUPV3_WRAP1_S3_CLK : GCC_QUPV3_WRAP1_S4_CLK : GCC_QUPV3_WRAP1_S5_CLK : GCC_QUPV3_WRAP1_S6_CLK : GCC_QUPV3_WRAP1_S7_CLK : GCC_QUPV3_WRAP_0_M_AHB_CLK : GCC_QUPV3_WRAP_0_S_AHB_CLK : GCC_QUPV3_WRAP_1_M_AHB_CLK : ON GCC_QUPV3_WRAP_1_S_AHB_CLK : ON GCC_SDCC2_AHB_CLK : ON GCC_SDCC2_APPS_CLK : ON GCC_SDCC4_AHB_CLK : GCC_SDCC4_APPS_CLK : GCC_UFS_CARD_AHB_CLK : GCC_UFS_CARD_AXI_CLK : GCC_UFS_CARD_CLKREF_CLK : ON GCC_UFS_CARD_ICE_CORE_CLK : GCC_UFS_CARD_PHY_AUX_CLK : GCC_UFS_CARD_RX_SYMBOL_0_CLK : GCC_UFS_CARD_RX_SYMBOL_1_CLK : GCC_UFS_CARD_TX_SYMBOL_0_CLK : GCC_UFS_CARD_UNIPRO_CORE_CLK : GCC_UFS_MEM_CLKREF_CLK : ON GCC_UFS_PHY_AHB_CLK : ON GCC_UFS_PHY_AXI_CLK : ON GCC_UFS_PHY_ICE_CORE_CLK : ON GCC_UFS_PHY_PHY_AUX_CLK : ON GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON GCC_UFS_PHY_UNIPRO_CORE_CLK : ON GCC_USB30_PRIM_MASTER_CLK : ON GCC_USB30_PRIM_MOCK_UTMI_CLK : ON GCC_USB30_PRIM_SLEEP_CLK : ON GCC_USB30_SEC_MASTER_CLK : GCC_USB30_SEC_MOCK_UTMI_CLK : GCC_USB30_SEC_SLEEP_CLK : GCC_USB3_PRIM_CLKREF_CLK : ON GCC_USB3_PRIM_PHY_AUX_CLK : ON GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON GCC_USB3_PRIM_PHY_PIPE_CLK : ON GCC_USB3_SEC_CLKREF_CLK : ON GCC_USB3_SEC_PHY_AUX_CLK : GCC_USB3_SEC_PHY_PIPE_CLK : GCC_USB3_SEC_PHY_COM_AUX_CLK : GCC_USB_PHY_CFG_AHB2PHY_CLK : ON
GPLL clocks: | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | +--------+--------+-----------+------------+----------------+ | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000
RCGs: | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | +----------------------------------+----+-----+---------------------------------------+--------------+ GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000]
--- Caleb Connolly (4): clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data
drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+) --- change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86
// Caleb (they/them)
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets).
GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ 2 files changed, 123 insertions(+)
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 79c7606a2253..5727d055e95a 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -12,8 +12,9 @@ * Based on Little Kernel driver, simplified */
#include <clk-uclass.h> +#include <linux/clk-provider.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <errno.h> @@ -214,11 +215,127 @@ static int msm_clk_enable(struct clk *clk)
return 0; }
+static void dump_gplls(struct udevice *dev, phys_addr_t base) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + u32 i; + bool locked; + u64 l, a, xo_rate = 19200000; + struct clk *clk = NULL; + struct udevice *xodev; + const phys_addr_t *gplls = data->dbg_pll_addrs; + + uclass_foreach_dev_probe(UCLASS_CLK, xodev) { + if (!strcmp(xodev->name, "xo-board") || !strcmp(xodev->name, "xo_board")) { + clk = dev_get_clk_ptr(xodev); + break; + } + } + + if (clk) { + xo_rate = clk_get_rate(clk); + + /* On SDM845 this needs to be divided by 2 for some reason */ + if (xo_rate && of_machine_is_compatible("qcom,sdm845")) + xo_rate /= 2; + } else { + printf("Can't find XO clock, XO_BOARD rate may be wrong\n"); + } + + printf("GPLL clocks:\n"); + printf("| GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA |\n"); + printf("+--------+--------+-----------+------------+----------------+\n"); + for (i = 0; i < data->num_plls; i++) { + locked = !!(readl(gplls[i]) & BIT(31)); + l = readl(gplls[i] + 4) & (BIT(16) - 1); + a = readq(gplls[i] + 40) & (BIT(16) - 1); + printf("| GPLL%-2d | %-6s | %9llu * (%#-9llx + %#-13llx * 2 ** -40 ) / 1000000\n", + i, locked ? "X" : "", xo_rate, l, a); + } +} + +static void dump_rcgs(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + int i; + u32 cmd; + u32 cfg; + u32 not_n_minus_m; + u32 src, m, n, div; + bool root_on, d_odd; + + printf("\nRCGs:\n"); + + /* + * Which GPLL SRC corresponds to depends on the parent map, see gcc-<soc>.c in Linux + * and find the parent map associated with the clock. Note that often there are multiple + * outputs from a single GPLL where one is actually half the rate of the other (_EVEN). + * intput_freq = associated GPLL output freq (potentially divided depending on SRC). + */ + printf("| NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] |\n"); + printf("+----------------------------------+----+-----+---------------------------------------+--------------+\n"); + for (i = 0; i < data->num_rcgs; i++) { + cmd = readl(data->dbg_rcg_addrs[i]); + cfg = readl(data->dbg_rcg_addrs[i] + 0x4); + m = readl(data->dbg_rcg_addrs[i] + 0x8); + n = 0; + not_n_minus_m = readl(data->dbg_rcg_addrs[i] + 0xc); + + root_on = !(cmd & BIT(31)); // ROOT_OFF + src = (cfg >> 8) & 7; + + if (not_n_minus_m) { + n = (~not_n_minus_m & 0xffff); + + /* A clumsy assumption that this is an 8-bit MND RCG */ + if ((n & 0xff00) == 0xff00) + n = n & 0xff; + + n += m; + } + + div = ((cfg & 0b11111) + 1) / 2; + d_odd = ((cfg & 0b11111) + 1) % 2 == 1; + printf("%-34s | %-2s | %3d | input_freq * (%4d/%5d) * (1/%1d%-2s) | [%#010x]\n", + data->dbg_rcg_names[i], root_on ? "X" : "", src, + m ?: 1, n ?: 1, div, d_odd ? ".5" : "", cmd); + } + + printf("\n"); +} + +static void msm_dump_clks(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + const struct gate_clk *sclk; + int val, i; + + if (!data->clks) { + printf("No clocks\n"); + return; + } + + printf("Gate Clocks:\n"); + for (i = 0; i < data->num_clks; i++) { + sclk = &data->clks[i]; + if (!sclk->name) + continue; + printf("%-32s: ", sclk->name); + val = readl(priv->base + sclk->reg) & sclk->en_val; + printf("%s\n", val ? "ON" : ""); + } + + dump_gplls(dev, priv->base); + dump_rcgs(dev); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, .enable = msm_clk_enable, + .dump = msm_dump_clks, };
U_BOOT_DRIVER(qcom_clk) = { .name = "qcom_clk", diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566f..040c0cf29943 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -75,8 +75,14 @@ struct msm_clk_data { unsigned long num_resets; const struct gate_clk *clks; unsigned long num_clks;
+ const phys_addr_t *dbg_pll_addrs; + unsigned long num_plls; + const phys_addr_t *dbg_rcg_addrs; + unsigned long num_rcgs; + const char * const *dbg_rcg_names; + int (*enable)(struct clk *clk); unsigned long (*set_rate)(struct clk *clk, unsigned long rate); };
Add debug data to dump PLL and RCG clocks.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-sdm845.c | 93 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+)
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index f41f8c9e8dee..adffb0cb2402 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -202,8 +202,96 @@ static const struct qcom_power_map sdm845_gdscs[] = { [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, };
+static const phys_addr_t sdm845_gpll_addrs[] = { + 0x00100000, // GCC_GPLL0_MODE + 0x00101000, // GCC_GPLL1_MODE + 0x00102000, // GCC_GPLL2_MODE + 0x00103000, // GCC_GPLL3_MODE + 0x00176000, // GCC_GPLL4_MODE + 0x00174000, // GCC_GPLL5_MODE + 0x00113000, // GCC_GPLL6_MODE +}; + +static const phys_addr_t sdm845_rcg_addrs[] = { + 0x0010f018, // GCC_USB30_PRIM_MASTER + 0x0010f030, // GCC_USB30_PRIM_MOCK_UTMI + 0x0010f05c, // GCC_USB3_PRIM_PHY_AUX + 0x00110018, // GCC_USB30_SEC_MASTER + 0x00110030, // GCC_USB30_SEC_MOCK_UTMI + 0x0011005c, // GCC_USB3_SEC_PHY_AUX + 0x0011400c, // GCC_SDCC2_APPS + 0x0011600c, // GCC_SDCC4_APPS + 0x00117018, // GCC_QUPV3_WRAP0_CORE_2X + 0x00117034, // GCC_QUPV3_WRAP0_S0 + 0x00117164, // GCC_QUPV3_WRAP0_S1 + 0x00117294, // GCC_QUPV3_WRAP0_S2 + 0x001173c4, // GCC_QUPV3_WRAP0_S3 + 0x001174f4, // GCC_QUPV3_WRAP0_S4 + 0x00117624, // GCC_QUPV3_WRAP0_S5 + 0x00117754, // GCC_QUPV3_WRAP0_S6 + 0x00117884, // GCC_QUPV3_WRAP0_S7 + 0x00118018, // GCC_QUPV3_WRAP1_S0 + 0x00118148, // GCC_QUPV3_WRAP1_S1 + 0x00118278, // GCC_QUPV3_WRAP1_S2 + 0x001183a8, // GCC_QUPV3_WRAP1_S3 + 0x001184d8, // GCC_QUPV3_WRAP1_S4 + 0x00118608, // GCC_QUPV3_WRAP1_S5 + 0x00118738, // GCC_QUPV3_WRAP1_S6 + 0x00118868, // GCC_QUPV3_WRAP1_S7 + 0x0016b028, // GCC_PCIE_0_AUX + 0x0018d028, // GCC_PCIE_1_AUX + 0x0016f014, // GCC_PCIE_PHY_REFGEN + 0x0017501c, // GCC_UFS_CARD_AXI + 0x0017505c, // GCC_UFS_CARD_ICE_CORE + 0x00175074, // GCC_UFS_CARD_UNIPRO_CORE + 0x00175090, // GCC_UFS_CARD_PHY_AUX + 0x0017701c, // GCC_UFS_PHY_AXI + 0x0017705c, // GCC_UFS_PHY_ICE_CORE + 0x00177074, // GCC_UFS_PHY_UNIPRO_CORE + 0x00177090, // GCC_UFS_PHY_PHY_AUX +}; + +static const char *const sdm845_rcg_names[] = { + "GCC_USB30_PRIM_MASTER", + "GCC_USB30_PRIM_MOCK_UTMI", + "GCC_USB3_PRIM_PHY_AUX", + "GCC_USB30_SEC_MASTER", + "GCC_USB30_SEC_MOCK_UTMI", + "GCC_USB3_SEC_PHY_AUX", + "GCC_SDCC2_APPS", + "GCC_SDCC4_APPS", + "GCC_QUPV3_WRAP0_CORE_2X", + "GCC_QUPV3_WRAP0_S0", + "GCC_QUPV3_WRAP0_S1", + "GCC_QUPV3_WRAP0_S2", + "GCC_QUPV3_WRAP0_S3", + "GCC_QUPV3_WRAP0_S4", + "GCC_QUPV3_WRAP0_S5", + "GCC_QUPV3_WRAP0_S6", + "GCC_QUPV3_WRAP0_S7", + "GCC_QUPV3_WRAP1_S0", + "GCC_QUPV3_WRAP1_S1", + "GCC_QUPV3_WRAP1_S2", + "GCC_QUPV3_WRAP1_S3", + "GCC_QUPV3_WRAP1_S4", + "GCC_QUPV3_WRAP1_S5", + "GCC_QUPV3_WRAP1_S6", + "GCC_QUPV3_WRAP1_S7", + "GCC_PCIE_0_AUX", + "GCC_PCIE_1_AUX", + "GCC_PCIE_PHY_REFGEN", + "GCC_UFS_CARD_AXI", + "GCC_UFS_CARD_ICE_CORE", + "GCC_UFS_CARD_UNIPRO_CORE", + "GCC_UFS_CARD_PHY_AUX", + "GCC_UFS_PHY_AXI", + "GCC_UFS_PHY_ICE_CORE", + "GCC_UFS_PHY_UNIPRO_CORE", + "GCC_UFS_PHY_PHY_AUX", +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, @@ -212,8 +300,13 @@ static struct msm_clk_data sdm845_clk_data = { .num_power_domains = ARRAY_SIZE(sdm845_gdscs),
.enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, + .dbg_pll_addrs = sdm845_gpll_addrs, + .num_plls = ARRAY_SIZE(sdm845_gpll_addrs), + .dbg_rcg_addrs = sdm845_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sdm845_rcg_addrs), + .dbg_rcg_names = sdm845_rcg_names, };
static const struct udevice_id gcc_sdm845_of_match[] = { {
Add "clk dump" support for SM6115.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-sm6115.c | 63 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)
diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c index 8314a0deb348..9057dfe0bb18 100644 --- a/drivers/clk/qcom/clock-sm6115.c +++ b/drivers/clk/qcom/clock-sm6115.c @@ -169,8 +169,65 @@ static const struct qcom_reset_map sm6115_gcc_resets[] = { static const struct qcom_power_map sm6115_gdscs[] = { [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, };
+static const phys_addr_t sm6115_gpll_addrs[] = { + 0x01400000, // GCC_GPLL0_MODE + 0x01401000, // GCC_GPLL1_MODE + 0x01402000, // GCC_GPLL2_MODE + 0x01403000, // GCC_GPLL3_MODE + 0x01404000, // GCC_GPLL4_MODE + 0x01405000, // GCC_GPLL5_MODE + 0x01406000, // GCC_GPLL6_MODE + 0x01407000, // GCC_GPLL7_MODE + 0x01408000, // GCC_GPLL8_MODE + 0x01409000, // GCC_GPLL9_MODE + 0x0140a000, // GCC_GPLL10_MODE + 0x0140b000, // GCC_GPLL11_MODE +}; + +static const phys_addr_t sm6115_rcg_addrs[] = { + 0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x01438028, // GCC_SDCC1_APPS_CMD_RCGR + 0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0141f018, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR + 0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x01428014, // GCC_SLEEP_CMD_RCGR + 0x0142802c, // GCC_XO_CMD_RCGR + 0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR +}; + +static const char *const sm6115_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_SDCC1_APPS_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_SLEEP_CMD_RCGR", + "GCC_XO_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", +}; + static struct msm_clk_data sm6115_gcc_data = { .resets = sm6115_gcc_resets, .num_resets = ARRAY_SIZE(sm6115_gcc_resets), .clks = sm6115_clks, @@ -179,8 +236,14 @@ static struct msm_clk_data sm6115_gcc_data = { .num_power_domains = ARRAY_SIZE(sm6115_gdscs),
.enable = sm6115_enable, .set_rate = sm6115_set_rate, + + .dbg_pll_addrs = sm6115_gpll_addrs, + .num_plls = ARRAY_SIZE(sm6115_gpll_addrs), + .dbg_rcg_addrs = sm6115_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm6115_rcg_addrs), + .dbg_rcg_names = sm6115_rcg_names, };
static const struct udevice_id gcc_sm6115_of_match[] = { {
Drop in the RCG and GPLL data for debugging these clocks.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-sm8250.c | 115 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+)
diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c index af10fc116219..e322a923a5c0 100644 --- a/drivers/clk/qcom/clock-sm8250.c +++ b/drivers/clk/qcom/clock-sm8250.c @@ -252,8 +252,117 @@ static const struct qcom_power_map sm8250_gdscs[] = { [UFS_PHY_GDSC] = { 0x77004 }, [USB30_PRIM_GDSC] = { 0xf004 }, [USB30_SEC_GDSC] = { 0x10004 }, };
+static const phys_addr_t sm8250_gpll_addrs[] = { + 0x00100000, // GCC_GPLL0_MODE + 0x00101000, // GCC_GPLL1_MODE + 0x00102000, // GCC_GPLL2_MODE + 0x00103000, // GCC_GPLL3_MODE + 0x00176000, // GCC_GPLL4_MODE + 0x00174000, // GCC_GPLL5_MODE + 0x00113000, // GCC_GPLL6_MODE + 0x0011a000, // GCC_GPLL7_MODE + 0x0011b000, // GCC_GPLL8_MODE + 0x0011c000, // GCC_GPLL9_MODE + 0x0011d000, // GCC_GPLL10_MODE + 0x0014a000, // GCC_GPLL11_MODE +}; + +static const phys_addr_t sm8250_rcg_addrs[] = { + 0x0010f020, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0010f038, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0010f064, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x00110020, // GCC_USB30_SEC_MASTER_CMD_RCGR + 0x00110038, // GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR + 0x00110064, // GCC_USB3_SEC_PHY_AUX_CMD_RCGR + 0x0011400c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0011600c, // GCC_SDCC4_APPS_CMD_RCGR + 0x0012300c, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR + 0x00117010, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x00117140, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x00117270, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x001173a0, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x001174d0, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x00117600, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x00117730, // GCC_QUPV3_WRAP0_S6_CMD_RCGR + 0x00117860, // GCC_QUPV3_WRAP0_S7_CMD_RCGR + 0x00123144, // GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR + 0x00118010, // GCC_QUPV3_WRAP1_S0_CMD_RCGR + 0x00118140, // GCC_QUPV3_WRAP1_S1_CMD_RCGR + 0x00118270, // GCC_QUPV3_WRAP1_S2_CMD_RCGR + 0x001183a0, // GCC_QUPV3_WRAP1_S3_CMD_RCGR + 0x001184d0, // GCC_QUPV3_WRAP1_S4_CMD_RCGR + 0x00118600, // GCC_QUPV3_WRAP1_S5_CMD_RCGR + 0x0016b038, // GCC_PCIE_0_AUX_CMD_RCGR + 0x0018d038, // GCC_PCIE_1_AUX_CMD_RCGR + 0x0016f014, // GCC_PCIE_PHY_REFGEN_CMD_RCGR + 0x00175024, // GCC_UFS_CARD_AXI_CMD_RCGR + 0x0017506c, // GCC_UFS_CARD_ICE_CORE_CMD_RCGR + 0x00175084, // GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR + 0x001750a0, // GCC_UFS_CARD_PHY_AUX_CMD_RCGR + 0x00177024, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x0017706c, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x00177084, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x001770a0, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR + 0x0012327c, // GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR + 0x0011e010, // GCC_QUPV3_WRAP2_S0_CMD_RCGR + 0x0011e140, // GCC_QUPV3_WRAP2_S1_CMD_RCGR + 0x0011e270, // GCC_QUPV3_WRAP2_S2_CMD_RCGR + 0x0011e3a0, // GCC_QUPV3_WRAP2_S3_CMD_RCGR + 0x0011e4d0, // GCC_QUPV3_WRAP2_S4_CMD_RCGR + 0x0011e600, // GCC_QUPV3_WRAP2_S5_CMD_RCGR + 0x0010d00c, // GCC_RBCPR_MMCX_CMD_RCGR + 0x00106038, // GCC_PCIE_2_AUX_CMD_RCGR +}; + +static const char *const sm8250_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_USB30_SEC_MASTER_CMD_RCGR", + "GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_SEC_PHY_AUX_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_SDCC4_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_QUPV3_WRAP0_S6_CMD_RCGR", + "GCC_QUPV3_WRAP0_S7_CMD_RCGR", + "GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP1_S0_CMD_RCGR", + "GCC_QUPV3_WRAP1_S1_CMD_RCGR", + "GCC_QUPV3_WRAP1_S2_CMD_RCGR", + "GCC_QUPV3_WRAP1_S3_CMD_RCGR", + "GCC_QUPV3_WRAP1_S4_CMD_RCGR", + "GCC_QUPV3_WRAP1_S5_CMD_RCGR", + "GCC_PCIE_0_AUX_CMD_RCGR", + "GCC_PCIE_1_AUX_CMD_RCGR", + "GCC_PCIE_PHY_REFGEN_CMD_RCGR", + "GCC_UFS_CARD_AXI_CMD_RCGR", + "GCC_UFS_CARD_ICE_CORE_CMD_RCGR", + "GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_CARD_PHY_AUX_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", + "GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP2_S0_CMD_RCGR", + "GCC_QUPV3_WRAP2_S1_CMD_RCGR", + "GCC_QUPV3_WRAP2_S2_CMD_RCGR", + "GCC_QUPV3_WRAP2_S3_CMD_RCGR", + "GCC_QUPV3_WRAP2_S4_CMD_RCGR", + "GCC_QUPV3_WRAP2_S5_CMD_RCGR", + "GCC_RBCPR_MMCX_CMD_RCGR", + "GCC_PCIE_2_AUX_CMD_RCGR", +}; + static struct msm_clk_data qcs404_gcc_data = { .resets = sm8250_gcc_resets, .num_resets = ARRAY_SIZE(sm8250_gcc_resets), .clks = sm8250_clks, @@ -262,8 +371,14 @@ static struct msm_clk_data qcs404_gcc_data = { .num_power_domains = ARRAY_SIZE(sm8250_gdscs),
.enable = sm8250_enable, .set_rate = sm8250_set_rate, + + .dbg_pll_addrs = sm8250_gpll_addrs, + .num_plls = ARRAY_SIZE(sm8250_gpll_addrs), + .dbg_rcg_addrs = sm8250_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm8250_rcg_addrs), + .dbg_rcg_names = sm8250_rcg_names, };
static const struct udevice_id gcc_sm8250_of_match[] = { {
Hi Lukasz,
Could you take a quick look at this?
Thanks and kind regards,
On 19/08/2024 21:34, Caleb Connolly wrote:
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c.
If your SoC doesn't yet define the debug data for clocks, it can be added using the Linux driver as a reference.
The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
- Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
- Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets).
GPLL: Global Phase Locked Loop
- Crystal as input
- integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
- Put between RCGs and the peripherals they power
- Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter.
== Example output ==
=> clk dump Rate Usecnt Name
38400000 0 |-- xo-board 32764 0 |-- sleep-clk
qcom_clk qcom_clk: Gate Clocks: GCC_AGGRE_USB3_SEC_AXI_CLK : GCC_CFG_NOC_USB3_SEC_AXI_CLK : GCC_QUPV3_WRAP0_S0_CLK : GCC_QUPV3_WRAP0_S1_CLK : GCC_QUPV3_WRAP0_S2_CLK : GCC_QUPV3_WRAP0_S3_CLK : GCC_QUPV3_WRAP0_S4_CLK : GCC_QUPV3_WRAP0_S5_CLK : GCC_QUPV3_WRAP0_S6_CLK : GCC_QUPV3_WRAP0_S7_CLK : GCC_QUPV3_WRAP1_S0_CLK : GCC_QUPV3_WRAP1_S1_CLK : ON GCC_QUPV3_WRAP1_S3_CLK : GCC_QUPV3_WRAP1_S4_CLK : GCC_QUPV3_WRAP1_S5_CLK : GCC_QUPV3_WRAP1_S6_CLK : GCC_QUPV3_WRAP1_S7_CLK : GCC_QUPV3_WRAP_0_M_AHB_CLK : GCC_QUPV3_WRAP_0_S_AHB_CLK : GCC_QUPV3_WRAP_1_M_AHB_CLK : ON GCC_QUPV3_WRAP_1_S_AHB_CLK : ON GCC_SDCC2_AHB_CLK : ON GCC_SDCC2_APPS_CLK : ON GCC_SDCC4_AHB_CLK : GCC_SDCC4_APPS_CLK : GCC_UFS_CARD_AHB_CLK : GCC_UFS_CARD_AXI_CLK : GCC_UFS_CARD_CLKREF_CLK : ON GCC_UFS_CARD_ICE_CORE_CLK : GCC_UFS_CARD_PHY_AUX_CLK : GCC_UFS_CARD_RX_SYMBOL_0_CLK : GCC_UFS_CARD_RX_SYMBOL_1_CLK : GCC_UFS_CARD_TX_SYMBOL_0_CLK : GCC_UFS_CARD_UNIPRO_CORE_CLK : GCC_UFS_MEM_CLKREF_CLK : ON GCC_UFS_PHY_AHB_CLK : ON GCC_UFS_PHY_AXI_CLK : ON GCC_UFS_PHY_ICE_CORE_CLK : ON GCC_UFS_PHY_PHY_AUX_CLK : ON GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON GCC_UFS_PHY_UNIPRO_CORE_CLK : ON GCC_USB30_PRIM_MASTER_CLK : ON GCC_USB30_PRIM_MOCK_UTMI_CLK : ON GCC_USB30_PRIM_SLEEP_CLK : ON GCC_USB30_SEC_MASTER_CLK : GCC_USB30_SEC_MOCK_UTMI_CLK : GCC_USB30_SEC_SLEEP_CLK : GCC_USB3_PRIM_CLKREF_CLK : ON GCC_USB3_PRIM_PHY_AUX_CLK : ON GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON GCC_USB3_PRIM_PHY_PIPE_CLK : ON GCC_USB3_SEC_CLKREF_CLK : ON GCC_USB3_SEC_PHY_AUX_CLK : GCC_USB3_SEC_PHY_PIPE_CLK : GCC_USB3_SEC_PHY_COM_AUX_CLK : GCC_USB_PHY_CFG_AHB2PHY_CLK : ON
GPLL clocks: | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | +--------+--------+-----------+------------+----------------+ | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000
RCGs: | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | +----------------------------------+----+-----+---------------------------------------+--------------+ GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000]
Caleb Connolly (4): clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data
drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+)
change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86
// Caleb (they/them)
On Mon, 19 Aug 2024 21:34:16 +0200, Caleb Connolly wrote:
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly.
== Usage ==
[...]
Applied, thanks!
[1/4] clk/qcom: implement clk dump https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/c0999fef... [2/4] clk/qcom: sdm845: add dump data https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/2880a076... [3/4] clk/qcom: sm6115: add debug data https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/84b2b8dc... [4/4] clk/qcom: sm8250: add debug data https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/866cda77...
Best regards,
participants (1)
-
Caleb Connolly