[U-Boot] [PATCH 0/7] mmc: sunxi: Enable DM_MMC
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
Add for all Allwinner SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better to go for the release. Request to test respective board takers.
Any inputs, Jagan.
Jagan Teki (7): mmc: sunxi: Configure reset support for DM_MMC mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
arch/arm/Kconfig | 1 + arch/arm/dts/sunxi-u-boot.dtsi | 4 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 3 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - drivers/mmc/sunxi_mmc.c | 73 ++++++++++++++++++- 6 files changed, 79 insertions(+), 4 deletions(-)
Start with Allwinner A31, mmc controllers do support reset control bit. This code add support to enable the reset control start from SUN6I even though it share same compatible between SUN4I and SUN6I.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 302332bf97..0b17e2c391 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -21,8 +21,11 @@
#ifdef CONFIG_DM_MMC struct sunxi_mmc_variant { + bool has_reset; u16 gate_offset; u16 mclk_offset; + u16 reset_offset; + u8 reset_start_bit; }; #endif
@@ -609,7 +612,7 @@ static int sunxi_mmc_probe(struct udevice *dev) struct sunxi_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; struct ofnode_phandle_args args; - u32 *gate_reg, *ccu_reg; + u32 *gate_reg, *reset_reg, *ccu_reg; int bus_width, ret;
cfg->name = dev->name; @@ -644,6 +647,12 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
+ if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) && priv->variant->has_reset) { + reset_reg = (void *)ccu_reg + priv->variant->reset_offset; + setbits_le32(reset_reg, BIT(priv->mmc_no + + priv->variant->reset_start_bit)); + } + ret = mmc_set_mod_clk(priv, 24000000); if (ret) return ret; @@ -680,6 +689,14 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, };
+static const struct sunxi_mmc_variant sun7i_a20_variant = { + .has_reset = true, + .gate_offset = 0x60, + .mclk_offset = 0x88, + .reset_offset = 0x2c0, + .reset_start_bit = 8, +}; + static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -691,7 +708,7 @@ static const struct udevice_id sunxi_mmc_ids[] = { }, { .compatible = "allwinner,sun7i-a20-mmc", - .data = (ulong)&sun4i_a10_variant, + .data = (ulong)&sun7i_a20_variant, }, { /* sentinel */ } };
Add emmc compatible for A83T SoC.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0b17e2c391..5557111c1f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -710,6 +710,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun7i-a20-mmc", .data = (ulong)&sun7i_a20_variant, }, + { + .compatible = "allwinner,sun8i-a83t-emmc", + .data = (ulong)&sun7i_a20_variant, + }, { /* sentinel */ } };
Added H5, A64 compatible for mmc and emmc.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 5557111c1f..b50d70645a 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -714,6 +714,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun7i_a20_variant, }, + { + .compatible = "allwinner,sun50i-a64-mmc", + .data = (ulong)&sun7i_a20_variant, + }, + { + .compatible = "allwinner,sun50i-a64-emmc", + .data = (ulong)&sun7i_a20_variant, + }, { /* sentinel */ } };
Unlike other Allwinner SoC's, H6 comes with different clock and reset control offset values. So support them via driver data.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- .../arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 3 +++ drivers/mmc/sunxi_mmc.c | 16 ++++++++++++++++ 2 files changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index e36937059b..baf9b2e6e2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -301,6 +301,9 @@ struct sunxi_ccm_reg { #define DRAM_CLK_SRC_PLL5 (0 << 24) #define DRAM_CLK_M(m) (((m)-1) << 0)
+/* MMC ahb clock bit field */ +#define AHB_GATE_OFFSET_MMC(n) ((n)) + /* MMC clock bit field */ #define CCM_MMC_CTRL_M(x) ((x) - 1) #define CCM_MMC_CTRL_N(x) ((x) << 8) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index b50d70645a..05f15838a8 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -697,6 +697,14 @@ static const struct sunxi_mmc_variant sun7i_a20_variant = { .reset_start_bit = 8, };
+static const struct sunxi_mmc_variant sun50i_h6_variant = { + .has_reset = true, + .gate_offset = 0x84c, + .mclk_offset = 0x830, + .reset_offset = 0x84c, + .reset_start_bit = 16, +}; + static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -722,6 +730,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun50i-a64-emmc", .data = (ulong)&sun7i_a20_variant, }, + { + .compatible = "allwinner,sun50i-h6-mmc", + .data = (ulong)&sun50i_h6_variant, + }, + { + .compatible = "allwinner,sun50i-h6-emmc", + .data = (ulong)&sun50i_h6_variant, + }, { /* sentinel */ } };
Unlike other Allwinner SoC's, A80 comes with different ahb gate clock offset values and also has mmc common controller. So support them via driver data.
Cc: Rask Ingemann Lambertsen rask@formelder.dk Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 05f15838a8..33f1ec5e5a 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -22,6 +22,7 @@ #ifdef CONFIG_DM_MMC struct sunxi_mmc_variant { bool has_reset; + bool has_mmc_common; u16 gate_offset; u16 mclk_offset; u16 reset_offset; @@ -653,6 +654,19 @@ static int sunxi_mmc_probe(struct udevice *dev) priv->variant->reset_start_bit)); }
+ if (priv->variant->has_mmc_common) { + u32 *mmc_config_clk, *mmc_common_base; + + ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, + 0, &args); + if (ret) + return ret; + mmc_config_clk = (u32 *)ofnode_get_addr(args.node); + + mmc_common_base = (void *)mmc_config_clk + (priv->mmc_no * 4); + setbits_le32(mmc_common_base, BIT(18) | BIT(16)); + } + ret = mmc_set_mod_clk(priv, 24000000); if (ret) return ret; @@ -697,6 +711,12 @@ static const struct sunxi_mmc_variant sun7i_a20_variant = { .reset_start_bit = 8, };
+static const struct sunxi_mmc_variant sun9i_a80_variant = { + .has_mmc_common = true, + .gate_offset = 0x580, + .mclk_offset = 0x410, +}; + static const struct sunxi_mmc_variant sun50i_h6_variant = { .has_reset = true, .gate_offset = 0x84c, @@ -722,6 +742,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun7i_a20_variant, }, + { + .compatible = "allwinner,sun9i-a80-mmc", + .data = (ulong)&sun9i_a80_variant, + }, { .compatible = "allwinner,sun50i-a64-mmc", .data = (ulong)&sun7i_a20_variant,
Enable DM_MMC for all Allwinner SoCs, this will eventually enable BLK.
Also removed DM_MMC enablement in few parts of sunxi configurations.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 520ea8bed9..d5a35b2b5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -850,6 +850,7 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_KEYBOARD + select DM_MMC if MMC select DM_SERIAL select DM_USB if DISTRO_DEFAULTS select OF_BOARD_SETUP diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3c54f5106d..74e234cded 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -154,7 +154,6 @@ config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A select ARM_CORTEX_CPU_IS_UP - select DM_MMC if MMC select DM_SCSI if SCSI select PHY_SUN4I_USB select DRAM_SUN4I diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 00a49d1077..56e8d5398e 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ { + aliases { + mmc1 = &mmc2; + }; + binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;
On Fri, Jan 11, 2019 at 10:04 AM Jagan Teki jagan@amarulasolutions.com wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
Add for all Allwinner SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better to go for the release. Request to test respective board takers.
Hi Jagan,
Do you have a branch with all the patches (including clk and reset) that I can use to test the changes on Pine64 and Pinebook?
Regards, Vasily
Any inputs, Jagan.
Jagan Teki (7): mmc: sunxi: Configure reset support for DM_MMC mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
arch/arm/Kconfig | 1 + arch/arm/dts/sunxi-u-boot.dtsi | 4 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 3 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - drivers/mmc/sunxi_mmc.c | 73 ++++++++++++++++++- 6 files changed, 79 insertions(+), 4 deletions(-)
-- 2.18.0.321.gffc6fa0e3
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On Sat, Jan 12, 2019 at 5:32 AM Vasily Khoruzhick anarsoul@gmail.com wrote:
On Fri, Jan 11, 2019 at 10:04 AM Jagan Teki jagan@amarulasolutions.com wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
Add for all Allwinner SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better to go for the release. Request to test respective board takers.
Hi Jagan,
Do you have a branch with all the patches (including clk and reset) that I can use to test the changes on Pine64 and Pinebook?
Please check it in u-boot-sunxi/next
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200) Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Setting up a 640x480 dvi console (overscan 0x0) In: serial Out: vga Err: vga Allwinner mUSB OTG (Peripheral) SCSI: SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net: sunxi_set_gate: (CLK#66) unhandled eth0: ethernet@1c50000
And also CLK#66 message
Add for all Allwinner SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better to go for the release. Request to test respective board takers.
Any inputs, Jagan.
Jagan Teki (7): mmc: sunxi: Configure reset support for DM_MMC mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
arch/arm/Kconfig | 1 + arch/arm/dts/sunxi-u-boot.dtsi | 4 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 3 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - drivers/mmc/sunxi_mmc.c | 73 ++++++++++++++++++- 6 files changed, 79 insertions(+), 4 deletions(-)
-- 2.18.0.321.gffc6fa0e3
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes plaes@plaes.org wrote:
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200) Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Can you try this diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..7fab88c47f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
- if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) && priv->variant->has_reset) { + if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) && priv->variant->has_reset) { reset_reg = (void *)ccu_reg + priv->variant->reset_offset; setbits_le32(reset_reg, BIT(priv->mmc_no + priv->variant->reset_start_bit));
Setting up a 640x480 dvi console (overscan 0x0) In: serial Out: vga Err: vga Allwinner mUSB OTG (Peripheral) SCSI: SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net: sunxi_set_gate: (CLK#66) unhandled eth0: ethernet@1c50000
And also CLK#66 message
This is expected, looking EMAC clock from dw driver, will handle in next series. to be noted we enable print.
On Mon, Jan 14, 2019 at 03:40:37PM +0530, Jagan Teki wrote:
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes plaes@plaes.org wrote:
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200) Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Can you try this diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..7fab88c47f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) && priv->variant->has_reset) {
if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) && priv->variant->has_reset) { reset_reg = (void *)ccu_reg + priv->variant->reset_offset; setbits_le32(reset_reg, BIT(priv->mmc_no + priv->variant->reset_start_bit));
Still fails:
MMC: no card present scanning bus for devices... Found 0 device(s).
Device 0: unknown device
Device 0: unknown device
Setting up a 640x480 dvi console (overscan 0x0) In: serial Out: vga Err: vga Allwinner mUSB OTG (Peripheral) SCSI: SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net: sunxi_set_gate: (CLK#66) unhandled eth0: ethernet@1c50000
And also CLK#66 message
This is expected, looking EMAC clock from dw driver, will handle in next series. to be noted we enable print.
-- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
On Mon 14 Jan, 2019, 3:53 PM Priit Laes <plaes@plaes.org wrote:
On Mon, Jan 14, 2019 at 03:40:37PM +0530, Jagan Teki wrote:
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes plaes@plaes.org wrote:
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200)
Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Can you try this diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..7fab88c47f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) &&priv->variant->has_reset) {
if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) &&priv->variant->has_reset) {
reset_reg = (void *)ccu_reg +priv->variant->reset_offset;
setbits_le32(reset_reg, BIT(priv->mmc_no + priv->variant->reset_start_bit));Still fails:
MMC: no card present scanning bus for devices... Found 0 device(s).
Device 0: unknown device
Device 0: unknown device
Can you print the reg values mclk and gate_reg. I have Lime2 which is fine but doesn't have eMMC.
On Mon, Jan 14, 2019 at 04:00:44PM +0530, Jagan Teki wrote:
On Mon 14 Jan, 2019, 3:53 PM Priit Laes <plaes@plaes.org wrote:
On Mon, Jan 14, 2019 at 03:40:37PM +0530, Jagan Teki wrote:
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes plaes@plaes.org wrote:
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200)
Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Can you try this diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..7fab88c47f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) &&priv->variant->has_reset) {
if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) &&priv->variant->has_reset) {
reset_reg = (void *)ccu_reg +priv->variant->reset_offset;
setbits_le32(reset_reg, BIT(priv->mmc_no + priv->variant->reset_start_bit));Still fails:
MMC: no card present scanning bus for devices... Found 0 device(s).
Device 0: unknown device
Device 0: unknown device
Can you print the reg values mclk and gate_reg. I have Lime2 which is fine but doesn't have eMMC.
mclk0: 0x0 gate0: 0x200c141 mclk2: 0x0 gate2: 0x200c541
-- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
On Mon, Jan 14, 2019 at 10:39:37AM +0000, Priit Laes wrote:
On Mon, Jan 14, 2019 at 04:00:44PM +0530, Jagan Teki wrote:
On Mon 14 Jan, 2019, 3:53 PM Priit Laes <plaes@plaes.org wrote:
On Mon, Jan 14, 2019 at 03:40:37PM +0530, Jagan Teki wrote:
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes plaes@plaes.org wrote:
On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
I thought of waiting this till CLK framework gets Mainline, but migration deadline for DM_MMC and BLK seems expiring in next release. So instead of doing so huddle and make some last minute changes, I have managed to add CLK, Reset code for mmc driver via driver data.
U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200)
Allwinner Technology
CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2-eMMC I2C: ready DRAM: 1 GiB MMC: mmc@1c0f000: 0, mmc@1c11000: 1 Loading Environment from FAT... Card did not respond to voltage select!
eMMC seems to be broken: => mmc list mmc@1c0f000: 0 mmc@1c11000: 1 => mmc dev 1 => mmc dev 0 MMC: no card present => mmc part MMC: no card present => mmc info MMC: no card present
Can you try this diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..7fab88c47f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev) gate_reg = (void *)ccu_reg + priv->variant->gate_offset; setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) &&priv->variant->has_reset) {
if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) &&priv->variant->has_reset) {
reset_reg = (void *)ccu_reg +priv->variant->reset_offset;
setbits_le32(reset_reg, BIT(priv->mmc_no + priv->variant->reset_start_bit));Still fails:
MMC: no card present scanning bus for devices... Found 0 device(s).
Device 0: unknown device
Device 0: unknown device
Can you print the reg values mclk and gate_reg. I have Lime2 which is fine but doesn't have eMMC.
mclk0: 0x0 gate0: 0x200c141 mclk2: 0x0 gate2: 0x200c541
I managed to mess it up:
XXX: mclk0: 0x80500000 XXX: gate0: 0x200c141
XXX: mclk2: 0x80500000 XXX: gate2: 0x200c541
This is what you want:
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 33f1ec5e5a..ac396d8d89 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -684,6 +684,9 @@ static int sunxi_mmc_probe(struct udevice *dev)
upriv->mmc = &plat->mmc;
+ printf("XXX: mclk%d: 0x%x\n", priv->mmc_no, *priv->mclkreg); + printf("XXX: gate%d: 0x%x\n", priv->mmc_no, *gate_reg); + /* Reset controller */ writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); udelay(1000);
-- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
-- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
participants (3)
-
Jagan Teki -
Priit Laes -
Vasily Khoruzhick