[U-Boot] [PATCH 0/5] Add initial support for Pine64 Rock64 board.
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Kever Yang (3): rockchip: rk3328: add spl board file support rockchip: rk3328: add config option for SPL rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (2): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-rock64-u-boot.dtsi | 30 +++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ configs/rock64-rk3328_defconfig | 91 +++++++++ include/configs/rk3328_common.h | 5 +- 8 files changed, 487 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
From: Kever Yang kever.yang@rock-chips.com
rk3328 spl is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 368302e1da..ce823df6c6 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -16,6 +16,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif
On Wed, 8 May 2019 at 00:35, Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
From: Kever Yang kever.yang@rock-chips.com
rk3328 spl is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
Reviewed-by: Simon Glass sjg@chromium.org
From: Kever Yang kever.yang@rock-chips.com
Enable SPL_FRAMEWORK and SPL related base addr and size.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- include/configs/rk3328_common.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..03d2a70154 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,7 +16,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 - +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
Hi Matwey,
On Wed, 8 May 2019 at 00:35, Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
From: Kever Yang kever.yang@rock-chips.com
Enable SPL_FRAMEWORK and SPL related base addr and size.
Where are you enabling SPL_FRAMEWORK?
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
include/configs/rk3328_common.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
Regards, Simon
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 282d728b82..2748cc59e7 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -83,6 +83,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
On Wed, 8 May 2019 at 00:35, Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
rk3328-rock64.dts has been taken from Linux kernel with minor modifications.
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-rock64-u-boot.dtsi | 30 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8e082f2840..cacc580502 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ + rk3328-rock64.dtb \ rk3399-ficus.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..a0e04be758 --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +};
Hi Matwey,
On 05/08/2019 02:34 PM, Matwey V. Kornilov wrote:
rk3328-rock64.dts has been taken from Linux kernel with minor modifications.
Could you detail about which commit of kernel do you take this dts from?
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-rock64-u-boot.dtsi | 30 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8e082f2840..cacc580502 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \
- rk3328-rock64.dtb \ rk3399-ficus.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..a0e04be758 --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,30 @@ +/*
- (C) Copyright 2018 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+/ {
- aliases {
mmc0 = &emmc;mmc1 = &sdmmc;- };
Maybe you would need a spl-boot-order here to make sure SPL can find u-boot from both emmc and sdmmc.
+};
+&cru {
- u-boot,dm-pre-reloc;
+};
+&uart2 {
- u-boot,dm-pre-reloc;
+};
And maybe you need add 'clock-frequency=24000000' for uart2.
Thanks, - Kever
+&emmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
+};
+&sdmmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
+}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2017 PINE64
- */
+/dts-v1/; +#include "rk3328.dtsi"
+/ {
- model = "Pine64 Rock64";
- compatible = "pine64,rock64", "rockchip,rk3328";
- chosen {
stdout-path = "serial2:1500000n8";- };
- gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac_clkin";#clock-cells = <0>;- };
- vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&sdmmc0m1_gpio>;regulator-name = "vcc_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_io>;- };
- vcc_host_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb30_host_drv>;regulator-name = "vcc_host_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;- };
- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb20_host_drv>;regulator-name = "vcc_host1_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;- };
- vcc_sys: vcc-sys {
compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
+};
+&cpu0 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu1 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu2 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu3 {
- cpu-supply = <&vdd_arm>;
+};
+&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
+};
+&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_io>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- snps,force_thresh_dma_mode;
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x24>;
- rx_delay = <0x18>;
- status = "okay";
+};
+&i2c1 {
- status = "okay";
- rk805: rk805@18 {
compatible = "rockchip,rk805";reg = <0x18>;interrupt-parent = <&gpio2>;interrupts = <6 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <1>;clock-output-names = "xin32k", "rk805-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc5-supply = <&vcc_io>;vcc6-supply = <&vcc_sys>;regulators {vdd_logic: DCDC_REG1 {regulator-name = "vdd_logic";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vdd_arm: DCDC_REG2 {regulator-name = "vdd_arm";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <950000>;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_io: DCDC_REG4 {regulator-name = "vcc_io";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_18: LDO_REG1 {regulator-name = "vdd_18";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc18_emmc: LDO_REG2 {regulator-name = "vcc_18emmc";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_10: LDO_REG3 {regulator-name = "vdd_10";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};};- };
+};
+&io_domains {
- status = "okay";
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- pmuio-supply = <&vcc_io>;
+};
+&pinctrl {
- pmic {
pmic_int_l: pmic-int-l {rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- usb2 {
usb20_host_drv: usb20-host-drv {rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb3 {
usb30_host_drv: usb30-host-drv {rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
+};
+&spi0 {
- status = "okay";
- spiflash@0 {
compatible = "jedec,spi-nor";reg = <0>;/* maximum speed for Rockchip SPI */spi-max-frequency = <50000000>;- };
+};
+&uart2 {
- status = "okay";
+};
+&usb20_otg {
- dr_mode = "host";
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
Hi Kever,
чт, 16 мая 2019 г. в 09:56, Kever Yang kever.yang@rock-chips.com:
Hi Matwey,
On 05/08/2019 02:34 PM, Matwey V. Kornilov wrote:
rk3328-rock64.dts has been taken from Linux kernel with minor modifications.
Could you detail about which commit of kernel do you take this dts from?
Sure.
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-rock64-u-boot.dtsi | 30 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8e082f2840..cacc580502 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \
rk3328-rock64.dtb \ rk3399-ficus.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..a0e04be758 --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,30 @@ +/*
- (C) Copyright 2018 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+/ {
aliases {mmc0 = &emmc;mmc1 = &sdmmc;};Maybe you would need a spl-boot-order here to make sure SPL can find u-boot from both emmc and sdmmc.
Done. Yet I don't have EMMC on my board to test.
+};
+&cru {
u-boot,dm-pre-reloc;+};
+&uart2 {
u-boot,dm-pre-reloc;+};
And maybe you need add 'clock-frequency=24000000' for uart2.
uart2 node in rk3328.dtsi already has the clock-frequency.
Thanks,
- Kever
+&emmc {
u-boot,dm-pre-reloc;fifo-mode;+};
+&sdmmc {
u-boot,dm-pre-reloc;fifo-mode;+}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2017 PINE64
- */
+/dts-v1/; +#include "rk3328.dtsi"
+/ {
model = "Pine64 Rock64";compatible = "pine64,rock64", "rockchip,rk3328";chosen {stdout-path = "serial2:1500000n8";};gmac_clkin: external-gmac-clock {compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac_clkin";#clock-cells = <0>;};vcc_sd: sdmmc-regulator {compatible = "regulator-fixed";gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&sdmmc0m1_gpio>;regulator-name = "vcc_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_io>;};vcc_host_5v: vcc-host-5v-regulator {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb30_host_drv>;regulator-name = "vcc_host_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;};vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb20_host_drv>;regulator-name = "vcc_host1_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;};vcc_sys: vcc-sys {compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;};+};
+&cpu0 {
cpu-supply = <&vdd_arm>;+};
+&cpu1 {
cpu-supply = <&vdd_arm>;+};
+&cpu2 {
cpu-supply = <&vdd_arm>;+};
+&cpu3 {
cpu-supply = <&vdd_arm>;+};
+&emmc {
bus-width = <8>;cap-mmc-highspeed;mmc-hs200-1_8v;non-removable;pinctrl-names = "default";pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;vmmc-supply = <&vcc_io>;vqmmc-supply = <&vcc18_emmc>;status = "okay";+};
+&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;clock_in_out = "input";phy-supply = <&vcc_io>;phy-mode = "rgmii";pinctrl-names = "default";pinctrl-0 = <&rgmiim1_pins>;snps,force_thresh_dma_mode;snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;snps,reset-active-low;snps,reset-delays-us = <0 10000 50000>;tx_delay = <0x24>;rx_delay = <0x18>;status = "okay";+};
+&i2c1 {
status = "okay";rk805: rk805@18 {compatible = "rockchip,rk805";reg = <0x18>;interrupt-parent = <&gpio2>;interrupts = <6 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <1>;clock-output-names = "xin32k", "rk805-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc5-supply = <&vcc_io>;vcc6-supply = <&vcc_sys>;regulators {vdd_logic: DCDC_REG1 {regulator-name = "vdd_logic";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vdd_arm: DCDC_REG2 {regulator-name = "vdd_arm";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <950000>;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_io: DCDC_REG4 {regulator-name = "vcc_io";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_18: LDO_REG1 {regulator-name = "vdd_18";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc18_emmc: LDO_REG2 {regulator-name = "vcc_18emmc";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_10: LDO_REG3 {regulator-name = "vdd_10";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};};};+};
+&io_domains {
status = "okay";vccio1-supply = <&vcc_io>;vccio2-supply = <&vcc18_emmc>;vccio3-supply = <&vcc_io>;vccio4-supply = <&vcc_18>;vccio5-supply = <&vcc_io>;vccio6-supply = <&vcc_io>;pmuio-supply = <&vcc_io>;+};
+&pinctrl {
pmic {pmic_int_l: pmic-int-l {rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;};};usb2 {usb20_host_drv: usb20-host-drv {rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;};};usb3 {usb30_host_drv: usb30-host-drv {rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;};};+};
+&sdmmc {
bus-width = <4>;cap-mmc-highspeed;cap-sd-highspeed;disable-wp;max-frequency = <150000000>;pinctrl-names = "default";pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;vmmc-supply = <&vcc_sd>;status = "okay";+};
+&spi0 {
status = "okay";spiflash@0 {compatible = "jedec,spi-nor";reg = <0>;/* maximum speed for Rockchip SPI */spi-max-frequency = <50000000>;};+};
+&uart2 {
status = "okay";+};
+&usb20_otg {
dr_mode = "host";status = "okay";+};
+&usb_host0_ehci {
status = "okay";+};
+&usb_host0_ohci {
status = "okay";+};
-- With best regards, Matwey V. Kornilov
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..b278315035 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
On 2019-05-08, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
Thanks for submitting these patches upstream!
Unfortunately, I wasn't able to get this to boot off of microSD.
What process do you use to test this? Does it depend on patches not present in 2019.07-rc1 or not yet merged?
The process I tried after building upstream arm-trusted-firmware 2.1:
mkimage -T rksd -n rk3328 -d spl/u-boot-spl.bin u-boot-spl.rksd
dd if=u-boot-spl.rksd of=/dev/sdb seek=64 dd if=u-boot.itb of=/dev/sdb seek=16384
There was no output on the serial console, either at 1500000 or 115200.
live well, vagrant
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..b278315035 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
On 2019-05-13, Vagrant Cascadian wrote:
On 2019-05-08, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
Thanks for submitting these patches upstream!
Unfortunately, I wasn't able to get this to boot off of microSD.
What process do you use to test this? Does it depend on patches not present in 2019.07-rc1 or not yet merged?
Downloading the patch series from patchwork didn't include the cover letter which explains what is needed... I'll test with that now; sorry for the noise.
Maybe those instructions should be included in doc/README.rockchip ?
live well, vagrant
On 2019-05-13, Vagrant Cascadian wrote:
On 2019-05-13, Vagrant Cascadian wrote:
On 2019-05-08, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
...
Downloading the patch series from patchwork didn't include the cover letter which explains what is needed... I'll test with that now; sorry for the noise.
Maybe those instructions should be included in doc/README.rockchip ?
Works for me! Tested booting from microSD and PXE.
Please CC me on updated patch series, if any.
Tested-by: Vagrant Cascadian vagrant@debian.org
live well, vagrant
вт, 14 мая 2019 г. в 02:13, Vagrant Cascadian vagrant@debian.org:
On 2019-05-13, Vagrant Cascadian wrote:
On 2019-05-13, Vagrant Cascadian wrote:
On 2019-05-08, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
...
Downloading the patch series from patchwork didn't include the cover letter which explains what is needed... I'll test with that now; sorry for the noise.
Maybe those instructions should be included in doc/README.rockchip ?
Works for me! Tested booting from microSD and PXE.
Nice to hear. Thank you for the work.
Please CC me on updated patch series, if any.
Tested-by: Vagrant Cascadian vagrant@debian.org
live well, vagrant
Hi Matwey,
Please add commit message for the patch.
On 05/08/2019 02:34 PM, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..b278315035 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
Does this SPL_REVERVE_IRAM=0 fine with support ATF? SPL TEXT_BASE is 0, and ATF starts at 0x100000, I use to reserve big enough space for ATF and U-Boot before SPL enable the relocate feature, or else it's very easy to get panic in SPL.
Thanks, - Kever
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Hi Kever,
чт, 16 мая 2019 г. в 10:01, Kever Yang kever.yang@rock-chips.com:
Hi Matwey,
Please add commit message for the patch.On 05/08/2019 02:34 PM, Matwey V. Kornilov wrote:
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..b278315035 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
Does this SPL_REVERVE_IRAM=0 fine with support ATF? SPL TEXT_BASE is 0, and ATF starts at 0x100000, I use to reserve big enough space for ATF and U-Boot before SPL enable the relocate feature, or else it's very easy to get panic in SPL.
I set it to 0x40000 now as in evb-rk3328_defconfig. However It works for me also with 0x0.
Thanks,
- Kever
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
-- With best regards, Matwey V. Kornilov
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Changes since v1: - reword messages for commit 2,4,5 - set SPL_REVERVE_IRAM to 0x40000 - add spl-boot-order to rk3328-rock64-u-boot.dtsi
Kever Yang (3): rockchip: rk3328: add SPL board file support rockchip: rk3328: add SPL support rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (2): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ configs/rock64-rk3328_defconfig | 91 +++++++++ include/configs/rk3328_common.h | 4 + 8 files changed, 492 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
From: Kever Yang kever.yang@rock-chips.com
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif
On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
From: Kever Yang kever.yang@rock-chips.com
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+void board_debug_uart_init(void) +{ +}
+void board_init_f(ulong dummy) +{
- struct udevice *dev;
- int ret;
- ret = spl_early_init();
- if (ret) {
debug("spl_early_init() failed: %d\n", ret);hang();- }
- preloader_console_init();
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
debug("DRAM init failed: %d\n", ret);return;- }
+}
+u32 spl_boot_mode(const u32 boot_device) +{
- return MMCSD_MODE_RAW;
+}
+u32 spl_boot_device(void) +{
- return BOOT_DEVICE_MMC1;
+}
+#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- return 0;
+} +#endif
From: Kever Yang kever.yang@rock-chips.com
Add SPL support for rk3328, default with of-platdata enabled.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- include/configs/rk3328_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
From: Kever Yang kever.yang@rock-chips.com
Add SPL support for rk3328, default with of-platdata enabled.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
include/configs/rk3328_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..3e38344b50 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..3e38344b50 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64
- select SUPPORT_SPL
- select SPL
- imply SPL_SERIAL_SUPPORT
- imply SPL_SEPARATE_BSS
- select ENABLE_ARM_SOC_BOOT0_HOOK
- select DEBUG_UART_BOARD_INIT
- select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")
with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0ec7bc987d..42ee1fb654 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +};
On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0ec7bc987d..42ee1fb654 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- rk3328-evb.dtb
- rk3328-evb.dtb \
- rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/*
- (C) Copyright 2018 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+/ {
- aliases {
mmc0 = &emmc;mmc1 = &sdmmc;- };
- chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;- };
+};
+&cru {
- u-boot,dm-pre-reloc;
+};
+&uart2 {
- u-boot,dm-pre-reloc;
+};
+&emmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
+};
+&sdmmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
+}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2017 PINE64
- */
+/dts-v1/; +#include "rk3328.dtsi"
+/ {
- model = "Pine64 Rock64";
- compatible = "pine64,rock64", "rockchip,rk3328";
- chosen {
stdout-path = "serial2:1500000n8";- };
- gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac_clkin";#clock-cells = <0>;- };
- vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&sdmmc0m1_gpio>;regulator-name = "vcc_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_io>;- };
- vcc_host_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb30_host_drv>;regulator-name = "vcc_host_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;- };
- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb20_host_drv>;regulator-name = "vcc_host1_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;- };
- vcc_sys: vcc-sys {
compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
+};
+&cpu0 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu1 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu2 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu3 {
- cpu-supply = <&vdd_arm>;
+};
+&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
+};
+&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_io>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- snps,force_thresh_dma_mode;
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x24>;
- rx_delay = <0x18>;
- status = "okay";
+};
+&i2c1 {
- status = "okay";
- rk805: rk805@18 {
compatible = "rockchip,rk805";reg = <0x18>;interrupt-parent = <&gpio2>;interrupts = <6 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <1>;clock-output-names = "xin32k", "rk805-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc5-supply = <&vcc_io>;vcc6-supply = <&vcc_sys>;regulators {vdd_logic: DCDC_REG1 {regulator-name = "vdd_logic";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vdd_arm: DCDC_REG2 {regulator-name = "vdd_arm";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <12500>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <950000>;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_io: DCDC_REG4 {regulator-name = "vcc_io";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_18: LDO_REG1 {regulator-name = "vdd_18";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc18_emmc: LDO_REG2 {regulator-name = "vcc_18emmc";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_10: LDO_REG3 {regulator-name = "vdd_10";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};};- };
+};
+&io_domains {
- status = "okay";
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- pmuio-supply = <&vcc_io>;
+};
+&pinctrl {
- pmic {
pmic_int_l: pmic-int-l {rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- usb2 {
usb20_host_drv: usb20-host-drv {rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb3 {
usb30_host_drv: usb30-host-drv {rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
+};
+&spi0 {
- status = "okay";
- spiflash@0 {
compatible = "jedec,spi-nor";reg = <0>;/* maximum speed for Rockchip SPI */spi-max-frequency = <50000000>;- };
+};
+&uart2 {
- status = "okay";
+};
+&usb20_otg {
- dr_mode = "host";
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
On 2019-05-19, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Could you add a patch documenting this in doc/README.rockchip or a board-specific README? That would be more useful than having to search the git commit messages or mailing list archives.
Tested this patch series against v2019.07-rc2, and I was able to pxe boot fine, but unfortunately was unable to boot from microSD.
I presume this is caused by some other change since v2019.07-rc1, since the earlier rock64 patches worked fine with microSD on v2019.07-rc1.
Scanning mmc 1:6... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1953 bytes read in 4 ms (476.6 KiB/s) U-Boot menu 1: Debian GNU/Linux kernel 5.1.0-trunk-arm64 2: Debian GNU/Linux kernel 5.1.0-trunk-arm64 (rescue target) 3: Debian GNU/Linux kernel 5.0.0-trunk-arm64 4: Debian GNU/Linux kernel 5.0.0-trunk-arm64 (rescue target) 5: Debian GNU/Linux kernel 4.19.0-5-arm64 6: Debian GNU/Linux kernel 4.19.0-5-arm64 (rescue target) Enter choice: 1 1: Debian GNU/Linux kernel 5.1.0-trunk-arm64 Retrieving file: /boot/initrd.img-5.1.0-trunk-arm64 ** fs_devread read error - block Skipping l0 for failure retrieving initrd 2: Debian GNU/Linux kernel 5.1.0-trunk-arm64 (rescue target) Retrieving file: /boot/initrd.img-5.1.0-trunk-arm64 *** ERROR: Can't read GPT Entries *** GPT: Failed to allocate memory for PTE part_get_info_efi: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header ***
I enabled CONFIG_CMD_CACHE=y and tried "dcache off" but that didn't appear to help anything. Any other suggestions?
live well, vagrant
пн, 20 мая 2019 г. в 20:11, Vagrant Cascadian vagrant@debian.org:
On 2019-05-19, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Could you add a patch documenting this in doc/README.rockchip or a board-specific README? That would be more useful than having to search the git commit messages or mailing list archives.
Tested this patch series against v2019.07-rc2, and I was able to pxe boot fine, but unfortunately was unable to boot from microSD.
I presume this is caused by some other change since v2019.07-rc1, since the earlier rock64 patches worked fine with microSD on v2019.07-rc1.\
Thanks for the report. This series is based on 98b3156b0df4 At least bootefi works fine for me. Do v1 patches works for you on v2019.07-rc2?
Scanning mmc 1:6... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1953 bytes read in 4 ms (476.6 KiB/s) U-Boot menu 1: Debian GNU/Linux kernel 5.1.0-trunk-arm64 2: Debian GNU/Linux kernel 5.1.0-trunk-arm64 (rescue target) 3: Debian GNU/Linux kernel 5.0.0-trunk-arm64 4: Debian GNU/Linux kernel 5.0.0-trunk-arm64 (rescue target) 5: Debian GNU/Linux kernel 4.19.0-5-arm64 6: Debian GNU/Linux kernel 4.19.0-5-arm64 (rescue target) Enter choice: 1 1: Debian GNU/Linux kernel 5.1.0-trunk-arm64 Retrieving file: /boot/initrd.img-5.1.0-trunk-arm64 ** fs_devread read error - block Skipping l0 for failure retrieving initrd 2: Debian GNU/Linux kernel 5.1.0-trunk-arm64 (rescue target) Retrieving file: /boot/initrd.img-5.1.0-trunk-arm64 *** ERROR: Can't read GPT Entries *** GPT: Failed to allocate memory for PTE part_get_info_efi: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header ***
I enabled CONFIG_CMD_CACHE=y and tried "dcache off" but that didn't appear to help anything. Any other suggestions?
live well, vagrant
On 2019-05-20, Matwey V. Kornilov wrote:
пн, 20 мая 2019 г. в 20:11, Vagrant Cascadian vagrant@debian.org:
On 2019-05-19, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Could you add a patch documenting this in doc/README.rockchip or a board-specific README? That would be more useful than having to search the git commit messages or mailing list archives.
Tested this patch series against v2019.07-rc2, and I was able to pxe boot fine, but unfortunately was unable to boot from microSD.
I presume this is caused by some other change since v2019.07-rc1, since the earlier rock64 patches worked fine with microSD on v2019.07-rc1.\
Thanks for the report. This series is based on 98b3156b0df4 At least bootefi works fine for me.
No obvious relevent changes between 98b3156b0df4 and v2019.07-rc2.
I haven't tested with bootefi ... will give that a try too.
Do v1 patches works for you on v2019.07-rc2?
With some minor rebasing to apply to -rc2, the v1 patches fail in the same way as the v2 patches on top of v2019.07-rc2.
live well, vagrant
пн, 20 мая 2019 г. в 21:15, Vagrant Cascadian vagrant@debian.org:
On 2019-05-20, Matwey V. Kornilov wrote:
пн, 20 мая 2019 г. в 20:11, Vagrant Cascadian vagrant@debian.org:
On 2019-05-19, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Could you add a patch documenting this in doc/README.rockchip or a board-specific README? That would be more useful than having to search the git commit messages or mailing list archives.
Tested this patch series against v2019.07-rc2, and I was able to pxe boot fine, but unfortunately was unable to boot from microSD.
I presume this is caused by some other change since v2019.07-rc1, since the earlier rock64 patches worked fine with microSD on v2019.07-rc1.\
Thanks for the report. This series is based on 98b3156b0df4 At least bootefi works fine for me.
No obvious relevent changes between 98b3156b0df4 and v2019.07-rc2.
I haven't tested with bootefi ... will give that a try too.
Do v1 patches works for you on v2019.07-rc2?
With some minor rebasing to apply to -rc2, the v1 patches fail in the same way as the v2 patches on top of v2019.07-rc2.
Maybe try to rebase?
Could you share your OS image? I can not reproduce the issue now :(
live well, vagrant
-- With best regards, Matwey V. Kornilov
On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Hi Matwey,
Recommend to use patman(tools/patman) to send to patch set,
so that it's easy to add change log for each version on each patch,
and don't forget to add review tag if you didn't change anything fot
the patch, eg. review tag from Simon on patch 3.
Thanks, - Kever On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Changes since v1:
- reword messages for commit 2,4,5
- set SPL_REVERVE_IRAM to 0x40000
- add spl-boot-order to rk3328-rock64-u-boot.dtsi
Kever Yang (3): rockchip: rk3328: add SPL board file support rockchip: rk3328: add SPL support rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (2): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ configs/rock64-rk3328_defconfig | 91 +++++++++ include/configs/rk3328_common.h | 4 + 8 files changed, 492 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
Hi Matwey,
This patch set broken the spl build for evb-rk3328, see:
https://travis-ci.org/keveryang/u-boot/jobs/539154859
Please try buildman/buildman rockchip or pass the Travis build for U-Boot for your patches.
Thanks, - Kever On 05/19/2019 08:10 PM, Matwey V. Kornilov wrote:
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Changes since v1:
- reword messages for commit 2,4,5
- set SPL_REVERVE_IRAM to 0x40000
- add spl-boot-order to rk3328-rock64-u-boot.dtsi
Kever Yang (3): rockchip: rk3328: add SPL board file support rockchip: rk3328: add SPL support rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (2): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ configs/rock64-rk3328_defconfig | 91 +++++++++ include/configs/rk3328_common.h | 4 + 8 files changed, 492 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Changes since v2: - add deploy documentation to doc/README.rockchip - fix broken evb-rk3328 build
Changes since v1: - reword messages for commit 2,4,5 - set SPL_REVERVE_IRAM to 0x40000 - add spl-boot-order to rk3328-rock64-u-boot.dtsi
Kever Yang (3): rockchip: rk3328: add SPL board file support rockchip: rk3328: add SPL support rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (3): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig doc: rockchip: Add note for Pine64 Rock64 board
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ configs/evb-rk3328_defconfig | 7 + configs/rock64-rk3328_defconfig | 91 +++++++++ doc/README.rockchip | 30 ++- include/configs/rk3328_common.h | 4 + 10 files changed, 527 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
From: Kever Yang kever.yang@rock-chips.com
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif
From: Kever Yang kever.yang@rock-chips.com
Add SPL support for rk3328, default with of-platdata enabled.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- include/configs/rk3328_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Kconfig | 7 +++++++ configs/evb-rk3328_defconfig | 7 +++++++ 2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..3e38344b50 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362..92d6817ad5 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -19,11 +22,15 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")
with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 31ef2b66a3..f6b5bacfcc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +};
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Hi Matwey,
You will need to add MAINTAINER info for configs/rock64-rk3328_defconfig,
or else Travis build fail in case "Check for configs without MAINTAINERS entry":
https://travis-ci.org/keveryang/u-boot/jobs/541040787
You can add MAINTAIN info in board/rockchip/evb_rk3328/MAINTAINERS before it need a dedicate folder for board setting.
Thanks, - Kever On 06/01/2019 10:47 PM, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Hi Kever,
Should I add myself as contact person?
вт, 4 июн. 2019 г. в 10:42, Kever Yang kever.yang@rock-chips.com:
Hi Matwey,
You will need to add MAINTAINER info for configs/rock64-rk3328_defconfig,or else Travis build fail in case " Check for configs without MAINTAINERS entry":
https://travis-ci.org/keveryang/u-boot/jobs/541040787
You can add MAINTAIN info in board/rockchip/evb_rk3328/MAINTAINERSbefore it need a dedicate folder for board setting.
Thanks,
- Kever
On 06/01/2019 10:47 PM, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com
configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Add build notes for Pine64 Rock64 board.
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- doc/README.rockchip | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/doc/README.rockchip b/doc/README.rockchip index ca4d6473b0..eacedbddf4 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration
-One RK3328 board is supported: +Two RK3328 board are supported:
- - EVB RK3328 + - EVB RK3328 - use evb-rk3328_defconfig + - Pine64 Rock64 board - use rock64-rk3328_defconfig
Size RK3399 boards are supported (aarch64):
@@ -307,6 +308,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
+Booting from an SD card on Pine64 Rock64 (RK3328) +================================================= + +For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin: + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create TPL/SPL image + + => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => cat spl/u-boot-spl.bin >> idbloader.img + + - Write TPL/SPL image at 64 sector + + => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 + + - Write u-boot image tree blob at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384 + Booting from an SD card on RK3399 =================================
On 06/01/2019 10:47 PM, Matwey V. Kornilov wrote:
Add build notes for Pine64 Rock64 board.
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
doc/README.rockchip | 30 ++++++++++++++++++++++++++++--
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/doc/README.rockchip b/doc/README.rockchip index ca4d6473b0..eacedbddf4 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration
-One RK3328 board is supported: +Two RK3328 board are supported:
- EVB RK3328
- EVB RK3328 - use evb-rk3328_defconfig
- Pine64 Rock64 board - use rock64-rk3328_defconfig
Size RK3399 boards are supported (aarch64):
@@ -307,6 +308,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
+Booting from an SD card on Pine64 Rock64 (RK3328) +=================================================
+For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin:
- Get the rkbin
- => git clone https://github.com/rockchip-linux/rkbin.git
- Create TPL/SPL image
- => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img
- => cat spl/u-boot-spl.bin >> idbloader.img
- Write TPL/SPL image at 64 sector
- => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64
- Write u-boot image tree blob at 16384 sector
- => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384
Booting from an SD card on RK3399
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.14.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
The series has been tested with ATF v1.6.
Some patches in the series are taken from https://github.com/rockchip-linux/u-boot Credits are given in each patch separately.
Changes since v3: - add the entry to board/rockchip/evb_rk3328/MAINTAINERS
Changes since v2: - add deploy documentation to doc/README.rockchip - fix broken evb-rk3328 build
Changes since v1: - reword messages for commit 2,4,5 - set SPL_REVERVE_IRAM to 0x40000 - add spl-boot-order to rk3328-rock64-u-boot.dtsi
Kever Yang (3): rockchip: rk3328: add SPL board file support rockchip: rk3328: add SPL support rockchip: Kconfig: enable SPL support for rk3328
Matwey V. Kornilov (3): rockchip: dts: rk3328: add rk3328-rock64.dts rockchip: rk3328: add rock64-rk3328_defconfig doc: rockchip: Add note for Pine64 Rock64 board
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 ++++++ board/rockchip/evb_rk3328/MAINTAINERS | 6 + configs/evb-rk3328_defconfig | 7 + configs/rock64-rk3328_defconfig | 91 +++++++++ doc/README.rockchip | 30 ++- include/configs/rk3328_common.h | 4 + 11 files changed, 533 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c create mode 100644 configs/rock64-rk3328_defconfig
From: Kever Yang kever.yang@rock-chips.com
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa722... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3328-board-spl.c | 59 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif
From: Kever Yang kever.yang@rock-chips.com
Add SPL support for rk3328, default with of-platdata enabled.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae02... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- include/configs/rk3328_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
From: Kever Yang kever.yang@rock-chips.com
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang kever.yang@rock-chips.com [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587... with minor modifications] Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- arch/arm/mach-rockchip/Kconfig | 7 +++++++ configs/evb-rk3328_defconfig | 7 +++++++ 2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..3e38344b50 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362..92d6817ad5 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -19,11 +22,15 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")
with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 34 ++++ arch/arm/dts/rk3328-rock64.dts | 294 +++++++++++++++++++++++++++++++++ 3 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e0c54bfa76..19499ddfc6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +};
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com --- board/rockchip/evb_rk3328/MAINTAINERS | 6 +++ configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a6..c661d2e06a 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig + +ROCK64-RK3328 +M: Matwey V. Kornilov matwey.kornilov@gmail.com +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
On 06/09/2019 05:27 AM, Matwey V. Kornilov wrote:
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board. The proprietary TPL is stil required for deploy:
./tools/mkimage -n rk3328 -T rksd \ -d ./rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
board/rockchip/evb_rk3328/MAINTAINERS | 6 +++ configs/rock64-rk3328_defconfig | 91 +++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a6..c661d2e06a 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig
+ROCK64-RK3328 +M: Matwey V. Kornilov matwey.kornilov@gmail.com +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y
Add build notes for Pine64 Rock64 board.
Signed-off-by: Matwey V. Kornilov matwey.kornilov@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- doc/README.rockchip | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/doc/README.rockchip b/doc/README.rockchip index 264f7e4994..11ab74a103 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration
-One RK3328 board is supported: +Two RK3328 board are supported:
- - EVB RK3328 + - EVB RK3328 - use evb-rk3328_defconfig + - Pine64 Rock64 board - use rock64-rk3328_defconfig
Size RK3399 boards are supported (aarch64):
@@ -310,6 +311,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
+Booting from an SD card on Pine64 Rock64 (RK3328) +================================================= + +For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin: + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create TPL/SPL image + + => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => cat spl/u-boot-spl.bin >> idbloader.img + + - Write TPL/SPL image at 64 sector + + => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 + + - Write u-boot image tree blob at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384 + Booting from an SD card on RK3399 =================================
participants (4)
-
Kever Yang -
Matwey V. Kornilov -
Simon Glass -
Vagrant Cascadian