T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue.

Signed-off-by: Zhao Qiang B45475@freescale.com --- changes for v2 - modify the commit message changes for v3 - use CONFIG_FSL_PCIE_RESET instead of CONFIG_FSL_PCIE_T2080QDS_RESET

drivers/pci/fsl_pci_init.c | 15 +++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 16 insertions(+)

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..152045e 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; +#ifdef CONFIG_FSL_PCIE_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + &ltssm); + udelay(1000); + } +#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..839896a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */