RE: [U-Boot-Users] [patch] Fix DDR6 errata on TQM834x boards
Kumar Gala wrote on Thursday, March 09, 2006 6:18 PM:
Why dont you make this a runtime check since I believe this errata is suppose to be fixed in rev2.0
Something like:
if (((get_pvr() >> 4) & 0xf) == 1) { ...}
Um, in my opinion the patch does a runtime check of the cpu revision, only the written value is dependent on the configured CAS latency. Or am I missing someting?
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index dada673..b9fd5bd 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -405,4 +405,28 @@ static void set_ddr_config(void) { (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); SYNC; + + /* Workaround for DDR6 Erratum + * see MPC8349E Device Errata Rev.8, 2/2006 + * This workaround influences the MPC internal "input enables" + * dependent on CAS latency and MPC revision. According to errata + * sheet the internal reserved registers for this workaround are + * not available from revision 2.0 and up. + */ + + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 + * (0x200) + */ + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { + + /* There is a internal reserved register at IMMRBAR+0x2F00 + * which has to be written with a certain value defined by + * errata sheet. + */ +#if defined(DDR_CASLAT_20) + *((u8 *)im + 0x2f00) = 0x201c0000; +#else + *((u8 *)im + 0x2f00) = 0x202c0000; +#endif + } }
Regards, Martin
In message 47F3F98010FF784EBEE6526EAAB078D1C060A6@tq-mailsrv.tq-net.de you wrote:
Um, in my opinion the patch does a runtime check of the cpu revision, only the written value is dependent on the configured CAS latency.
Configured where?
+#if defined(DDR_CASLAT_20)
I can't find any definition or use of DDR_CASLAT_20 anywhere in U-Boot...
Best regards,
Wolfgang Denk
On Mar 10, 2006, at 1:16 AM, Martin Krause wrote:
Kumar Gala wrote on Thursday, March 09, 2006 6:18 PM:
Why dont you make this a runtime check since I believe this errata is suppose to be fixed in rev2.0
Something like:
if (((get_pvr() >> 4) & 0xf) == 1) { ...}
Um, in my opinion the patch does a runtime check of the cpu revision, only the written value is dependent on the configured CAS latency. Or am I missing someting?
My bad, didn't see the checking of spridr.
- kumar
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index dada673..b9fd5bd 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -405,4 +405,28 @@ static void set_ddr_config(void) { (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); SYNC;
- /* Workaround for DDR6 Erratum
* see MPC8349E Device Errata Rev.8, 2/2006* This workaround influences the MPC internal "input enables"* dependent on CAS latency and MPC revision. According to errata* sheet the internal reserved registers for this workaround are* not available from revision 2.0 and up.*/- /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
* (0x200)*/- if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
/* There is a internal reserved register at IMMRBAR+0x2F00* which has to be written with a certain value defined by* errata sheet.*/+#if defined(DDR_CASLAT_20)
*((u8 *)im + 0x2f00) = 0x201c0000;+#else
*((u8 *)im + 0x2f00) = 0x202c0000;+#endif
- }
}
Regards, Martin
participants (3)
-
Kumar Gala -
Martin Krause -
Wolfgang Denk