[U-Boot] [PATCH v1 0/2] sunxi: A64: support I2C and R_I2C
This changeset adds the necessary defines and pin-config to enable I2C and R_I2C on the sun50iw1p1 (A64).
Tested on the A64-uQ7.
Philipp Tomsich (2): sunxi (sun50i): support i2c on A64 (pin-config, clocking) sunxi (sun50i): support R_I2C on A64 (pin-config, clocking)
arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++++ arch/arm/mach-sunxi/Makefile | 1 + board/sunxi/board.c | 29 ++++++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-)
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/clock.c | 2 ++ board/sunxi/board.c | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 7cdf5a3..b85ca22 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -109,120 +109,123 @@ struct sunxi_gpio_reg { enum sunxi_gpio_number { SUNXI_GPIO_A_START = 0, SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), SUNXI_GPIO_L_START = 352, SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), SUNXI_GPIO_AXP0_START = 1024, };
/* SUNXI GPIO number definitions */ #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_DISABLE 7
#define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 #define SUN4I_GPB_TWI2 2 #define SUN5I_GPB_TWI2 2 #define SUN6I_GPB_TWI3 4 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 #define SUN8I_A83T_GPB_UART0 2 #define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SPI0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 #define SUN50I_GPC_SPI0 4
#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3
#define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 +#define SUN50I_GPE_TWI2 3
#define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 #define SUN8I_GPF_UART0 3
#define SUN4I_GPG_SDC1 4 #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 #define SUN6I_GPG_TWI3 2 #define SUN6I_GPG_UART2 2 #define SUN5I_GPG_UART1 4 #define SUN6I_GPG_USB3 3
#define SUN6I_GPH_PWM 2 #define SUN8I_GPH_PWM 2 #define SUN4I_GPH_SDC1 5 #define SUN6I_GPH_TWI0 2 #define SUN8I_GPH_TWI0 2 +#define SUN50I_GPH_TWI0 2 #define SUN6I_GPH_TWI1 2 #define SUN8I_GPH_TWI1 2 +#define SUN50I_GPH_TWI1 2 #define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUN9I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2 #define SUN7I_GPI_TWI3 3 #define SUN7I_GPI_TWI4 3
#define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL_R_RSB 2 #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2
#define SUN9I_GPN_R_RSB 3
/* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" #define SUNXI_GPIO_AXP0_VBUS_DETECT 4 #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 #define SUNXI_GPIO_AXP0_GPIO_COUNT 6
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index e6f53f9..457a076 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -41,31 +41,33 @@ int clock_init(void) int clock_twi_onoff(int port, int state) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if !defined(CONFIG_MACH_SUN50I) if (port == 5) { if (state) prcm_apb0_enable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); else prcm_apb0_disable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); return 0; } +#endif
/* set the apb clock gate and reset for twi */ if (state) { setbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); } else { clrbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); clrbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); }
return 0; } #endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index bba9b7c..a47b113 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -485,90 +485,108 @@ int board_mmc_init(bd_t *bis) void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); + /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */ + sunxi_gpio_set_pull(SUNXI_GPH(0), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); + clock_twi_onoff(0, 1); #endif #endif
#ifdef CONFIG_I2C1_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); + /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */ + sunxi_gpio_set_pull(SUNXI_GPH(2), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_pull(SUNXI_GPH(3), SUNXI_GPIO_PULL_UP); + clock_twi_onoff(1, 1); #endif #endif
#ifdef CONFIG_I2C2_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); + clock_twi_onoff(2, 1); #endif #endif
#ifdef CONFIG_I2C3_ENABLE #if defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN6I) && defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN6I_GPB_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPB(5), SUN6I_GPB_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); clock_twi_onoff(3, 1); #endif #endif
#ifdef CONFIG_I2C4_ENABLE #if defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); clock_twi_onoff(4, 1); #endif #endif
#ifdef CONFIG_R_I2C_ENABLE clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif }
#ifdef CONFIG_SPL_BUILD
On 17/02/17 17:43, Philipp Tomsich wrote:
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/clock.c | 2 ++ board/sunxi/board.c | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 7cdf5a3..b85ca22 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -109,120 +109,123 @@ struct sunxi_gpio_reg { enum sunxi_gpio_number { SUNXI_GPIO_A_START = 0, SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), SUNXI_GPIO_L_START = 352, SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), SUNXI_GPIO_AXP0_START = 1024, };
/* SUNXI GPIO number definitions */ #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_DISABLE 7
#define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 #define SUN4I_GPB_TWI2 2 #define SUN5I_GPB_TWI2 2 #define SUN6I_GPB_TWI3 4 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 #define SUN8I_A83T_GPB_UART0 2 #define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SPI0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 #define SUN50I_GPC_SPI0 4
#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3
#define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 +#define SUN50I_GPE_TWI2 3
#define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 #define SUN8I_GPF_UART0 3
#define SUN4I_GPG_SDC1 4 #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 #define SUN6I_GPG_TWI3 2 #define SUN6I_GPG_UART2 2 #define SUN5I_GPG_UART1 4 #define SUN6I_GPG_USB3 3
#define SUN6I_GPH_PWM 2 #define SUN8I_GPH_PWM 2 #define SUN4I_GPH_SDC1 5 #define SUN6I_GPH_TWI0 2 #define SUN8I_GPH_TWI0 2 +#define SUN50I_GPH_TWI0 2 #define SUN6I_GPH_TWI1 2 #define SUN8I_GPH_TWI1 2 +#define SUN50I_GPH_TWI1 2 #define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUN9I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2 #define SUN7I_GPI_TWI3 3 #define SUN7I_GPI_TWI4 3
#define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL_R_RSB 2 #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2
#define SUN9I_GPN_R_RSB 3
/* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" #define SUNXI_GPIO_AXP0_VBUS_DETECT 4 #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 #define SUNXI_GPIO_AXP0_GPIO_COUNT 6
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index e6f53f9..457a076 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -41,31 +41,33 @@ int clock_init(void) int clock_twi_onoff(int port, int state) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if !defined(CONFIG_MACH_SUN50I) if (port == 5) { if (state) prcm_apb0_enable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); else prcm_apb0_disable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); return 0; } +#endif
/* set the apb clock gate and reset for twi */ if (state) { setbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); } else { clrbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); clrbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); }
return 0; } #endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index bba9b7c..a47b113 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -485,90 +485,108 @@ int board_mmc_init(bd_t *bis) void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
- /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */
- sunxi_gpio_set_pull(SUNXI_GPH(0), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
Is this specific to your board? Which isn't officially supported yet?
And having a DM conversion would make this easily fixable via DT, I guess?
- clock_twi_onoff(0, 1);
#endif #endif
#ifdef CONFIG_I2C1_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
- /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */
- sunxi_gpio_set_pull(SUNXI_GPH(2), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_pull(SUNXI_GPH(3), SUNXI_GPIO_PULL_UP);
Same here.
Other than that the pins and mux match the manual.
Cheers, Andre.
- clock_twi_onoff(1, 1);
#endif #endif
#ifdef CONFIG_I2C2_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
- clock_twi_onoff(2, 1);
#endif #endif
#ifdef CONFIG_I2C3_ENABLE #if defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN6I) && defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN6I_GPB_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPB(5), SUN6I_GPB_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); clock_twi_onoff(3, 1); #endif #endif
#ifdef CONFIG_I2C4_ENABLE #if defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); clock_twi_onoff(4, 1); #endif #endif
#ifdef CONFIG_R_I2C_ENABLE clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif }
#ifdef CONFIG_SPL_BUILD
On 18 Feb 2017, at 02:15, André Przywara andre.przywara@arm.com wrote:
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index bba9b7c..a47b113 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -485,90 +485,108 @@ int board_mmc_init(bd_t *bis) void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
- /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */
- sunxi_gpio_set_pull(SUNXI_GPH(0), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
Is this specific to your board?
No. This is board-specific for any board. Every I2C bus will need pull-ups, but it’s not defined where on the bus these should/will be located. There’s even a few I2C peripherals that have the pull-ups integrated.
In other words: this was one of many things that triggered me going after support DM (and it was the one change that caused me to look at the size of the SPL and whether there’s still space available for DM drivers when using OF_PLATDATA … but we both know the conclusion).
Which isn't officially supported yet?
I can send patches with the board-specific DTS and defconfig, if that helps ;-)
Just wanted until we get dual-IO SPI reads validated (and the DM changes merged), so it can be a single changeset instead of relying on multiple updates to the same files.
If you think it’s worthwhile to send out a defconfig that doesn’t depend on DM together with the DTS (without the gpiobank-entries), let me know.
And having a DM conversion would make this easily fixable via DT, I guess?
Yes. But that will still leave the SPL/TPL discussion for another day, as the SPL still depends on these programmatic settings.
Our board’s early-stage normally shouldn't need to do anything on this I2C bus, but customer boards may come up with a use for it (image this going towards battery/power managing circuitry on a baseboard).
Regards, Philipp.
Hi,
On 18/02/17 12:03, Dr. Philipp Tomsich wrote:
On 18 Feb 2017, at 02:15, André Przywara <andre.przywara@arm.com mailto:andre.przywara@arm.com> wrote:
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index bba9b7c..a47b113 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -485,90 +485,108 @@ int board_mmc_init(bd_t *bis) void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I) +sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); +sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); +/* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */ +sunxi_gpio_set_pull(SUNXI_GPH(0), SUNXI_GPIO_PULL_UP); +sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
Is this specific to your board?
No. This is board-specific for any board. Every I2C bus will need pull-ups, but it’s not defined where on the bus these should/will be located. There’s even a few I2C peripherals that have the pull-ups integrated.
I think I got this, but it's just that no other SoC above is doing this, also your comment hints at this being specific to your board. So for the sake of a generic A64 I2C support patch, I'd rather remove those lines from this file for now. You could keep a separate patch that fixes this for your board build.
In other words: this was one of many things that triggered me going after support DM (and it was the one change that caused me to look at the size of the SPL and whether there’s still space available for DM drivers when using OF_PLATDATA … but we both know the conclusion).
Which isn't officially supported yet?
I can send patches with the board-specific DTS and defconfig, if that helps ;-)
You can of course always do, but to be honest this was more a rhetorical question. I'd rather avoid putting some board specific code into this function in this way. I clearly see where you are going to, but please keep this patch sane.
Just wanted until we get dual-IO SPI reads validated (and the DM changes merged), so it can be a single changeset instead of relying on multiple updates to the same files.
If you think it’s worthwhile to send out a defconfig that doesn’t depend on DM together with the DTS (without the gpiobank-entries), let me know.
I don't think it's necessary for now, we have enough stuff on our plate already ;-) All of those patches seem to work toward a saner board specific configuration, so you could post your defconfig & DT at the end to motivate these changes.
And having a DM conversion would make this easily fixable via DT, I guess?
Yes. But that will still leave the SPL/TPL discussion for another day, as the SPL still depends on these programmatic settings.
Our board’s early-stage normally shouldn't need to do anything on this I2C bus, but customer boards may come up with a use for it (image this going towards battery/power managing circuitry on a baseboard).
In this case we should definitely remove these three lines.
Cheers, Andre.
On 20 Feb 2017, at 11:18, Andre Przywara andre.przywara@arm.com wrote:
Our board’s early-stage normally shouldn't need to do anything on this I2C bus, but customer boards may come up with a use for it (image this going towards battery/power managing circuitry on a baseboard).
In this case we should definitely remove these three lines.
I should have said “we don’t do anything with this I2C bus, but it’s available for customer use via the edge connector and a header on our eval-board”.
As there’s no way to enable pull-ups via a command in U-Boot, I’d prefer to keep these pull ups configured.
Regards, Philipp.
Hi,
On 20/02/17 10:21, Dr. Philipp Tomsich wrote:
On 20 Feb 2017, at 11:18, Andre Przywara <andre.przywara@arm.com mailto:andre.przywara@arm.com> wrote:
Our board’s early-stage normally shouldn't need to do anything on this I2C bus, but customer boards may come up with a use for it (image this going towards battery/power managing circuitry on a baseboard).
In this case we should definitely remove these three lines.
I should have said “we don’t do anything with this I2C bus, but it’s available for customer use via the edge connector and a header on our eval-board”.
As there’s no way to enable pull-ups via a command in U-Boot, I’d prefer to keep these pull ups configured.
So either make this a separate patch or use some other method of enabling this, but please keep this board specific setting separate from the SoC enablement.
Cheers, Andre.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/clock.c | 2 -- board/sunxi/board.c | 11 ++++++++++- 4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b85ca22..b820dd1 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -109,123 +109,124 @@ struct sunxi_gpio_reg { enum sunxi_gpio_number { SUNXI_GPIO_A_START = 0, SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), SUNXI_GPIO_L_START = 352, SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), SUNXI_GPIO_AXP0_START = 1024, };
/* SUNXI GPIO number definitions */ #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_DISABLE 7
#define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 #define SUN4I_GPB_TWI2 2 #define SUN5I_GPB_TWI2 2 #define SUN6I_GPB_TWI3 4 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 #define SUN8I_A83T_GPB_UART0 2 #define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SPI0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 #define SUN50I_GPC_SPI0 4
#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3
#define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 #define SUN50I_GPE_TWI2 3
#define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 #define SUN8I_GPF_UART0 3
#define SUN4I_GPG_SDC1 4 #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 #define SUN6I_GPG_TWI3 2 #define SUN6I_GPG_UART2 2 #define SUN5I_GPG_UART1 4 #define SUN6I_GPG_USB3 3
#define SUN6I_GPH_PWM 2 #define SUN8I_GPH_PWM 2 #define SUN4I_GPH_SDC1 5 #define SUN6I_GPH_TWI0 2 #define SUN8I_GPH_TWI0 2 #define SUN50I_GPH_TWI0 2 #define SUN6I_GPH_TWI1 2 #define SUN8I_GPH_TWI1 2 #define SUN50I_GPH_TWI1 2 #define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUN9I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2 #define SUN7I_GPI_TWI3 3 #define SUN7I_GPI_TWI4 3
#define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL_R_RSB 2 #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 +#define SUN50I_GPL_R_TWI 2 #define SUN8I_GPL_R_UART 2
#define SUN9I_GPN_R_RSB 3
/* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" #define SUNXI_GPIO_AXP0_VBUS_DETECT 4 #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 #define SUNXI_GPIO_AXP0_GPIO_COUNT 6
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 866bcf7..4487c31 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o obj-$(CONFIG_MACH_SUN9I) += prcm.o +obj-$(CONFIG_MACH_SUN50I) += prcm.o obj-$(CONFIG_MACH_SUN6I) += p2wi.o obj-$(CONFIG_MACH_SUN8I) += rsb.o obj-$(CONFIG_MACH_SUN9I) += rsb.o diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index 457a076..e6f53f9 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -41,33 +41,31 @@ int clock_init(void) int clock_twi_onoff(int port, int state) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-#if !defined(CONFIG_MACH_SUN50I) if (port == 5) { if (state) prcm_apb0_enable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); else prcm_apb0_disable( PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); return 0; } -#endif
/* set the apb clock gate and reset for twi */ if (state) { setbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); } else { clrbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_TWI_SHIFT + port)); clrbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); }
return 0; } #endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index a47b113..89edf2e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -485,108 +485,117 @@ int board_mmc_init(bd_t *bis) void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN50I) sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */ sunxi_gpio_set_pull(SUNXI_GPH(0), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); clock_twi_onoff(0, 1); #endif #endif
#ifdef CONFIG_I2C1_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN50I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); /* The A64-uQ7 doesn't have external pull-ups for I2C[01]. */ sunxi_gpio_set_pull(SUNXI_GPH(2), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_pull(SUNXI_GPH(3), SUNXI_GPIO_PULL_UP); clock_twi_onoff(1, 1); #endif #endif
#ifdef CONFIG_I2C2_ENABLE #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); clock_twi_onoff(2, 1); #elif defined(CONFIG_MACH_SUN50I) sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); clock_twi_onoff(2, 1); #endif #endif
#ifdef CONFIG_I2C3_ENABLE #if defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN6I) && defined(CONFIG_SUNXI_PANGOLIN) sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN6I_GPB_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPB(5), SUN6I_GPB_TWI3); clock_twi_onoff(3, 1); #elif defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); clock_twi_onoff(3, 1); #endif #endif
#ifdef CONFIG_I2C4_ENABLE #if defined(CONFIG_MACH_SUN7I) sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); clock_twi_onoff(4, 1); #endif #endif
-#ifdef CONFIG_R_I2C_ENABLE +#if defined(CONFIG_R_I2C_ENABLE) +#if defined(CONFIG_MACH_SUN50I) + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); + /* The A64-uQ7 doesn't have external pull-ups for R_I2C. */ + sunxi_gpio_set_pull(SUNXI_GPL(8), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_pull(SUNXI_GPL(9), SUNXI_GPIO_PULL_UP); +#else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif +#endif }
#ifdef CONFIG_SPL_BUILD
participants (4)
-
Andre Przywara -
André Przywara
-
Dr. Philipp Tomsich -
Philipp Tomsich