[U-Boot] [PATCH v2 1/3] x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/mtrr.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index d5a825d..ac8765f 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -17,6 +17,8 @@ #include <asm/msr.h> #include <asm/mtrr.h>
+DECLARE_GLOBAL_DATA_PTR; + /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state) {
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - Use space instead of tab to indent in arch_global_data
arch/x86/cpu/cpu.c | 7 +++++++ arch/x86/include/asm/global_data.h | 13 +++++++------ 2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 30e5069..ed7905c 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -223,6 +223,11 @@ static bool has_cpuid(void) return flag_is_changeable_p(X86_EFLAGS_ID); }
+static bool has_mtrr(void) +{ + return cpuid_edx(0x00000001) & (1 << 12) ? true : false; +} + static int build_vendor_name(char *vendor_name) { struct cpuid_result result; @@ -318,6 +323,8 @@ int x86_cpu_init_f(void) gd->arch.x86_model = c.x86_model; gd->arch.x86_mask = c.x86_mask; gd->arch.x86_device = cpu.device; + + gd->arch.has_mtrr = has_mtrr(); }
return 0; diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 24e3052..243ed5c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -44,11 +44,11 @@ struct mtrr_request {
/* Architecture-specific global data */ struct arch_global_data { - struct global_data *gd_addr; /* Location of Global Data */ - uint8_t x86; /* CPU family */ - uint8_t x86_vendor; /* CPU vendor */ - uint8_t x86_model; - uint8_t x86_mask; + struct global_data *gd_addr; /* Location of Global Data */ + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; uint32_t x86_device; uint64_t tsc_base; /* Initial value returned by rdtsc() */ uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */ @@ -60,10 +60,11 @@ struct arch_global_data { const struct pch_gpio_map *gpio_map; /* board GPIO map */ struct memory_info meminfo; /* Memory information */ #ifdef CONFIG_HAVE_FSP - void *hob_list; /* FSP HOB list */ + void *hob_list; /* FSP HOB list */ #endif struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; int mtrr_req_count; + int has_mtrr; };
#endif
On 21 January 2015 at 20:29, Bin Meng bmeng.cn@gmail.com wrote:
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Use space instead of tab to indent in arch_global_data
arch/x86/cpu/cpu.c | 7 +++++++ arch/x86/include/asm/global_data.h | 13 +++++++------ 2 files changed, 14 insertions(+), 6 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
(for reference, normally we would do this sort of clean-up in a separate patch)
Regards, Simon
On 22 January 2015 at 08:05, Simon Glass sjg@chromium.org wrote:
On 21 January 2015 at 20:29, Bin Meng bmeng.cn@gmail.com wrote:
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Use space instead of tab to indent in arch_global_data
arch/x86/cpu/cpu.c | 7 +++++++ arch/x86/include/asm/global_data.h | 13 +++++++------ 2 files changed, 14 insertions(+), 6 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
(for reference, normally we would do this sort of clean-up in a separate patch)
Applied to u-boot-x86, thanks!
On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - Return -ENOSYS in mtrr_commit() and mtrr_add_request() when MTRR MSR is not implemented in the processor - Add return value description of mtrr_commit() and mtrr_add_request() - Ignore -ENOSYS in init_cache_f_r() in arch/x86/lib/init_helpers.c
arch/x86/cpu/mtrr.c | 12 ++++++++++++ arch/x86/include/asm/mtrr.h | 5 ++++- arch/x86/lib/init_helpers.c | 4 +++- 3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index ac8765f..5d36b3e 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state) { + if (!gd->arch.has_mtrr) + return; + state->enable_cache = dcache_status();
if (state->enable_cache) @@ -33,6 +36,9 @@ void mtrr_open(struct mtrr_state *state) /* Clean up after adjusting MTRRs, and enable them */ void mtrr_close(struct mtrr_state *state) { + if (!gd->arch.has_mtrr) + return; + wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); if (state->enable_cache) enable_caches(); @@ -45,6 +51,9 @@ int mtrr_commit(bool do_caches) uint64_t mask; int i;
+ if (!gd->arch.has_mtrr) + return -ENOSYS; + mtrr_open(&state); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) { mask = ~(req->size - 1); @@ -66,6 +75,9 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) struct mtrr_request *req; uint64_t mask;
+ if (!gd->arch.has_mtrr) + return -ENOSYS; + if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) return -ENOSPC; req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 3c11740..fda4eae 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -65,7 +65,6 @@ void mtrr_open(struct mtrr_state *state); * * @state: Structure from mtrr_open() */ -/* */ void mtrr_close(struct mtrr_state *state);
/** @@ -76,6 +75,8 @@ void mtrr_close(struct mtrr_state *state); * @type: Requested type (MTRR_TYPE_) * @start: Start address * @size: Size + * + * @return: 0 on success, non-zero on failure */ int mtrr_add_request(int type, uint64_t start, uint64_t size);
@@ -86,6 +87,8 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size); * It must be called with caches disabled. * * @do_caches: true if caches are currently on + * + * @return: 0 on success, non-zero on failure */ int mtrr_commit(bool do_caches);
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index fc211d9..5097ca2 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -7,6 +7,7 @@ #include <common.h> #include <fdtdec.h> #include <spi.h> +#include <asm/errno.h> #include <asm/mtrr.h> #include <asm/sections.h>
@@ -71,7 +72,8 @@ int init_cache_f_r(void) int ret;
ret = mtrr_commit(false); - if (ret) + /* If MTRR MSR is not implemented by the processor, just ignore it */ + if (ret && ret != -ENOSYS) return ret; #endif /* Initialise the CPU cache(s) */
On 21 January 2015 at 20:29, Bin Meng bmeng.cn@gmail.com wrote:
On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Return -ENOSYS in mtrr_commit() and mtrr_add_request() when MTRR MSR is not implemented in the processor
- Add return value description of mtrr_commit() and mtrr_add_request()
- Ignore -ENOSYS in init_cache_f_r() in arch/x86/lib/init_helpers.c
arch/x86/cpu/mtrr.c | 12 ++++++++++++ arch/x86/include/asm/mtrr.h | 5 ++++- arch/x86/lib/init_helpers.c | 4 +++- 3 files changed, 19 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 22 January 2015 at 08:06, Simon Glass sjg@chromium.org wrote:
On 21 January 2015 at 20:29, Bin Meng bmeng.cn@gmail.com wrote:
On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Return -ENOSYS in mtrr_commit() and mtrr_add_request() when MTRR MSR is not implemented in the processor
- Add return value description of mtrr_commit() and mtrr_add_request()
- Ignore -ENOSYS in init_cache_f_r() in arch/x86/lib/init_helpers.c
arch/x86/cpu/mtrr.c | 12 ++++++++++++ arch/x86/include/asm/mtrr.h | 5 ++++- arch/x86/lib/init_helpers.c | 4 +++- 3 files changed, 19 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
On 21 January 2015 at 20:29, Bin Meng bmeng.cn@gmail.com wrote:
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v2: None
Applied to u-boot-x86, thanks!
participants (2)
-
Bin Meng -
Simon Glass