[PATCH 0/8] rockchip: Add PCIe host support
Thanks to Patrick for initial work done on this.
This series support PCIe host controller support on rockchip rk3399 platform.
Works well on rk3399 boards like rock960, nanopc-t4 and roc-kr3399-pc-mezzanine board as Gen1 configurable host.
It has dependency with v5.7-rc1 dts(i) sync series[1]
[1] https://patchwork.ozlabs.org/project/uboot/cover/20200425105319.12009-1-jaga...
Any inputs? Jagan.
Jagan Teki (8): iopoll: Add dealy to read poll iopoll: Add readl_poll_sleep_timeout clk: rk3399: Enable PCIE_PHY clock clk: rk3399: Disable PCIE_PHY clock pci: Add Rockchip PCIe controller driver pci: Add Rockchip PCIe PHY controller driver rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 rockchip: Enable PCIe/M.2 on rock960 board
arch/arm/dts/rk3399-u-boot.dtsi | 1 + board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 + configs/nanopc-t4-rk3399_defconfig | 4 + configs/roc-pc-mezzanine-rk3399_defconfig | 4 + configs/rock960-rk3399_defconfig | 5 + drivers/clk/rockchip/clk_rk3399.c | 32 ++ drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 484 ++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 142 ++++++ drivers/pci/pcie_rockchip_phy.c | 205 +++++++++ include/linux/iopoll.h | 23 +- 12 files changed, 920 insertions(+), 9 deletions(-) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h create mode 100644 drivers/pci/pcie_rockchip_phy.c
Some drivers and other bsp code not only poll the register with timeout but also required to delay on each transaction.
This patch add that requirement by adding sleep_us variable so-that read_poll_timeout now support delay as well.
Cc: Tom Rini trini@konsulko.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/linux/iopoll.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h index ab0ae1969a..0bbd757939 100644 --- a/include/linux/iopoll.h +++ b/include/linux/iopoll.h @@ -16,6 +16,7 @@ * @addr: Address to poll * @val: Variable to read the value into * @cond: Break condition (usually involving @val) + * @sleep_us: Maximum time to sleep in us * @timeout_us: Timeout in us, 0 means never timeout * * Returns 0 on success and -ETIMEDOUT upon a timeout. In either @@ -24,7 +25,7 @@ * When available, you'll probably want to use one of the specialized * macros defined below rather than this macro directly. */ -#define readx_poll_timeout(op, addr, val, cond, timeout_us) \ +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \ ({ \ unsigned long timeout = timer_get_us() + timeout_us; \ for (;;) { \ @@ -35,33 +36,34 @@ (val) = op(addr); \ break; \ } \ + if (sleep_us) \ + udelay(sleep_us); \ } \ (cond) ? 0 : -ETIMEDOUT; \ })
- #define readb_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readb, addr, val, cond, timeout_us) + readx_poll_timeout(readb, addr, val, cond, false, timeout_us)
#define readw_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readw, addr, val, cond, timeout_us) + readx_poll_timeout(readw, addr, val, cond, false, timeout_us)
#define readl_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readl, addr, val, cond, timeout_us) + readx_poll_timeout(readl, addr, val, cond, false, timeout_us)
#define readq_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readq, addr, val, cond, timeout_us) + readx_poll_timeout(readq, addr, val, cond, false, timeout_us)
#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us) + readx_poll_timeout(readb_relaxed, addr, val, cond, false, timeout_us)
#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us) + readx_poll_timeout(readw_relaxed, addr, val, cond, false, timeout_us)
#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us) + readx_poll_timeout(readl_relaxed, addr, val, cond, false, timeout_us)
#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \ - readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us) + readx_poll_timeout(readq_relaxed, addr, val, cond, false, timeout_us)
#endif /* _LINUX_IOPOLL_H */
Add readl poll API with sleep and timeout support.
Cc: Tom Rini trini@konsulko.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/linux/iopoll.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h index 0bbd757939..e087f23271 100644 --- a/include/linux/iopoll.h +++ b/include/linux/iopoll.h @@ -42,6 +42,9 @@ (cond) ? 0 : -ETIMEDOUT; \ })
+#define readl_poll_sleep_timeout(addr, val, cond, sleep_us, timeout_us) \ + readx_poll_timeout(readl, addr, val, cond, sleep_us, timeout_us) + #define readb_poll_timeout(addr, val, cond, timeout_us) \ readx_poll_timeout(readb, addr, val, cond, false, timeout_us)
Add PCIE_PHY clock enablement support on rk3399 clock driver.
This clock is enabled by default, so do nothing if it triggers during the PCIe PHY probe other PHY users on this clock will simply fail.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index d822acace1..8e069fbade 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1071,12 +1071,27 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, return -ENOENT; }
+static int rk3399_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case SCLK_PCIEPHY_REF: + /* do nothing, clk is enabled by default */ + break; + default: + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return 0; +} + static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3399_clk_set_parent, #endif + .enable = rk3399_clk_enable, };
#ifdef CONFIG_SPL_BUILD
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:49 +0530
Add PCIE_PHY clock enablement support on rk3399 clock driver.
This clock is enabled by default, so do nothing if it triggers during the PCIe PHY probe other PHY users on this clock will simply fail.
This breaks Ethernet on my firefly-rk3399, and I suspect it does the same on other boards:
In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: Firefly-RK3399 Board Net: failed to enable clock 0 No ethernet found.
Looking at the px30 clock driver, I think you need to add a few more clocks here:
SCLK_MAC, SCLK_MAC_RX, SCLK_MAC_TX, SCLK_MACREF, SCLK_MACREF_OUT, ACLK_GMAC, PCLK_GMAC
That makes it work again for me.
Cheers,
Mark
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index d822acace1..8e069fbade 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1071,12 +1071,27 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, return -ENOENT; }
+static int rk3399_clk_enable(struct clk *clk) +{
- switch (clk->id) {
- case SCLK_PCIEPHY_REF:
/* do nothing, clk is enabled by default */break;- default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);return -ENOENT;- }
- return 0;
+}
static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3399_clk_set_parent, #endif
- .enable = rk3399_clk_enable,
};
#ifdef CONFIG_SPL_BUILD
2.17.1
On Sun, Apr 26, 2020 at 1:54 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:49 +0530
Add PCIE_PHY clock enablement support on rk3399 clock driver.
This clock is enabled by default, so do nothing if it triggers during the PCIe PHY probe other PHY users on this clock will simply fail.
This breaks Ethernet on my firefly-rk3399, and I suspect it does the same on other boards:
Yes it does. It's affected by the v5.7-rc1 sync series. Will update the fixes on that series, thanks!
Add PCIE_PHY clock disablement support on rk3399 clock driver.
This would trigger if the PCIe PHY driver failed to initialize or power on the PHY.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 8e069fbade..2d447f96f7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk) return 0; }
+static int rk3399_clk_disable(struct clk *clk) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case SCLK_PCIEPHY_REF: + rk_clrreg(&priv->cru->clksel_con[18], BIT(7)); + break; + default: + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return 0; +} + static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, @@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = { .set_parent = rk3399_clk_set_parent, #endif .enable = rk3399_clk_enable, + .disable = rk3399_clk_disable, };
#ifdef CONFIG_SPL_BUILD
On 2020/4/25 下午7:03, Jagan Teki wrote:
Add PCIE_PHY clock disablement support on rk3399 clock driver.
This would trigger if the PCIe PHY driver failed to initialize or power on the PHY.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 8e069fbade..2d447f96f7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk) return 0; }
+static int rk3399_clk_disable(struct clk *clk) +{
- struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
- switch (clk->id) {
- case SCLK_PCIEPHY_REF:
rk_clrreg(&priv->cru->clksel_con[18], BIT(7));break;- default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);return -ENOENT;- }
- return 0;
+}
- static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate,
@@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = { .set_parent = rk3399_clk_set_parent, #endif .enable = rk3399_clk_enable,
.disable = rk3399_clk_disable, };
#ifdef CONFIG_SPL_BUILD
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP + bool "Enable Rockchip PCIe driver" + select DM_PCI + default y if ROCKCHIP_RK3399 + help + Say Y here if you want to enable PCIe controller support on + Rockchip SoCs. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip AXI PCIe host controller driver + * + * Copyright (c) 2016 Rockchip, Inc. + * Copyright (c) 2020 Amarula Solutions(India) + * Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com + * Copyright (c) 2019 Patrick Wildt patrick@blueri.se + * Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org + * + * Bits taken from Linux Rockchip PCIe host controller. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h> + +#include "pcie_rockchip.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct rockchip_pcie *priv = dev_get_priv(bus); + ulong value; + u32 off; + + off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) | + (PCI_FUNC(bdf) << 12) | (offset & ~0x3); + + if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) { + value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off); + *valuep = pci_conv_32_to_size(value, offset, size); + return 0; + } + + if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) { + value = readl(priv->axi_base + off); + *valuep = pci_conv_32_to_size(value, offset, size); + return 0; + } + + *valuep = pci_get_ff(size); + + return 0; +} + +static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct rockchip_pcie *priv = dev_get_priv(bus); + ulong old; + u32 off; + + off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) | + (PCI_FUNC(bdf) << 12) | (offset & ~0x3); + + if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) { + old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off); + value = pci_conv_size_to_32(old, value, offset, size); + writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off); + return 0; + } + + if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) { + old = readl(priv->axi_base + off); + value = pci_conv_size_to_32(old, value, offset, size); + writel(value, priv->axi_base + off); + return 0; + } + + return 0; +} + +static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{ + struct udevice *ctlr = pci_get_controller(priv->dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + u64 addr, size, offset; + u32 type; + int i, region; + + /* Use region 0 to map PCI configuration space. */ + writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0)); + writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0)); + writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID, + priv->apb_base + PCIE_ATR_OB_DESC0(0)); + writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0)); + + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY) + continue; + + if (hose->regions[i].flags == PCI_REGION_IO) + type = PCIE_ATR_HDR_IO; + else + type = PCIE_ATR_HDR_MEM; + + /* Only support identity mappings. */ + if (hose->regions[i].bus_start != + hose->regions[i].phys_start) + return -EINVAL; + + /* Only support mappings aligned on a region boundary. */ + addr = hose->regions[i].bus_start; + if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) + return -EINVAL; + + /* Mappings should lie between AXI and APB regions. */ + size = hose->regions[i].size; + if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE) + return -EINVAL; + if (addr + size > (u64)priv->apb_base) + return -EINVAL; + + offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE; + region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); + while (size > 0) { + writel(32 - 1, + priv->apb_base + PCIE_ATR_OB_ADDR0(region)); + writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region)); + writel(type | PCIE_ATR_HDR_RID, + priv->apb_base + PCIE_ATR_OB_DESC0(region)); + writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region)); + + addr += PCIE_ATR_OB_REGION_SIZE; + size -= PCIE_ATR_OB_REGION_SIZE; + region++; + } + } + + /* Passthrough inbound translations unmodified. */ + writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2)); + writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2)); + + return 0; +} + +static int rockchip_pcie_init_port(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + u32 cr, val, status; + int ret; + + if (dm_gpio_is_valid(&priv->ep_gpio)) + dm_gpio_set_value(&priv->ep_gpio, 0); + + ret = reset_assert(&priv->aclk_rst); + if (ret) { + dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_assert(&priv->pclk_rst); + if (ret) { + dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_assert(&priv->pm_rst); + if (ret) { + dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_assert(&priv->core_rst); + if (ret) { + dev_err(dev, "failed to assert core reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_assert(&priv->mgmt_rst); + if (ret) { + dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_assert(&priv->mgmt_sticky_rst); + if (ret) { + dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n", + ret); + return ret; + } + + ret = reset_assert(&priv->pipe_rst); + if (ret) { + dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret); + return ret; + } + + udelay(10); + + ret = reset_deassert(&priv->pm_rst); + if (ret) { + dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_deassert(&priv->aclk_rst); + if (ret) { + dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_deassert(&priv->pclk_rst); + if (ret) { + dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret); + return ret; + } + + /* Select GEN1 for now */ + cr = PCIE_CLIENT_GEN_SEL_1; + /* Set Root complex mode */ + cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; + writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG); + + ret = reset_deassert(&priv->mgmt_sticky_rst); + if (ret) { + dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n", + ret); + return ret; + } + + ret = reset_deassert(&priv->core_rst); + if (ret) { + dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_deassert(&priv->mgmt_rst); + if (ret) { + dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_deassert(&priv->pipe_rst); + if (ret) { + dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret); + return ret; + } + + /* Enable Gen1 training */ + writel(PCIE_CLIENT_LINK_TRAIN_ENABLE, + priv->apb_base + PCIE_CLIENT_CONFIG); + + if (dm_gpio_is_valid(&priv->ep_gpio)) + dm_gpio_set_value(&priv->ep_gpio, 1); + + ret = readl_poll_sleep_timeout + (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1, + status, PCIE_LINK_UP(status), 20, 500 * 1000); + if (ret) { + dev_err(dev, "PCIe link training gen1 timeout!\n"); + return ret; + } + + /* Initialize Root Complex registers. */ + writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID); + writel(PCI_CLASS_BRIDGE_PCI << 16, + priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION); + writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS, + priv->apb_base + PCIE_LM_RCBAR); + + if (dev_read_bool(dev, "aspm-no-l0s")) { + val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP); + val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S; + writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP); + } + + /* Configure Address Translation. */ + ret = rockchip_pcie_atr_init(priv); + if (ret) { + dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq); + return ret; + } + + return 0; +} + +static int rockchip_pcie_set_vpcie(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + int ret; + + if (!IS_ERR(priv->vpcie3v3)) { + ret = regulator_set_enable(priv->vpcie3v3, true); + if (ret) { + dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", + ret); + return ret; + } + } + + ret = regulator_set_enable(priv->vpcie1v8, true); + if (ret) { + dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret); + goto err_disable_3v3; + } + + ret = regulator_set_enable(priv->vpcie0v9, true); + if (ret) { + dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret); + goto err_disable_1v8; + } + + return 0; + +err_disable_1v8: + regulator_set_enable(priv->vpcie1v8, false); +err_disable_3v3: + if (!IS_ERR(priv->vpcie3v3)) + regulator_set_enable(priv->vpcie3v3, false); + return ret; +} + +static int rockchip_pcie_parse_dt(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + int ret; + + priv->axi_base = dev_read_addr_name(dev, "axi-base"); + if (!priv->axi_base) + return -ENODEV; + + priv->apb_base = dev_read_addr_name(dev, "apb-base"); + if (!priv->axi_base) + return -ENODEV; + + ret = gpio_request_by_name(dev, "ep-gpios", 0, + &priv->ep_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "failed to find ep-gpios property\n"); + return ret; + } + + ret = reset_get_by_name(dev, "core", &priv->core_rst); + if (ret) { + dev_err(dev, "failed to get core reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst); + if (ret) { + dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst); + if (ret) { + dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst); + if (ret) { + dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "pm", &priv->pm_rst); + if (ret) { + dev_err(dev, "failed to get pm reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst); + if (ret) { + dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst); + if (ret) { + dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vpcie3v3-supply", + &priv->vpcie3v3); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vpcie1v8-supply", + &priv->vpcie1v8); + if (ret) { + dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vpcie0v9-supply", + &priv->vpcie0v9); + if (ret) { + dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +static int rockchip_pcie_probe(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + int ret; + + priv->first_busno = dev->seq; + priv->dev = dev; + + ret = rockchip_pcie_parse_dt(dev); + if (ret) + return ret; + + ret = rockchip_pcie_set_vpcie(dev); + if (ret) + return ret; + + ret = rockchip_pcie_init_port(dev); + if (ret) + return ret; + + dev_info(dev, "PCIE-%d: Link up (Bus%d)\n", + dev->seq, hose->first_busno); + + return 0; +} + +static const struct dm_pci_ops rockchip_pcie_ops = { + .read_config = rockchip_pcie_rd_conf, + .write_config = rockchip_pcie_wr_conf, +}; + +static const struct udevice_id rockchip_pcie_ids[] = { + { .compatible = "rockchip,rk3399-pcie" }, + { } +}; + +U_BOOT_DRIVER(rockchip_pcie) = { + .name = "rockchip_pcie", + .id = UCLASS_PCI, + .of_match = rockchip_pcie_ids, + .ops = &rockchip_pcie_ops, + .probe = rockchip_pcie_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_pcie), +}; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h new file mode 100644 index 0000000000..6ded5c9553 --- /dev/null +++ b/drivers/pci/pcie_rockchip.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Rockchip PCIe Headers + * + * Copyright (c) 2016 Rockchip, Inc. + * Copyright (c) 2020 Amarula Solutions(India) + * Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com + * Copyright (c) 2019 Patrick Wildt patrick@blueri.se + * + */ + +#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) + +#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_BASIC_STATUS1 0x0048 +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) +#define PCIE_LINK_UP(x) \ + (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) +#define PCIE_RC_NORMAL_BASE 0x800000 +#define PCIE_LM_BASE 0x900000 +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) +#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) +#define PCIE_LM_RCBARPIE BIT(19) +#define PCIE_LM_RCBARPIS BIT(20) +#define PCIE_RC_BASE 0xa00000 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) +#define PCIE_ATR_BASE 0xc00000 +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) +#define PCIE_ATR_HDR_MEM 0x2 +#define PCIE_ATR_HDR_IO 0x6 +#define PCIE_ATR_HDR_CFG_TYPE0 0xa +#define PCIE_ATR_HDR_CFG_TYPE1 0xb +#define PCIE_ATR_HDR_RID BIT(23) + +#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) +#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) + +struct rockchip_pcie { + fdt_addr_t axi_base; + fdt_addr_t apb_base; + int first_busno; + struct udevice *dev; + + /* resets */ + struct reset_ctl core_rst; + struct reset_ctl mgmt_rst; + struct reset_ctl mgmt_sticky_rst; + struct reset_ctl pipe_rst; + struct reset_ctl pm_rst; + struct reset_ctl pclk_rst; + struct reset_ctl aclk_rst; + + /* gpio */ + struct gpio_desc ep_gpio; + + /* vpcie regulators */ + struct udevice *vpcie12v; + struct udevice *vpcie3v3; + struct udevice *vpcie1v8; + struct udevice *vpcie0v9; +};
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:51 +0530
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Tried to get this to work on my firefly-rk3399 which made me notice some shortcomings:
1. The vpcie1v8 and vpcie0v9 supplies are optional, just like the vpcie3v3 supply.
2. The vpcie3v3 regulator check doesn't quite work.
See below for suggestions on how to fix this.
Sadly the NVME SSD doesn't seem to be happy and shows up as only 1023 MB. But that is probably not caused by this diff.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
- bool "Enable Rockchip PCIe driver"
- select DM_PCI
- default y if ROCKCHIP_RK3399
- help
Say Y here if you want to enable PCIe controller support onRockchip SoCs.endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong value;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- *valuep = pci_get_ff(size);
- return 0;
+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong old;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;- }
- return 0;
+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
- struct udevice *ctlr = pci_get_controller(priv->dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- u64 addr, size, offset;
- u32 type;
- int i, region;
- /* Use region 0 to map PCI configuration space. */
- writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
- writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
- writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
priv->apb_base + PCIE_ATR_OB_DESC0(0));- writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
- for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}- }
- /* Passthrough inbound translations unmodified. */
- writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
- writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
- return 0;
+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- u32 cr, val, status;
- int ret;
- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 0);- ret = reset_assert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_assert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;- }
- udelay(10);
- ret = reset_deassert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;- }
- /* Select GEN1 for now */
- cr = PCIE_CLIENT_GEN_SEL_1;
- /* Set Root complex mode */
- cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
- writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = reset_deassert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_deassert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;- }
- /* Enable Gen1 training */
- writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
priv->apb_base + PCIE_CLIENT_CONFIG);- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 1);- ret = readl_poll_sleep_timeout
(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);- if (ret) {
dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;- }
- /* Initialize Root Complex registers. */
- writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
- writel(PCI_CLASS_BRIDGE_PCI << 16,
priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);- writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
priv->apb_base + PCIE_LM_RCBAR);- if (dev_read_bool(dev, "aspm-no-l0s")) {
val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);- }
- /* Configure Address Translation. */
- ret = rockchip_pcie_atr_init(priv);
- if (ret) {
dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;- }
- return 0;
+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- if (!IS_ERR(priv->vpcie3v3)) {
I think this should be:
if (priv->vpcie3v3) {
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}- }
And to make this regulator optional, it needs an
if (priv->vpcie1v8) {
here.
- ret = regulator_set_enable(priv->vpcie1v8, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);goto err_disable_3v3;- }
}
if (priv->vpcie0v9) {
- ret = regulator_set_enable(priv->vpcie0v9, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);goto err_disable_1v8;- }
}
- return 0;
+err_disable_1v8:
if (priv->vpcie1v8)
- regulator_set_enable(priv->vpcie1v8, false);
+err_disable_3v3:
- if (!IS_ERR(priv->vpcie3v3))
if (priv->vpcie3v3)
regulator_set_enable(priv->vpcie3v3, false);- return ret;
+}
+static int rockchip_pcie_parse_dt(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- priv->axi_base = dev_read_addr_name(dev, "axi-base");
- if (!priv->axi_base)
return -ENODEV;- priv->apb_base = dev_read_addr_name(dev, "apb-base");
- if (!priv->axi_base)
return -ENODEV;- ret = gpio_request_by_name(dev, "ep-gpios", 0,
&priv->ep_gpio, GPIOD_IS_OUT);- if (ret) {
dev_err(dev, "failed to find ep-gpios property\n");return ret;- }
- ret = reset_get_by_name(dev, "core", &priv->core_rst);
- if (ret) {
dev_err(dev, "failed to get core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
&priv->vpcie3v3);- if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
&priv->vpcie1v8);- if (ret) {
To make this optional, make this
if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
&priv->vpcie0v9);- if (ret) {
The same here.
dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);return ret;- }
- return 0;
+}
+static int rockchip_pcie_probe(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- struct udevice *ctlr = pci_get_controller(dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- int ret;
- priv->first_busno = dev->seq;
- priv->dev = dev;
- ret = rockchip_pcie_parse_dt(dev);
- if (ret)
return ret;- ret = rockchip_pcie_set_vpcie(dev);
- if (ret)
return ret;- ret = rockchip_pcie_init_port(dev);
- if (ret)
return ret;- dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
dev->seq, hose->first_busno);- return 0;
+}
+static const struct dm_pci_ops rockchip_pcie_ops = {
- .read_config = rockchip_pcie_rd_conf,
- .write_config = rockchip_pcie_wr_conf,
+};
+static const struct udevice_id rockchip_pcie_ids[] = {
- { .compatible = "rockchip,rk3399-pcie" },
- { }
+};
+U_BOOT_DRIVER(rockchip_pcie) = {
- .name = "rockchip_pcie",
- .id = UCLASS_PCI,
- .of_match = rockchip_pcie_ids,
- .ops = &rockchip_pcie_ops,
- .probe = rockchip_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
+}; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h new file mode 100644 index 0000000000..6ded5c9553 --- /dev/null +++ b/drivers/pci/pcie_rockchip.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Rockchip PCIe Headers
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- */
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_BASIC_STATUS1 0x0048 +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) +#define PCIE_LINK_UP(x) \
- (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000 +#define PCIE_LM_BASE 0x900000 +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) +#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) +#define PCIE_LM_RCBARPIE BIT(19) +#define PCIE_LM_RCBARPIS BIT(20) +#define PCIE_RC_BASE 0xa00000 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) +#define PCIE_ATR_BASE 0xc00000 +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) +#define PCIE_ATR_HDR_MEM 0x2 +#define PCIE_ATR_HDR_IO 0x6 +#define PCIE_ATR_HDR_CFG_TYPE0 0xa +#define PCIE_ATR_HDR_CFG_TYPE1 0xb +#define PCIE_ATR_HDR_RID BIT(23)
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) +#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+struct rockchip_pcie {
- fdt_addr_t axi_base;
- fdt_addr_t apb_base;
- int first_busno;
- struct udevice *dev;
- /* resets */
- struct reset_ctl core_rst;
- struct reset_ctl mgmt_rst;
- struct reset_ctl mgmt_sticky_rst;
- struct reset_ctl pipe_rst;
- struct reset_ctl pm_rst;
- struct reset_ctl pclk_rst;
- struct reset_ctl aclk_rst;
- /* gpio */
- struct gpio_desc ep_gpio;
- /* vpcie regulators */
- struct udevice *vpcie12v;
- struct udevice *vpcie3v3;
- struct udevice *vpcie1v8;
- struct udevice *vpcie0v9;
+};
2.17.1
On Sun, Apr 26, 2020 at 12:23 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:51 +0530
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Tried to get this to work on my firefly-rk3399 which made me notice some shortcomings:
The vpcie1v8 and vpcie0v9 supplies are optional, just like the vpcie3v3 supply.
The vpcie3v3 regulator check doesn't quite work.
You mean the regulator check?
See below for suggestions on how to fix this.
Sadly the NVME SSD doesn't seem to be happy and shows up as only 1023 MB. But that is probably not caused by this diff.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"select DM_PCIdefault y if ROCKCHIP_RK3399helpSay Y here if you want to enable PCIe controller support onRockchip SoCs.endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong value;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}*valuep = pci_get_ff(size);return 0;+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong old;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;}return 0;+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
struct udevice *ctlr = pci_get_controller(priv->dev);struct pci_controller *hose = dev_get_uclass_priv(ctlr);u64 addr, size, offset;u32 type;int i, region;/* Use region 0 to map PCI configuration space. */writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(0));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));for (i = 0; i < hose->region_count; i++) {if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}}/* Passthrough inbound translations unmodified. */writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));return 0;+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);u32 cr, val, status;int ret;if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 0);ret = reset_assert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->core_rst);if (ret) {dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_assert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;}udelay(10);ret = reset_deassert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;}/* Select GEN1 for now */cr = PCIE_CLIENT_GEN_SEL_1;/* Set Root complex mode */cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);ret = reset_deassert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_deassert(&priv->core_rst);if (ret) {dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;}/* Enable Gen1 training */writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,priv->apb_base + PCIE_CLIENT_CONFIG);if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 1);ret = readl_poll_sleep_timeout(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);if (ret) {dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;}/* Initialize Root Complex registers. */writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);writel(PCI_CLASS_BRIDGE_PCI << 16,priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,priv->apb_base + PCIE_LM_RCBAR);if (dev_read_bool(dev, "aspm-no-l0s")) {val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);}/* Configure Address Translation. */ret = rockchip_pcie_atr_init(priv);if (ret) {dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;}return 0;+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);int ret;if (!IS_ERR(priv->vpcie3v3)) {I think this should be:
if (priv->vpcie3v3) {
I didn't find any issue with the board I have optional of this, but will check it.
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}}And to make this regulator optional, it needs an
if (priv->vpcie1v8) {
I can see from v5.7-rc1, 12v, 3v3 are optional and rest not If I'm not wrong.
Jagan.
From: Jagan Teki jagan@amarulasolutions.com Date: Sun, 26 Apr 2020 01:06:56 +0530
On Sun, Apr 26, 2020 at 12:23 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:51 +0530
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Tried to get this to work on my firefly-rk3399 which made me notice some shortcomings:
The vpcie1v8 and vpcie0v9 supplies are optional, just like the vpcie3v3 supply.
The vpcie3v3 regulator check doesn't quite work.
You mean the regulator check?
I mean the check wether the regulator is actually there in rockchip_pcie_set_vpcie(). See my suggested changes below.
See below for suggestions on how to fix this.
Sadly the NVME SSD doesn't seem to be happy and shows up as only 1023 MB. But that is probably not caused by this diff.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"select DM_PCIdefault y if ROCKCHIP_RK3399helpSay Y here if you want to enable PCIe controller support onRockchip SoCs.endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong value;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}*valuep = pci_get_ff(size);return 0;+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong old;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;}return 0;+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
struct udevice *ctlr = pci_get_controller(priv->dev);struct pci_controller *hose = dev_get_uclass_priv(ctlr);u64 addr, size, offset;u32 type;int i, region;/* Use region 0 to map PCI configuration space. */writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(0));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));for (i = 0; i < hose->region_count; i++) {if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}}/* Passthrough inbound translations unmodified. */writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));return 0;+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);u32 cr, val, status;int ret;if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 0);ret = reset_assert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->core_rst);if (ret) {dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_assert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;}udelay(10);ret = reset_deassert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;}/* Select GEN1 for now */cr = PCIE_CLIENT_GEN_SEL_1;/* Set Root complex mode */cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);ret = reset_deassert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_deassert(&priv->core_rst);if (ret) {dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;}/* Enable Gen1 training */writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,priv->apb_base + PCIE_CLIENT_CONFIG);if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 1);ret = readl_poll_sleep_timeout(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);if (ret) {dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;}/* Initialize Root Complex registers. */writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);writel(PCI_CLASS_BRIDGE_PCI << 16,priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,priv->apb_base + PCIE_LM_RCBAR);if (dev_read_bool(dev, "aspm-no-l0s")) {val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);}/* Configure Address Translation. */ret = rockchip_pcie_atr_init(priv);if (ret) {dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;}return 0;+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);int ret;if (!IS_ERR(priv->vpcie3v3)) {I think this should be:
if (priv->vpcie3v3) {I didn't find any issue with the board I have optional of this, but will check it.
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}}And to make this regulator optional, it needs an
if (priv->vpcie1v8) {I can see from v5.7-rc1, 12v, 3v3 are optional and rest not If I'm not wrong.
The devicetree binding is clear about it. See Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt.
And rk3399-firefly.dts doesn't add the properties.
On Sun, Apr 26, 2020 at 1:59 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sun, 26 Apr 2020 01:06:56 +0530
On Sun, Apr 26, 2020 at 12:23 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:51 +0530
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Tried to get this to work on my firefly-rk3399 which made me notice some shortcomings:
The vpcie1v8 and vpcie0v9 supplies are optional, just like the vpcie3v3 supply.
The vpcie3v3 regulator check doesn't quite work.
You mean the regulator check?
I mean the check wether the regulator is actually there in rockchip_pcie_set_vpcie(). See my suggested changes below.
See below for suggestions on how to fix this.
Sadly the NVME SSD doesn't seem to be happy and shows up as only 1023 MB. But that is probably not caused by this diff.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"select DM_PCIdefault y if ROCKCHIP_RK3399helpSay Y here if you want to enable PCIe controller support onRockchip SoCs.endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong value;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}*valuep = pci_get_ff(size);return 0;+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong old;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;}return 0;+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
struct udevice *ctlr = pci_get_controller(priv->dev);struct pci_controller *hose = dev_get_uclass_priv(ctlr);u64 addr, size, offset;u32 type;int i, region;/* Use region 0 to map PCI configuration space. */writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(0));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));for (i = 0; i < hose->region_count; i++) {if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}}/* Passthrough inbound translations unmodified. */writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));return 0;+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);u32 cr, val, status;int ret;if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 0);ret = reset_assert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->core_rst);if (ret) {dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_assert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_assert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;}udelay(10);ret = reset_deassert(&priv->pm_rst);if (ret) {dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->aclk_rst);if (ret) {dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pclk_rst);if (ret) {dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;}/* Select GEN1 for now */cr = PCIE_CLIENT_GEN_SEL_1;/* Set Root complex mode */cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);ret = reset_deassert(&priv->mgmt_sticky_rst);if (ret) {dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;}ret = reset_deassert(&priv->core_rst);if (ret) {dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->mgmt_rst);if (ret) {dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;}ret = reset_deassert(&priv->pipe_rst);if (ret) {dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;}/* Enable Gen1 training */writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,priv->apb_base + PCIE_CLIENT_CONFIG);if (dm_gpio_is_valid(&priv->ep_gpio))dm_gpio_set_value(&priv->ep_gpio, 1);ret = readl_poll_sleep_timeout(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);if (ret) {dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;}/* Initialize Root Complex registers. */writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);writel(PCI_CLASS_BRIDGE_PCI << 16,priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,priv->apb_base + PCIE_LM_RCBAR);if (dev_read_bool(dev, "aspm-no-l0s")) {val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);}/* Configure Address Translation. */ret = rockchip_pcie_atr_init(priv);if (ret) {dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;}return 0;+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
struct rockchip_pcie *priv = dev_get_priv(dev);int ret;if (!IS_ERR(priv->vpcie3v3)) {I think this should be:
if (priv->vpcie3v3) {I didn't find any issue with the board I have optional of this, but will check it.
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}}And to make this regulator optional, it needs an
if (priv->vpcie1v8) {I can see from v5.7-rc1, 12v, 3v3 are optional and rest not If I'm not wrong.
The devicetree binding is clear about it. See Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt.
And rk3399-firefly.dts doesn't add the properties.
But, at least I can see these two are supplied from SoC Page 12 [1]?
[1] http://download.t-firefly.com/product/RK3399/Docs/Hardware/Schematic%20&...
On 2020-04-25 8:36 pm, Jagan Teki wrote:
On Sun, Apr 26, 2020 at 12:23 AM Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Jagan Teki jagan@amarulasolutions.com Date: Sat, 25 Apr 2020 16:33:51 +0530
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Tried to get this to work on my firefly-rk3399 which made me notice some shortcomings:
- The vpcie1v8 and vpcie0v9 supplies are optional, just like the vpcie3v3 supply.
FWIW those are "non-optional" in Linux in the sense that supplies to the PCIE_AVDD_0V9 and PCIE_AVDD_1V8 pins of the SoC must physically exist, even if they aren't described. If U-Boot doesn't have the same "create a dummy regulator if none is specified" behaviour then you might need some slightly different logic there.
The 3.3V and 12V supplies on the other hand may legitimately not be part of the board at all, depending on whether it implements a full-size slot, a mini-PCI/M.2 socket, a hard-wired endpoint chip, or just the data and clock signal pairs exposed on some non-standard connector.
Robin.
On 2020/4/25 19:03, Jagan Teki wrote:
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Thanks for your patches!
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
- bool "Enable Rockchip PCIe driver"
- select DM_PCI
- default y if ROCKCHIP_RK3399
- help
Say Y here if you want to enable PCIe controller support onRockchip SoCs.- endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong value;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- *valuep = pci_get_ff(size);
PCIe cfg accessors, for instance, rockchip_pcie_rd_config，is supposed to configure TLP type to PCIE_ATR_HDR_CFG_TYPE1 if scanning the downstream buses, as it possiblely is a pcie-switch which should need forward the type1 header packets.
Linux driver is a good example for reference: https://elixir.bootlin.com/linux/latest/source/drivers/pci/controller/pcie-r...
- return 0;
+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong old;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;- }
- return 0;
+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
- struct udevice *ctlr = pci_get_controller(priv->dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- u64 addr, size, offset;
- u32 type;
- int i, region;
- /* Use region 0 to map PCI configuration space. */
- writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
- writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
- writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
priv->apb_base + PCIE_ATR_OB_DESC0(0));- writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
- for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}- }
- /* Passthrough inbound translations unmodified. */
- writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
- writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
- return 0;
+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- u32 cr, val, status;
- int ret;
- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 0);- ret = reset_assert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_assert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;- }
- udelay(10);
- ret = reset_deassert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;- }
- /* Select GEN1 for now */
- cr = PCIE_CLIENT_GEN_SEL_1;
- /* Set Root complex mode */
- cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
- writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = reset_deassert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_deassert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;- }
- /* Enable Gen1 training */
- writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
priv->apb_base + PCIE_CLIENT_CONFIG);- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 1);- ret = readl_poll_sleep_timeout
(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);- if (ret) {
dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;- }
- /* Initialize Root Complex registers. */
- writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
- writel(PCI_CLASS_BRIDGE_PCI << 16,
priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);- writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
priv->apb_base + PCIE_LM_RCBAR);- if (dev_read_bool(dev, "aspm-no-l0s")) {
val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);- }
- /* Configure Address Translation. */
- ret = rockchip_pcie_atr_init(priv);
- if (ret) {
dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;- }
- return 0;
+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- if (!IS_ERR(priv->vpcie3v3)) {
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}- }
- ret = regulator_set_enable(priv->vpcie1v8, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);goto err_disable_3v3;- }
- ret = regulator_set_enable(priv->vpcie0v9, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);goto err_disable_1v8;- }
- return 0;
+err_disable_1v8:
- regulator_set_enable(priv->vpcie1v8, false);
+err_disable_3v3:
- if (!IS_ERR(priv->vpcie3v3))
regulator_set_enable(priv->vpcie3v3, false);- return ret;
+}
+static int rockchip_pcie_parse_dt(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- priv->axi_base = dev_read_addr_name(dev, "axi-base");
- if (!priv->axi_base)
return -ENODEV;- priv->apb_base = dev_read_addr_name(dev, "apb-base");
- if (!priv->axi_base)
return -ENODEV;- ret = gpio_request_by_name(dev, "ep-gpios", 0,
&priv->ep_gpio, GPIOD_IS_OUT);- if (ret) {
dev_err(dev, "failed to find ep-gpios property\n");return ret;- }
- ret = reset_get_by_name(dev, "core", &priv->core_rst);
- if (ret) {
dev_err(dev, "failed to get core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
&priv->vpcie3v3);- if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
&priv->vpcie1v8);- if (ret) {
dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
&priv->vpcie0v9);- if (ret) {
dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);return ret;- }
- return 0;
+}
+static int rockchip_pcie_probe(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- struct udevice *ctlr = pci_get_controller(dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- int ret;
- priv->first_busno = dev->seq;
- priv->dev = dev;
- ret = rockchip_pcie_parse_dt(dev);
- if (ret)
return ret;- ret = rockchip_pcie_set_vpcie(dev);
- if (ret)
return ret;- ret = rockchip_pcie_init_port(dev);
- if (ret)
return ret;- dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
dev->seq, hose->first_busno);- return 0;
+}
+static const struct dm_pci_ops rockchip_pcie_ops = {
- .read_config = rockchip_pcie_rd_conf,
- .write_config = rockchip_pcie_wr_conf,
+};
+static const struct udevice_id rockchip_pcie_ids[] = {
- { .compatible = "rockchip,rk3399-pcie" },
- { }
+};
+U_BOOT_DRIVER(rockchip_pcie) = {
- .name = "rockchip_pcie",
- .id = UCLASS_PCI,
- .of_match = rockchip_pcie_ids,
- .ops = &rockchip_pcie_ops,
- .probe = rockchip_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
+}; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h new file mode 100644 index 0000000000..6ded5c9553 --- /dev/null +++ b/drivers/pci/pcie_rockchip.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Rockchip PCIe Headers
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- */
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_BASIC_STATUS1 0x0048 +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) +#define PCIE_LINK_UP(x) \
- (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000 +#define PCIE_LM_BASE 0x900000 +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) +#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) +#define PCIE_LM_RCBARPIE BIT(19) +#define PCIE_LM_RCBARPIS BIT(20) +#define PCIE_RC_BASE 0xa00000 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) +#define PCIE_ATR_BASE 0xc00000 +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) +#define PCIE_ATR_HDR_MEM 0x2 +#define PCIE_ATR_HDR_IO 0x6 +#define PCIE_ATR_HDR_CFG_TYPE0 0xa +#define PCIE_ATR_HDR_CFG_TYPE1 0xb +#define PCIE_ATR_HDR_RID BIT(23)
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) +#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+struct rockchip_pcie {
- fdt_addr_t axi_base;
- fdt_addr_t apb_base;
- int first_busno;
- struct udevice *dev;
- /* resets */
- struct reset_ctl core_rst;
- struct reset_ctl mgmt_rst;
- struct reset_ctl mgmt_sticky_rst;
- struct reset_ctl pipe_rst;
- struct reset_ctl pm_rst;
- struct reset_ctl pclk_rst;
- struct reset_ctl aclk_rst;
- /* gpio */
- struct gpio_desc ep_gpio;
- /* vpcie regulators */
- struct udevice *vpcie12v;
- struct udevice *vpcie3v3;
- struct udevice *vpcie1v8;
- struct udevice *vpcie0v9;
+};
On Sun, Apr 26, 2020 at 5:21 AM Shawn Lin shawn.lin@rock-chips.com wrote:
On 2020/4/25 19:03, Jagan Teki wrote:
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Thanks for your patches!
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"select DM_PCIdefault y if ROCKCHIP_RK3399helpSay Y here if you want to enable PCIe controller support onRockchip SoCs.- endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong value;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}*valuep = pci_get_ff(size);PCIe cfg accessors, for instance, rockchip_pcie_rd_config，is supposed to configure TLP type to PCIE_ATR_HDR_CFG_TYPE1 if scanning the downstream buses, as it possiblely is a pcie-switch which should need forward the type1 header packets.
Linux driver is a good example for reference: https://elixir.bootlin.com/linux/latest/source/drivers/pci/controller/pcie-r...
Looks like we need to preserve root_bus_nr for this, but this indeed requires to parse the pcie ranges which I'm not sure it would be available in U-Boot. But, I can mark it as TODO if it really requires it in U-Boot.?
Jagan.
On 2020/4/25 下午7:03, Jagan Teki wrote:
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
- bool "Enable Rockchip PCIe driver"
- select DM_PCI
- default y if ROCKCHIP_RK3399
- help
Say Y here if you want to enable PCIe controller support onRockchip SoCs.- endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong value;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;- }
- *valuep = pci_get_ff(size);
- return 0;
+}
+static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
- struct rockchip_pcie *priv = dev_get_priv(bus);
- ulong old;
- u32 off;
- off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |
(PCI_FUNC(bdf) << 12) | (offset & ~0x3);- if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + off);return 0;- }
- if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {
old = readl(priv->axi_base + off);value = pci_conv_size_to_32(old, value, offset, size);writel(value, priv->axi_base + off);return 0;- }
- return 0;
+}
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) +{
- struct udevice *ctlr = pci_get_controller(priv->dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- u64 addr, size, offset;
- u32 type;
- int i, region;
- /* Use region 0 to map PCI configuration space. */
- writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
- writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
- writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
priv->apb_base + PCIE_ATR_OB_DESC0(0));- writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
- for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)continue;if (hose->regions[i].flags == PCI_REGION_IO)type = PCIE_ATR_HDR_IO;elsetype = PCIE_ATR_HDR_MEM;/* Only support identity mappings. */if (hose->regions[i].bus_start !=hose->regions[i].phys_start)return -EINVAL;/* Only support mappings aligned on a region boundary. */addr = hose->regions[i].bus_start;if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))return -EINVAL;/* Mappings should lie between AXI and APB regions. */size = hose->regions[i].size;if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)return -EINVAL;if (addr + size > (u64)priv->apb_base)return -EINVAL;offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);while (size > 0) {writel(32 - 1,priv->apb_base + PCIE_ATR_OB_ADDR0(region));writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));writel(type | PCIE_ATR_HDR_RID,priv->apb_base + PCIE_ATR_OB_DESC0(region));writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));addr += PCIE_ATR_OB_REGION_SIZE;size -= PCIE_ATR_OB_REGION_SIZE;region++;}- }
- /* Passthrough inbound translations unmodified. */
- writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
- writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
- return 0;
+}
+static int rockchip_pcie_init_port(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- u32 cr, val, status;
- int ret;
- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 0);- ret = reset_assert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_assert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_assert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);return ret;- }
- udelay(10);
- ret = reset_deassert(&priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);return ret;- }
- /* Select GEN1 for now */
- cr = PCIE_CLIENT_GEN_SEL_1;
- /* Set Root complex mode */
- cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
- writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = reset_deassert(&priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",ret);return ret;- }
- ret = reset_deassert(&priv->core_rst);
- if (ret) {
dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_deassert(&priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);return ret;- }
- /* Enable Gen1 training */
- writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
priv->apb_base + PCIE_CLIENT_CONFIG);- if (dm_gpio_is_valid(&priv->ep_gpio))
dm_gpio_set_value(&priv->ep_gpio, 1);- ret = readl_poll_sleep_timeout
(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,status, PCIE_LINK_UP(status), 20, 500 * 1000);- if (ret) {
dev_err(dev, "PCIe link training gen1 timeout!\n");return ret;- }
- /* Initialize Root Complex registers. */
- writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
- writel(PCI_CLASS_BRIDGE_PCI << 16,
priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);- writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
priv->apb_base + PCIE_LM_RCBAR);- if (dev_read_bool(dev, "aspm-no-l0s")) {
val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);- }
- /* Configure Address Translation. */
- ret = rockchip_pcie_atr_init(priv);
- if (ret) {
dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);return ret;- }
- return 0;
+}
+static int rockchip_pcie_set_vpcie(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- if (!IS_ERR(priv->vpcie3v3)) {
ret = regulator_set_enable(priv->vpcie3v3, true);if (ret) {dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",ret);return ret;}- }
- ret = regulator_set_enable(priv->vpcie1v8, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);goto err_disable_3v3;- }
- ret = regulator_set_enable(priv->vpcie0v9, true);
- if (ret) {
dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);goto err_disable_1v8;- }
- return 0;
+err_disable_1v8:
- regulator_set_enable(priv->vpcie1v8, false);
+err_disable_3v3:
- if (!IS_ERR(priv->vpcie3v3))
regulator_set_enable(priv->vpcie3v3, false);- return ret;
+}
+static int rockchip_pcie_parse_dt(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- int ret;
- priv->axi_base = dev_read_addr_name(dev, "axi-base");
- if (!priv->axi_base)
return -ENODEV;- priv->apb_base = dev_read_addr_name(dev, "apb-base");
- if (!priv->axi_base)
return -ENODEV;- ret = gpio_request_by_name(dev, "ep-gpios", 0,
&priv->ep_gpio, GPIOD_IS_OUT);- if (ret) {
dev_err(dev, "failed to find ep-gpios property\n");return ret;- }
- ret = reset_get_by_name(dev, "core", &priv->core_rst);
- if (ret) {
dev_err(dev, "failed to get core reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
- if (ret) {
dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
- if (ret) {
dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
- if (ret) {
dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
- if (ret) {
dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);return ret;- }
- ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
- if (ret) {
dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
&priv->vpcie3v3);- if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
&priv->vpcie1v8);- if (ret) {
dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);return ret;- }
- ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
&priv->vpcie0v9);- if (ret) {
dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);return ret;- }
- return 0;
+}
+static int rockchip_pcie_probe(struct udevice *dev) +{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- struct udevice *ctlr = pci_get_controller(dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- int ret;
- priv->first_busno = dev->seq;
- priv->dev = dev;
- ret = rockchip_pcie_parse_dt(dev);
- if (ret)
return ret;- ret = rockchip_pcie_set_vpcie(dev);
- if (ret)
return ret;- ret = rockchip_pcie_init_port(dev);
- if (ret)
return ret;- dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
dev->seq, hose->first_busno);- return 0;
+}
+static const struct dm_pci_ops rockchip_pcie_ops = {
- .read_config = rockchip_pcie_rd_conf,
- .write_config = rockchip_pcie_wr_conf,
+};
+static const struct udevice_id rockchip_pcie_ids[] = {
- { .compatible = "rockchip,rk3399-pcie" },
- { }
+};
+U_BOOT_DRIVER(rockchip_pcie) = {
- .name = "rockchip_pcie",
- .id = UCLASS_PCI,
- .of_match = rockchip_pcie_ids,
- .ops = &rockchip_pcie_ops,
- .probe = rockchip_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
+}; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h new file mode 100644 index 0000000000..6ded5c9553 --- /dev/null +++ b/drivers/pci/pcie_rockchip.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Rockchip PCIe Headers
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- */
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_BASIC_STATUS1 0x0048 +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) +#define PCIE_LINK_UP(x) \
- (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000 +#define PCIE_LM_BASE 0x900000 +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) +#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) +#define PCIE_LM_RCBARPIE BIT(19) +#define PCIE_LM_RCBARPIS BIT(20) +#define PCIE_RC_BASE 0xa00000 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) +#define PCIE_ATR_BASE 0xc00000 +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) +#define PCIE_ATR_HDR_MEM 0x2 +#define PCIE_ATR_HDR_IO 0x6 +#define PCIE_ATR_HDR_CFG_TYPE0 0xa +#define PCIE_ATR_HDR_CFG_TYPE1 0xb +#define PCIE_ATR_HDR_RID BIT(23)
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) +#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+struct rockchip_pcie {
- fdt_addr_t axi_base;
- fdt_addr_t apb_base;
- int first_busno;
- struct udevice *dev;
- /* resets */
- struct reset_ctl core_rst;
- struct reset_ctl mgmt_rst;
- struct reset_ctl mgmt_sticky_rst;
- struct reset_ctl pipe_rst;
- struct reset_ctl pm_rst;
- struct reset_ctl pclk_rst;
- struct reset_ctl aclk_rst;
- /* gpio */
- struct gpio_desc ep_gpio;
- /* vpcie regulators */
- struct udevice *vpcie12v;
- struct udevice *vpcie3v3;
- struct udevice *vpcie1v8;
- struct udevice *vpcie0v9;
+};
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass.
Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON.
Example:
grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>;
pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; };
Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/pci/Makefile | 2 +- drivers/pci/pcie_rockchip.c | 50 ++++++-- drivers/pci/pcie_rockchip.h | 63 ++++++++++ drivers/pci/pcie_rockchip_phy.c | 205 ++++++++++++++++++++++++++++++++ 4 files changed, 306 insertions(+), 14 deletions(-) create mode 100644 drivers/pci/pcie_rockchip_phy.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 493e9354dd..955351c5c2 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index adc64aedf5..00cf036ed8 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -152,6 +152,8 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) static int rockchip_pcie_init_port(struct udevice *dev) { struct rockchip_pcie *priv = dev_get_priv(dev); + struct rockchip_pcie_phy *phy = pcie_get_phy(priv); + struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy); u32 cr, val, status; int ret;
@@ -176,29 +178,35 @@ static int rockchip_pcie_init_port(struct udevice *dev) return ret; }
+ ret = ops->init(phy); + if (ret) { + dev_err(dev, "failed to init phy (ret=%d)\n", ret); + goto err_exit_phy; + } + ret = reset_assert(&priv->core_rst); if (ret) { dev_err(dev, "failed to assert core reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
ret = reset_assert(&priv->mgmt_rst); if (ret) { dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
ret = reset_assert(&priv->mgmt_sticky_rst); if (ret) { dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
ret = reset_assert(&priv->pipe_rst); if (ret) { dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
udelay(10); @@ -206,19 +214,19 @@ static int rockchip_pcie_init_port(struct udevice *dev) ret = reset_deassert(&priv->pm_rst); if (ret) { dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
ret = reset_deassert(&priv->aclk_rst); if (ret) { dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
ret = reset_deassert(&priv->pclk_rst); if (ret) { dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; }
/* Select GEN1 for now */ @@ -227,29 +235,35 @@ static int rockchip_pcie_init_port(struct udevice *dev) cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
+ ret = ops->power_on(phy); + if (ret) { + dev_err(dev, "failed to power on phy (ret=%d)\n", ret); + goto err_power_off_phy; + } + ret = reset_deassert(&priv->mgmt_sticky_rst); if (ret) { dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; }
ret = reset_deassert(&priv->core_rst); if (ret) { dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; }
ret = reset_deassert(&priv->mgmt_rst); if (ret) { dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; }
ret = reset_deassert(&priv->pipe_rst); if (ret) { dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; }
/* Enable Gen1 training */ @@ -264,7 +278,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) status, PCIE_LINK_UP(status), 20, 500 * 1000); if (ret) { dev_err(dev, "PCIe link training gen1 timeout!\n"); - return ret; + goto err_power_off_phy; }
/* Initialize Root Complex registers. */ @@ -284,10 +298,16 @@ static int rockchip_pcie_init_port(struct udevice *dev) ret = rockchip_pcie_atr_init(priv); if (ret) { dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq); - return ret; + goto err_power_off_phy; }
return 0; + +err_power_off_phy: + ops->power_off(phy); +err_exit_phy: + ops->exit(phy); + return ret; }
static int rockchip_pcie_set_vpcie(struct udevice *dev) @@ -426,6 +446,10 @@ static int rockchip_pcie_probe(struct udevice *dev) if (ret) return ret;
+ ret = rockchip_pcie_phy_get(dev); + if (ret) + return ret; + ret = rockchip_pcie_set_vpcie(dev); if (ret) return ret; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h index 6ded5c9553..c3a0a2846d 100644 --- a/drivers/pci/pcie_rockchip.h +++ b/drivers/pci/pcie_rockchip.h @@ -53,11 +53,61 @@ #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+/* + * The higher 16-bit of this register is used for write protection + * only if BIT(x + 16) set to 1 the BIT(x) can be written. + */ +#define HIWORD_UPDATE_MASK(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define PHY_CFG_DATA_SHIFT 7 +#define PHY_CFG_ADDR_SHIFT 1 +#define PHY_CFG_DATA_MASK 0xf +#define PHY_CFG_ADDR_MASK 0x3f +#define PHY_CFG_RD_MASK 0x3ff +#define PHY_CFG_WR_ENABLE 1 +#define PHY_CFG_WR_DISABLE 1 +#define PHY_CFG_WR_SHIFT 0 +#define PHY_CFG_WR_MASK 1 +#define PHY_CFG_PLL_LOCK 0x10 +#define PHY_CFG_CLK_TEST 0x10 +#define PHY_CFG_CLK_SCC 0x12 +#define PHY_CFG_SEPE_RATE BIT(3) +#define PHY_CFG_PLL_100M BIT(3) +#define PHY_PLL_LOCKED BIT(9) +#define PHY_PLL_OUTPUT BIT(10) +#define PHY_LANE_IDLE_OFF 0x1 +#define PHY_LANE_IDLE_MASK 0x1 +#define PHY_LANE_IDLE_A_SHIFT 3 +#define PHY_LANE_IDLE_B_SHIFT 4 +#define PHY_LANE_IDLE_C_SHIFT 5 +#define PHY_LANE_IDLE_D_SHIFT 6 + +#define PCIE_PHY_CONF 0xe220 +#define PCIE_PHY_STATUS 0xe2a4 +#define PCIE_PHY_LANEOFF 0xe214 + +struct rockchip_pcie_phy { + void *reg_base; + struct clk refclk; + struct reset_ctl phy_rst; + struct rockchip_pcie_phy_ops *ops; +}; + +struct rockchip_pcie_phy_ops { + int (*init)(struct rockchip_pcie_phy *phy); + int (*exit)(struct rockchip_pcie_phy *phy); + int (*power_on)(struct rockchip_pcie_phy *phy); + int (*power_off)(struct rockchip_pcie_phy *phy); +}; + struct rockchip_pcie { fdt_addr_t axi_base; fdt_addr_t apb_base; int first_busno; struct udevice *dev; + struct rockchip_pcie_phy rk_phy; + struct rockchip_pcie_phy *phy;
/* resets */ struct reset_ctl core_rst; @@ -77,3 +127,16 @@ struct rockchip_pcie { struct udevice *vpcie1v8; struct udevice *vpcie0v9; }; + +int rockchip_pcie_phy_get(struct udevice *dev); + +inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie) +{ + return pcie->phy; +} + +inline +struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy) +{ + return (struct rockchip_pcie_phy_ops *)phy->ops; +} diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c new file mode 100644 index 0000000000..47f5d6c7e3 --- /dev/null +++ b/drivers/pci/pcie_rockchip_phy.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip PCIe PHY driver + * + * Copyright (c) 2016 Rockchip, Inc. + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <reset.h> +#include <syscon.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/iopoll.h> +#include <asm/arch-rockchip/clock.h> + +#include "pcie_rockchip.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data) +{ + u32 reg; + + reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT); + reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + udelay(1); + + reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + udelay(1); + + reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); +} + +static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy) +{ + int ret = 0; + u32 reg, status; + + ret = reset_deassert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll lock timeout!\n"); + goto err_pll_lock; + } + + phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); + phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); + + ret = -ETIMEDOUT; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + !(status & PHY_PLL_OUTPUT), + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll output enable timeout!\n"); + goto err_pll_lock; + } + + reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll relock timeout!\n"); + goto err_pll_lock; + } + + return 0; + +err_pll_lock: + reset_assert(&phy->phy_rst); + return ret; +} + +static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy) +{ + int ret; + u32 reg; + + reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); + + ret = reset_assert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + return 0; +} + +static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy) +{ + int ret; + + ret = clk_enable(&phy->refclk); + if (ret) { + dev_err(dev, "failed to enable refclk clock\n"); + return ret; + } + + ret = reset_assert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + goto err_reset; + } + + return 0; + +err_reset: + clk_disable(&phy->refclk); + return ret; +} + +static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy) +{ + clk_disable(&phy->refclk); + + return 0; +} + +static struct rockchip_pcie_phy_ops pcie_phy_ops = { + .init = rockchip_pcie_phy_init, + .power_on = rockchip_pcie_phy_power_on, + .power_off = rockchip_pcie_phy_power_off, + .exit = rockchip_pcie_phy_exit, +}; + +int rockchip_pcie_phy_get(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + struct rockchip_pcie_phy *phy_priv = &priv->rk_phy; + ofnode phy_node; + u32 phandle; + int ret; + + phandle = dev_read_u32_default(dev, "phys", 0); + phy_node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(phy_node)) { + dev_err(dev, "failed to found pcie-phy\n"); + return -ENODEV; + } + + phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk); + if (ret) { + dev_err(dev, "failed to get refclk clock phandle\n"); + return ret; + } + + ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst); + if (ret) { + dev_err(dev, "failed to get phy reset phandle\n"); + return ret; + } + + phy_priv->ops = &pcie_phy_ops; + priv->phy = phy_priv; + + return 0; +}
Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards.
=> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x0100 Bridge device 0x04 => nvme scan => nvme dev
IDE device 0: Vendor: 0x144d Rev: 4L1QCXB7 Prod: S35FNX0J623292 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/rk3399-u-boot.dtsi | 1 + configs/nanopc-t4-rk3399_defconfig | 4 ++++ configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++++ 3 files changed, 9 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index ef57c36e73..a79a2d23d8 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -8,6 +8,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; + pci0 = &pcie0; };
cic: syscon@ff620000 { diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 607a00dbf7..032256fd76 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -34,10 +35,13 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 5a694edc03..0b853805f3 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y
Due to some on board limitation rock960 PCIe works only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work.
rock960 => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x0100 Bridge device 0x04 rock960 => nvme scan rock960 => nvme dev
IDE device 0: Vendor: 0x144d Rev: 4L1QCXB7 Prod: S35FNX0J623292 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Cc: Tom Cubie tom@radxa.com Cc: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ configs/rock960-rk3399_defconfig | 5 +++++ 2 files changed, 25 insertions(+)
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac..98d62e89ca 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,23 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org */ + +#include <common.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c4e954731a..cb1ec3c26b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y
participants (5)
-
Jagan Teki -
Kever Yang -
Mark Kettenis -
Robin Murphy -
Shawn Lin