[U-Boot] How to reduce SDcard speed in u-boot
Hello, I am probably working on a 'buggy hardware' based on i.MX6 that isn't able to manage a SDcard speed properly. I mean, u-boot starts, but as soon as I try to perform a fatload if the uImage the command won't work properly. I had the possibility to test the SoM on another carrier with a different layout and a different microSD connector and it works at every boot. The quick and dirty hack I found is to modify sd_switch() in drivers/mmc/mmc.c in this way
/* * Reduce SD/MMC speed * u-boot> mmc info * before : Tran Speed: 50000000 * after : Tran Speed: 25000000 */ printf("*** Skip support SD_HIGHSPEED in sd_change_freq\n") ; return 0;
just before
/* If high-speed isn't supported, we return */ if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0;
the problem is that on 80% of the carrier boards the problem is still present. My questions are: 1. is this hack the best solution in this case or can you suggest me another better way to proceed? 2. would be possible to reduce the speed more than this and how?
thank you in advance -- Marco
2015-03-30 17:32 GMT+02:00 Marco Cavallini cavallini.koan@gmail.com:
Hello, I am probably working on a 'buggy hardware' based on i.MX6 that isn't able to manage a SDcard speed properly. I mean, u-boot starts, but as soon as I try to perform a fatload if the uImage the command won't work properly. I had the possibility to test the SoM on another carrier with a different layout and a different microSD connector and it works at every boot. The quick and dirty hack I found is to modify sd_switch() in drivers/mmc/mmc.c in this way
/*
- Reduce SD/MMC speed
- u-boot> mmc info
- before : Tran Speed: 50000000
- after : Tran Speed: 25000000
*/ printf("*** Skip support SD_HIGHSPEED in sd_change_freq\n") ; return 0;
just before
/* If high-speed isn't supported, we return */ if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0;the problem is that on 80% of the carrier boards the problem is still present. My questions are:
- is this hack the best solution in this case or can you suggest me
another better way to proceed? 2. would be possible to reduce the speed more than this and how?
thank you in advance
Marco
Hello, sorry for bothering you. Any advice from the u-boot experts would give me a great help. Thank you
Hi
On Fri, Apr 3, 2015 at 9:50 PM, Marco Cavallini cavallini.koan@gmail.com wrote:
2015-03-30 17:32 GMT+02:00 Marco Cavallini cavallini.koan@gmail.com:
Hello, I am probably working on a 'buggy hardware' based on i.MX6 that isn't able to manage a SDcard speed properly. I mean, u-boot starts, but as soon as I try to perform a fatload if the uImage the command won't work properly. I had the possibility to test the SoM on another carrier with a different layout and a different microSD connector and it works at every boot. The quick and dirty hack I found is to modify sd_switch() in drivers/mmc/mmc.c in this way
/*
- Reduce SD/MMC speed
- u-boot> mmc info
- before : Tran Speed: 50000000
- after : Tran Speed: 25000000
*/ printf("*** Skip support SD_HIGHSPEED in sd_change_freq\n") ; return 0;
just before
/* If high-speed isn't supported, we return */ if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0;the problem is that on 80% of the carrier boards the problem is still present. My questions are:
- is this hack the best solution in this case or can you suggest me
another better way to proceed? 2. would be possible to reduce the speed more than this and how?
Increase the divisor of the clock
MXC_CCM_CSCDR1_USDHC[X]_PODF_MASK MXC_CCM_CSCDR1_USDHC[X]_PODF_OFFSET
I'm not sure because I have not a board and no time before Easter to open documentation ;)
Michael
thank you in advance
Marco
Hello, sorry for bothering you. Any advice from the u-boot experts would give me a great help. Thank you _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
2015-04-03 16:26 GMT+02:00 Michael Trimarchi michael@amarulasolutions.com:
Hi
Increase the divisor of the clock
MXC_CCM_CSCDR1_USDHC[X]_PODF_MASK MXC_CCM_CSCDR1_USDHC[X]_PODF_OFFSET
I'm not sure because I have not a board and no time before Easter to open documentation ;)
Michael
Hi Michael, the register CCM_CSCDR1 did the trick, thank you. Unfortunately on the buggy hardware I have the same problem (printed below).
=========
On the working board
md.l 020c4024 1
clocks
PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz
IPG 66000 kHz UART 80000 kHz AHB 132000 kHz AXI 198000 kHz DDR 396000 kHz USDHC1 198000 kHz USDHC2 198000 kHz USDHC3 198000 kHz USDHC4 198000 kHz EMI SLOW 99000 kHz IPG PERCLK 66000 kHz
run loadk
reading uImage 5157968 bytes read in 454 ms (10.8 MiB/s)
Increased divisor below:
mw.l 020c4024 00790b00
clocks
PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz
IPG 66000 kHz UART 80000 kHz AHB 132000 kHz AXI 198000 kHz DDR 396000 kHz USDHC1 198000 kHz USDHC2 198000 kHz USDHC3 49500 kHz <------- USDHC4 198000 kHz EMI SLOW 99000 kHz IPG PERCLK 66000 kHz
run loadk
reading uImage 5157968 bytes read in 882 ms (5.6 MiB/s) <--- slower upload into memory
=========
On the buggy board : ERROR
fatload mmc 0:1 0x12000000 uImage
reading uImage Error reading cluster ** Unable to read file uImage **
fatload mmc 0:1 0x12000000 uImage
** Can't read partition table on 0:0 ** ** Invalid partition 1 **
fatload mmc 0:1 0x12000000 uImage
** Can't read partition table on 0:0 ** ** Invalid partition 1 **
Ciao -- Marco
Hi
On Wed, Apr 8, 2015 at 3:22 PM, Marco Cavallini cavallini.koan@gmail.com wrote:
2015-04-03 16:26 GMT+02:00 Michael Trimarchi michael@amarulasolutions.com:
Hi
Increase the divisor of the clock
MXC_CCM_CSCDR1_USDHC[X]_PODF_MASK MXC_CCM_CSCDR1_USDHC[X]_PODF_OFFSET
I'm not sure because I have not a board and no time before Easter to open documentation ;)
Michael
Hi Michael, the register CCM_CSCDR1 did the trick, thank you. Unfortunately on the buggy hardware I have the same problem (printed below).
=========
On the working board
md.l 020c4024 1
clocks
PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz
IPG 66000 kHz UART 80000 kHz AHB 132000 kHz AXI 198000 kHz DDR 396000 kHz USDHC1 198000 kHz USDHC2 198000 kHz USDHC3 198000 kHz USDHC4 198000 kHz EMI SLOW 99000 kHz IPG PERCLK 66000 kHz
run loadk
reading uImage 5157968 bytes read in 454 ms (10.8 MiB/s)
Increased divisor below:
mw.l 020c4024 00790b00
clocks
PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz
IPG 66000 kHz UART 80000 kHz AHB 132000 kHz AXI 198000 kHz DDR 396000 kHz USDHC1 198000 kHz USDHC2 198000 kHz USDHC3 49500 kHz <-------
Try 25Mhz
Michael
USDHC4 198000 kHz EMI SLOW 99000 kHz IPG PERCLK 66000 kHz
run loadk
reading uImage 5157968 bytes read in 882 ms (5.6 MiB/s) <--- slower upload into memory
=========
On the buggy board : ERROR
fatload mmc 0:1 0x12000000 uImage
reading uImage Error reading cluster ** Unable to read file uImage **
fatload mmc 0:1 0x12000000 uImage
** Can't read partition table on 0:0 ** ** Invalid partition 1 **
fatload mmc 0:1 0x12000000 uImage
** Can't read partition table on 0:0 ** ** Invalid partition 1 **
Ciao
Marco _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
participants (2)
-
Marco Cavallini -
Michael Trimarchi