This adds missing hifsys reset parts in header files.

Tested-by: Frank Wunderlich frank-w@public-files.de Signed-off-by: Ryder Lee ryder.lee@mediatek.com --- arch/arm/dts/mt7623.dtsi | 7 +++++++ include/dt-bindings/reset/mtk-reset.h | 9 +++++++++ 2 files changed, 16 insertions(+)

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 448d1d7381..9f9eec8b9c 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -248,6 +248,13 @@ status = "disabled"; };

+ hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>; diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mtk-reset.h index 5f0a74f280..78fcdab009 100644 --- a/include/dt-bindings/reset/mtk-reset.h +++ b/include/dt-bindings/reset/mtk-reset.h @@ -15,4 +15,13 @@ #define ETHSYS_MCM_RST 2 #define ETHSYS_SYS_RST 0

+/* HIFSYS resets */ +#define HIFSYS_PCIE2_RST 26 +#define HIFSYS_PCIE1_RST 25 +#define HIFSYS_PCIE0_RST 24 +#define HIFSYS_UPHY1_RST 22 +#define HIFSYS_UPHY0_RST 21 +#define HIFSYS_UHOST1_RST 4 +#define HIFSYS_UHOST0_RST 3 + #endif /* _DT_BINDINGS_MTK_RESET_H_ */

This adds high speed interface subsystem - hifsys (i.e. PCIe and USB) for MT7623 SoC and enables its reset controller.

The control block is shared with ethsys and accordingly rename the related defines.

Tested-by: Frank Wunderlich frank-w@public-files.de Signed-off-by: Ryder Lee ryder.lee@mediatek.com --- drivers/clk/mediatek/clk-mt7623.c | 68 ++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mt7629.c | 4 +- drivers/clk/mediatek/clk-mtk.h | 2 +- 3 files changed, 51 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 87ad4f79ce..dfce32e283 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -691,34 +691,42 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11), };

-/* ethsys */ -static const struct mtk_gate_regs eth_cg_regs = { +/* ethsys and hifsys */ +static const struct mtk_gate_regs eth_hif_cg_regs = { .sta_ofs = 0x30, };

-#define GATE_ETH(_id, _parent, _shift, _flag) { \ +#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \ .id = _id, \ .parent = _parent, \ - .regs = &eth_cg_regs, \ + .regs = &eth_hif_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ }

-#define GATE_ETH0(_id, _parent, _shift) \ - GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) +#define GATE_ETH_HIF0(_id, _parent, _shift) \ + GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)

-#define GATE_ETH1(_id, _parent, _shift) \ - GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) +#define GATE_ETH_HIF1(_id, _parent, _shift) \ + GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)

static const struct mtk_gate eth_cgs[] = { - GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5), - GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6), - GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7), - GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8), - GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11), - GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14), - GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17), - GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29), + GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5), + GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6), + GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7), + GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8), + GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11), + GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14), + GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17), + GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29), +}; + +static const struct mtk_gate hif_cgs[] = { + GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21), + GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22), + GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24), + GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25), + GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26), };

static const struct mtk_clk_tree mt7623_clk_tree = { @@ -778,19 +786,24 @@ static int mt7623_pericfg_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs); }

+static int mt7623_hifsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs); +} + static int mt7623_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs); }

-static int mt7623_ethsys_bind(struct udevice *dev) +static int mt7623_ethsys_hifsys_bind(struct udevice *dev) { int ret = 0;

#if CONFIG_IS_ENABLED(RESET_MEDIATEK) - ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1); + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); if (ret) - debug("Warning: failed to bind ethsys reset controller\n"); + debug("Warning: failed to bind reset controller\n"); #endif

return ret; @@ -821,6 +834,11 @@ static const struct udevice_id mt7623_ethsys_compat[] = { { } };

+static const struct udevice_id mt7623_hifsys_compat[] = { + { .compatible = "mediatek,mt7623-hifsys" }, + { } +}; + static const struct udevice_id mt7623_mcucfg_compat[] = { { .compatible = "mediatek,mt7623-mcucfg" }, { } @@ -874,12 +892,22 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .flags = DM_FLAG_PRE_RELOC, };

+U_BOOT_DRIVER(mtk_clk_hifsys) = { + .name = "mt7623-clock-hifsys", + .id = UCLASS_CLK, + .of_match = mt7623_hifsys_compat, + .probe = mt7623_hifsys_probe, + .bind = mt7623_ethsys_hifsys_bind, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + U_BOOT_DRIVER(mtk_clk_ethsys) = { .name = "mt7623-clock-ethsys", .id = UCLASS_CLK, .of_match = mt7623_ethsys_compat, .probe = mt7623_ethsys_probe, - .bind = mt7623_ethsys_bind, + .bind = mt7623_ethsys_hifsys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 6a9f60139c..30a919f224 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -608,9 +608,9 @@ static int mt7629_ethsys_bind(struct udevice *dev) int ret = 0;

#if CONFIG_IS_ENABLED(RESET_MEDIATEK) - ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1); + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); if (ret) - debug("Warning: failed to bind ethsys reset controller\n"); + debug("Warning: failed to bind reset controller\n"); #endif

return ret; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 7847388b2a..dce93253ad 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -23,7 +23,7 @@ #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_MASK GENMASK(5, 4)

-#define ETHSYS_RST_CTRL_OFS 0x34 +#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34

/* struct mtk_pll_data - hardware-specific PLLs data */ struct mtk_pll_data {