[PATCH v2 0/4] qcom: pinctrl drivers for qcm2290/sm6115/sm8250
Introduce pinctrl drivers for three new SoCs and enable them.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- Changes in v2: - Fix a few formatting issues - Link to v1: https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8bdf@linaro....
--- Caleb Connolly (4): pinctrl: qcom: add qcm2290 pinctrl driver pinctrl: qcom: add sm6115 pinctrl driver pinctrl: qcom: add sm8250 pinctrl driver qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
configs/qcom_defconfig | 3 + drivers/pinctrl/qcom/Kconfig | 21 ++++ drivers/pinctrl/qcom/Makefile | 3 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 ++++++++++++ drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 +++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 ++++++++++++++++ 6 files changed, 396 insertions(+) --- change-id: 20240408-b4-qcom-rbx-soc-44ee99c8b799 base-commit: 4ba549b0a4e67c563785ab144edf47e108b34822
// Caleb (they/them)
This SoC has a basic pinctrl block with no tiles.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 ++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2fe639814785..35140efd5b62 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -26,8 +26,15 @@ config PINCTRL_QCOM_IPQ4019 help Say Y here to enable support for pinctrl on the IPQ4019 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_QCM2290 + bool "Qualcomm QCM2290 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM help diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6d9aca6d7b7e..0b1d610ea3e8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o +obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c new file mode 100644 index 000000000000..af969e177d73 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm qcm2290 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup4", 1 }, + { "gpio", 0 }, +}; + +static const char *qcm2290_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int selector) +{ + static const char *const special_pins_names[] = { + "sdc1_rclk", "sdc1_clk", "sdc1_cmd", "sdc1_data", + "sdc2_clk", "sdc2_cmd", "sdc2_data", + }; + + if (selector >= 127 && selector <= 133) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 127]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcm2290_data = { + .pin_data = { + .pin_count = 133, + .special_pins_start = 127, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcm2290_get_function_name, + .get_function_mux = qcm2290_get_function_mux, + .get_pin_name = qcm2290_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,qcm2290-tlmm", + .data = (ulong)&qcm2290_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_qcm2290) = { + .name = "pinctrl_qcm2290", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
This SoC features a pinctrl block with west, east, and south tiles.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/pinctrl/qcom/Kconfig | 7 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 ++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 35140efd5b62..e7a9853ce47a 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -47,7 +47,14 @@ config PINCTRL_QCOM_SDM845 help Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM6115 + bool "Qualcomm SM6115 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, + as well as the associated GPIO driver. + endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 0b1d610ea3e8..f00c4e6e10cc 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c new file mode 100644 index 000000000000..f07f39f4ac30 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm6115 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00000000 +#define SOUTH 0x00400000 +#define EAST 0x00800000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup4", 1 }, + { "gpio", 0 }, +}; + +static const unsigned int sm6115_pin_offsets[] = { + [0] = WEST, + [1] = WEST, + [2] = WEST, + [3] = WEST, + [4] = WEST, + [5] = WEST, + [6] = WEST, + [7] = WEST, + [8] = EAST, + [9] = EAST, + [10] = EAST, + [11] = EAST, + [12] = WEST, + [13] = WEST, + [14] = WEST, + [15] = WEST, + [16] = WEST, + [17] = WEST, + [18] = EAST, + [19] = EAST, + [20] = EAST, + [21] = EAST, + [22] = EAST, + [23] = EAST, + [24] = EAST, + [25] = EAST, + [26] = EAST, + [27] = EAST, + [28] = EAST, + [29] = EAST, + [30] = EAST, + [31] = EAST, + [32] = EAST, + [33] = EAST, + [34] = EAST, + [35] = EAST, + [36] = EAST, + [37] = EAST, + [38] = EAST, + [39] = EAST, + [40] = EAST, + [41] = EAST, + [42] = EAST, + [43] = EAST, + [44] = EAST, + [45] = EAST, + [46] = EAST, + [47] = EAST, + [48] = EAST, + [49] = EAST, + [50] = EAST, + [51] = EAST, + [52] = EAST, + [53] = EAST, + [54] = EAST, + [55] = EAST, + [56] = EAST, + [57] = EAST, + [58] = EAST, + [59] = EAST, + [60] = EAST, + [61] = EAST, + [62] = EAST, + [63] = EAST, + [64] = EAST, + [65] = WEST, + [66] = WEST, + [67] = WEST, + [68] = WEST, + [69] = WEST, + [70] = WEST, + [71] = WEST, + [72] = SOUTH, + [73] = SOUTH, + [74] = SOUTH, + [75] = SOUTH, + [76] = SOUTH, + [77] = SOUTH, + [78] = SOUTH, + [79] = SOUTH, + [80] = WEST, + [81] = WEST, + [82] = WEST, + [83] = WEST, + [84] = WEST, + [85] = WEST, + [86] = WEST, + [87] = EAST, + [88] = EAST, + [89] = WEST, + [90] = EAST, + [91] = EAST, + [92] = WEST, + [93] = WEST, + [94] = WEST, + [95] = WEST, + [96] = WEST, + [97] = WEST, + [98] = SOUTH, + [99] = SOUTH, + [100] = SOUTH, + [101] = SOUTH, + [102] = SOUTH, + [103] = SOUTH, + [104] = SOUTH, + [105] = SOUTH, + [106] = SOUTH, + [107] = SOUTH, + [108] = SOUTH, + [109] = SOUTH, + [110] = SOUTH, + [111] = SOUTH, + [112] = SOUTH, + /* Special pins */ + [113] = 0, + [114] = 0, + [115] = 0, + [116] = 0, + [117] = 0, + [118] = 0, + [119] = 0, + [120] = 0, +}; + +static const char *sm6115_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm6115_get_pin_name(struct udevice *dev, unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", "sdc1_rclk", "sdc1_clk", "sdc1_cmd", + "sdc1_data", "sdc2_clk", "sdc2_cmd", "sdc2_data", + }; + + if (selector >= 113 && selector <= 120) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 113]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data sm6115_data = { + .pin_data = { + .pin_offsets = sm6115_pin_offsets, + .pin_count = ARRAY_SIZE(sm6115_pin_offsets), + .special_pins_start = 113, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm6115_get_function_name, + .get_function_mux = sm6115_get_function_mux, + .get_pin_name = sm6115_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,sm6115-tlmm", + .data = (ulong)&sm6115_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_sm6115) = { + .name = "pinctrl_sm6115", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
This SoC features a pinctrl block with north, south, and west tiles accessible to the AP.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/pinctrl/qcom/Kconfig | 7 +++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 +++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index e7a9853ce47a..33c355ad3b24 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -54,7 +54,14 @@ config PINCTRL_QCOM_SM6115 help Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8250 + bool "Qualcomm SM8250 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC, + as well as the associated GPIO driver. + endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index f00c4e6e10cc..7dce95e5acb2 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o \ No newline at end of file diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 000000000000..dac24f11bc2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8250 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00000000 +#define SOUTH 0x00400000 +#define NORTH 0x00800000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup12", 1 }, + { "gpio", 0 }, + { "sdc2_clk", 0 } }; + +static const unsigned int sm8250_pin_offsets[] = { + [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = NORTH, [5] = NORTH, + [6] = NORTH, [7] = NORTH, [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH, + [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, [16] = NORTH, [17] = NORTH, + [18] = NORTH, [19] = NORTH, [20] = NORTH, [21] = NORTH, [22] = NORTH, [23] = NORTH, + [24] = SOUTH, [25] = SOUTH, [26] = SOUTH, [27] = SOUTH, [28] = NORTH, [29] = NORTH, + [30] = NORTH, [31] = NORTH, [32] = SOUTH, [33] = SOUTH, [34] = SOUTH, [35] = SOUTH, + [36] = SOUTH, [37] = SOUTH, [38] = SOUTH, [39] = SOUTH, [40] = SOUTH, [41] = SOUTH, + [42] = SOUTH, [43] = SOUTH, [44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH, + [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, [52] = SOUTH, [53] = SOUTH, + [54] = SOUTH, [55] = SOUTH, [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, [64] = SOUTH, [65] = SOUTH, + [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, [76] = SOUTH, [77] = NORTH, + [78] = NORTH, [79] = NORTH, [80] = NORTH, [81] = NORTH, [82] = NORTH, [83] = NORTH, + [84] = NORTH, [85] = SOUTH, [86] = SOUTH, [87] = SOUTH, [88] = SOUTH, [89] = SOUTH, + [90] = SOUTH, [91] = SOUTH, [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH, + [96] = NORTH, [97] = NORTH, [98] = NORTH, [99] = NORTH, [100] = NORTH, [101] = NORTH, + [102] = NORTH, [103] = NORTH, [104] = NORTH, [105] = NORTH, [106] = NORTH, [107] = NORTH, + [108] = NORTH, [109] = NORTH, [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, + [114] = NORTH, [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH, + [120] = NORTH, [121] = NORTH, [122] = NORTH, [123] = NORTH, [124] = NORTH, [125] = SOUTH, + [126] = SOUTH, [127] = SOUTH, [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, [133] = WEST, [134] = WEST, [135] = WEST, [136] = WEST, [137] = WEST, + [138] = WEST, [139] = WEST, [140] = WEST, [141] = WEST, [142] = WEST, [143] = WEST, + [144] = WEST, [145] = WEST, [146] = WEST, [147] = WEST, [148] = WEST, [149] = WEST, + [150] = WEST, [151] = WEST, [152] = WEST, [153] = WEST, [154] = WEST, [155] = WEST, + [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST, [160] = WEST, [161] = WEST, + [162] = WEST, [163] = WEST, [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, + [168] = WEST, [169] = WEST, [170] = WEST, [171] = WEST, [172] = WEST, [173] = WEST, + [174] = WEST, [175] = WEST, [176] = WEST, [177] = WEST, [178] = WEST, [179] = WEST, + [180] = 0, [181] = 0, [182] = 0, [183] = 0, +}; + +static const char *sm8250_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +} + +static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8250_data = { + .pin_data = { + .pin_offsets = sm8250_pin_offsets, + .pin_count = ARRAY_SIZE(sm8250_pin_offsets), + .special_pins_start = 180, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8250_get_function_name, + .get_function_mux = sm8250_get_function_mux, + .get_pin_name = sm8250_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,sm8250-pinctrl", + .data = (ulong)&sm8250_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_sm8250) = { + .name = "pinctrl_sm8250", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
Enable the clock and pinctrl drivers for qcm2290, sm6115, and sm8250.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- configs/qcom_defconfig | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index a0921ad55519..5e08ea392386 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -66,10 +66,13 @@ CONFIG_RGMII=y CONFIG_PHY=y CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PINCTRL=y +CONFIG_PINCTRL_QCOM_QCM2290=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_PINCTRL_QCOM_SM6115=y +CONFIG_PINCTRL_QCOM_SM8250=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y
On 10/04/2024 19:52, Caleb Connolly wrote:
Introduce pinctrl drivers for three new SoCs and enable them.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
Changes in v2:
- Fix a few formatting issues
- Link to v1: https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8bdf@linaro....
Caleb Connolly (4): pinctrl: qcom: add qcm2290 pinctrl driver pinctrl: qcom: add sm6115 pinctrl driver pinctrl: qcom: add sm8250 pinctrl driver qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
configs/qcom_defconfig | 3 + drivers/pinctrl/qcom/Kconfig | 21 ++++ drivers/pinctrl/qcom/Makefile | 3 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 ++++++++++++ drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 +++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 ++++++++++++++++ 6 files changed, 396 insertions(+)
change-id: 20240408-b4-qcom-rbx-soc-44ee99c8b799 base-commit: 4ba549b0a4e67c563785ab144edf47e108b34822
// Caleb (they/them)
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org
On Wed, 10 Apr 2024 at 23:23, Caleb Connolly caleb.connolly@linaro.org wrote:
Introduce pinctrl drivers for three new SoCs and enable them.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
Changes in v2:
- Fix a few formatting issues
- Link to v1: https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8bdf@linaro....
Caleb Connolly (4): pinctrl: qcom: add qcm2290 pinctrl driver pinctrl: qcom: add sm6115 pinctrl driver pinctrl: qcom: add sm8250 pinctrl driver qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
configs/qcom_defconfig | 3 + drivers/pinctrl/qcom/Kconfig | 21 ++++ drivers/pinctrl/qcom/Makefile | 3 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 ++++++++++++ drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 +++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 ++++++++++++++++ 6 files changed, 396 insertions(+)
change-id: 20240408-b4-qcom-rbx-soc-44ee99c8b799 base-commit: 4ba549b0a4e67c563785ab144edf47e108b34822
// Caleb (they/them)
participants (3)
-
Caleb Connolly -
Neil Armstrong -
Sumit Garg