[PATCH v2 0/4] Unify K3 initial memory map
Hello all,
This was an RFC as it might still break remoteproc loading, but posted now for merge as worst case this would expose the issue in remoteproc loading better and force someone to go fix it. :)
Changes for v2: - Add patch adding firewall MMU hole for Jacinto devices
Changes for non-RFC: - Included dependency patch from here[0] into this series - Add Tested-bys - Rebase on latest -next
Thanks, Andrew
[0] https://lore.kernel.org/all/20231122211218.607757-1-afd@ti.com/
Andrew Davis (4): arm: mach-k3: Let the compiler size the mem_map lists arm: mach-k3: Do not map ATF and OPTEE regions in MMU arm: mach-k3: Remove non-cached memory map areas arm: mach-k3: Merge initial memory maps
arch/arm/mach-k3/arm64-mmu.c | 271 +---------------------------------- 1 file changed, 3 insertions(+), 268 deletions(-)
NR_MMU_REGIONS is a copy/paste from another platform that extends this list later. We do not do that, so let the list be the size of the initializer list.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index e8db5332ae0..d872ed714c4 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -13,11 +13,7 @@ #include <asm/armv8/mmu.h>
#ifdef CONFIG_SOC_K3_AM654 -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region am654_mem_map[NR_MMU_REGIONS] = { +struct mm_region am654_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -68,10 +64,7 @@ struct mm_region *mem_map = am654_mem_map; #ifdef CONFIG_SOC_K3_J721E
#ifdef CONFIG_SOC_K3_J721E_J7200 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { +struct mm_region j7200_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -119,12 +112,7 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { struct mm_region *mem_map = j7200_mem_map;
#else /* CONFIG_SOC_K3_J721E_J7200 */ - -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) - -/* ToDo: Add 64bit IO */ -struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721e_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -181,10 +169,7 @@ struct mm_region *mem_map = j721e_mem_map; #endif /* CONFIG_SOC_K3_J721E */
#ifdef CONFIG_SOC_K3_J721S2 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) - -/* ToDo: Add 64bit IO */ -struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721s2_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -223,11 +208,7 @@ struct mm_region *mem_map = j721s2_mem_map;
#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am62_mem_map[NR_MMU_REGIONS] = { +struct mm_region am62_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -272,11 +253,7 @@ struct mm_region *mem_map = am62_mem_map;
#ifdef CONFIG_SOC_K3_AM642
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { +struct mm_region am64_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL,
On Tue, Nov 28, 2023 at 11:05:25AM -0600, Andrew Davis wrote:
NR_MMU_REGIONS is a copy/paste from another platform that extends this list later. We do not do that, so let the list be the size of the initializer list.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com
Applied to u-boot/next, thanks!
ATF and OPTEE regions may be firewalled from non-secure entities. To prevent access to this area we leave a hole there in the MMU map. This is the same idea as [0] but we complete that patch by adding the same for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae23c ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Signed-off-by: Andrew Davis afd@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index d872ed714c4..5c858ae0f84 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -24,7 +24,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, + .size = 0x1e780000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -75,7 +75,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, + .size = 0x1e780000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -123,7 +123,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, + .size = 0x1e780000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -180,7 +180,13 @@ struct mm_region j721s2_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x80000000UL, + .size = 0x1e780000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, + .phys = 0xa0000000UL, + .size = 0x60000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {
Hi Andrew,
On 28/11/23 22:35, Andrew Davis wrote:
ATF and OPTEE regions may be firewalled from non-secure entities. To prevent access to this area we leave a hole there in the MMU map. This is the same idea as [0] but we complete that patch by adding the same for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae23c ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Signed-off-by: Andrew Davis afd@ti.com
arch/arm/mach-k3/arm64-mmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index d872ed714c4..5c858ae0f84 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -24,7 +24,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,@@ -75,7 +75,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,
ATF lies 0x70000000 for j7 devices.
For reference.
configs/am62ax_evm_a53_defconfig:8:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 configs/verdin-am62_a53_defconfig:11:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 configs/am64x_evm_a53_defconfig:11:8:CONFIG_K3_ATF_LOAD_ADDR=0x701c0000 -> This is also different
configs/am62x_beagleplay_a53_defconfig:9:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 configs/am62x_evm_a53_defconfig:8:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
and rest all devices use 0x70000000
OP-TEE is consistent across all SoCs and lies at 9e800000 and I can see that removing the map after 9e780000 does handle that but am not sure if I see the ATF being unified with all this flow.
Regards, Manorit
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE}, { @@ -123,7 +123,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,@@ -180,7 +180,13 @@ struct mm_region j721s2_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x80000000UL,
.size = 0x1e780000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE- }, {
.virt = 0xa0000000UL,.phys = 0xa0000000UL,.size = 0x60000000UL,
On 11/29/23 2:00 AM, Manorit Chawdhry wrote:
Hi Andrew,
On 28/11/23 22:35, Andrew Davis wrote:
ATF and OPTEE regions may be firewalled from non-secure entities. To prevent access to this area we leave a hole there in the MMU map. This is the same idea as [0] but we complete that patch by adding the same for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae23c ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Signed-off-by: Andrew Davis afd@ti.com
arch/arm/mach-k3/arm64-mmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index d872ed714c4..5c858ae0f84 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -24,7 +24,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,@@ -75,7 +75,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,ATF lies 0x70000000 for j7 devices.
For reference.
configs/am62ax_evm_a53_defconfig:8:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
configs/verdin-am62_a53_defconfig:11:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
configs/am64x_evm_a53_defconfig:11:8:CONFIG_K3_ATF_LOAD_ADDR=0x701c0000 -> This is also different
configs/am62x_beagleplay_a53_defconfig:9:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 configs/am62x_evm_a53_defconfig:8:8:CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
and rest all devices use 0x70000000
OP-TEE is consistent across all SoCs and lies at 9e800000 and I can see that removing the map after 9e780000 does handle that but am not sure if I see the ATF being unified with all this flow.
We don't need to carve out ATF in our MMU map when it lives in SRAM as SRAM is already marked non-caching/device memory and so shouldn't be touched by U-Boot. Only when in DRAM do we do this carveout, and for all platforms that have ATF in DRAM it lies at 0x9e780000. So we make the MMU gap start at this location.
But as you have noticed, for platforms that keep ATF in SRAM this hole in DRAM is slightly larger than it needs to be (but that doesn't hurt anything, the OP-TEE hole is ~24MB and this just makes it just 128KB larger. This is DRAM so no one will care about 128KB).
The benefit of unconditionally leaving the MMU gap in DRAM cover where ATF would have been, even on SRAM platforms, is it makes the memory map unified across all platforms allowing us to combine them as in patch [4/4].
Andrew
Regards, Manorit
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE}, { @@ -123,7 +123,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,@@ -180,7 +180,13 @@ struct mm_region j721s2_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x80000000UL,
.size = 0x1e780000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE- }, {
.virt = 0xa0000000UL,.phys = 0xa0000000UL,.size = 0x60000000UL,
On Tue, Nov 28, 2023 at 11:05:26AM -0600, Andrew Davis wrote:
ATF and OPTEE regions may be firewalled from non-secure entities. To prevent access to this area we leave a hole there in the MMU map. This is the same idea as [0] but we complete that patch by adding the same for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae23c ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Signed-off-by: Andrew Davis afd@ti.com
Applied to u-boot/next, thanks!
All normal memory areas should be mapped as such.
We added these un-cached holes in our memory map to hack around the remoteproc driver missing the proper cache maintenance operations.
The problem is having these non-cached memory map areas causes stability issues later in system operation due to the nature of the K3 coherency architecture. Plus these are board specific carveouts and instead should have been added at the board level, not here in the SoC common code area.
Remove these non-cached memory map areas.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 30 +++--------------------------- 1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 5c858ae0f84..2c2d75d3f41 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -30,13 +30,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0xa0000000UL, .phys = 0xa0000000UL, - .size = 0x02100000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa2100000UL, - .phys = 0xa2100000UL, - .size = 0x5df00000UL, + .size = 0x60000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -81,13 +75,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0xa0000000UL, .phys = 0xa0000000UL, - .size = 0x04800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xa4800000UL, - .phys = 0xa4800000UL, - .size = 0x5b800000UL, + .size = 0x60000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -129,13 +117,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0xa0000000UL, .phys = 0xa0000000UL, - .size = 0x1bc00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xbbc00000UL, - .phys = 0xbbc00000UL, - .size = 0x44400000UL, + .size = 0x60000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -151,12 +133,6 @@ struct mm_region j721e_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x4d80000000UL, - .phys = 0x4d80000000UL, - .size = 0x0002000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE }, { /* List terminator */ 0,
On Tue, Nov 28, 2023 at 11:05:27AM -0600, Andrew Davis wrote:
All normal memory areas should be mapped as such.
We added these un-cached holes in our memory map to hack around the remoteproc driver missing the proper cache maintenance operations.
The problem is having these non-cached memory map areas causes stability issues later in system operation due to the nature of the K3 coherency architecture. Plus these are board specific carveouts and instead should have been added at the board level, not here in the SoC common code area.
Remove these non-cached memory map areas.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com
Applied to u-boot/next, thanks!
The Device vs Normal memory map is the same for all K3 SoCs. Merge the SoC specific maps into one.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 228 +---------------------------------- 1 file changed, 2 insertions(+), 226 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 2c2d75d3f41..b4308205b27 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -12,8 +12,7 @@ #include <asm/system.h> #include <asm/armv8/mmu.h>
-#ifdef CONFIG_SOC_K3_AM654 -struct mm_region am654_mem_map[] = { +struct mm_region k3_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -52,227 +51,4 @@ struct mm_region am654_mem_map[] = { } };
-struct mm_region *mem_map = am654_mem_map; -#endif /* CONFIG_SOC_K3_AM654 */ - -#ifdef CONFIG_SOC_K3_J721E - -#ifdef CONFIG_SOC_K3_J721E_J7200 -struct mm_region j7200_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1e780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j7200_mem_map; - -#else /* CONFIG_SOC_K3_J721E_J7200 */ -struct mm_region j721e_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1e780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721e_mem_map; -#endif /* CONFIG_SOC_K3_J721E_J7200 */ - -#endif /* CONFIG_SOC_K3_J721E */ - -#ifdef CONFIG_SOC_K3_J721S2 -struct mm_region j721s2_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1e780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721s2_mem_map; - -#endif /* CONFIG_SOC_K3_J721S2 */ - -#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) - -struct mm_region am62_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1E780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am62_mem_map; -#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ - -#ifdef CONFIG_SOC_K3_AM642 - -struct mm_region am64_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1E800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 */ +struct mm_region *mem_map = k3_mem_map;
On Tue, Nov 28, 2023 at 11:05:28AM -0600, Andrew Davis wrote:
The Device vs Normal memory map is the same for all K3 SoCs. Merge the SoC specific maps into one.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com
Applied to u-boot/next, thanks!
participants (3)
-
Andrew Davis -
Manorit Chawdhry -
Tom Rini