This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details: - IVM EEPROM is at adress: pca9547:70:9 - PCI is enabled - PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- changes for v3: - rebase to current master - use reset_phy funtion as on mgcoge3un changes for v2: - rename 128M16-1.cfg to kwbimage_128M16_1.cfg

MAINTAINERS | 1 + board/keymile/km_arm/km_arm.c | 7 +- board/keymile/km_arm/kwbimage_128M16_1.cfg | 296 ++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/km/km_arm.h | 44 ++++- include/configs/km_kirkwood.h | 67 ++++++- 6 files changed, 393 insertions(+), 23 deletions(-) create mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS index ce9fc9d..864a827 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com

km_kirkwood ARM926EJS (Kirkwood SoC) + kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index cb3402b..e77c5ad 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -134,10 +134,11 @@ int startup_allowed(void) } #endif

-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ + defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg new file mode 100644 index 0000000..3e1237b --- /dev/null +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles + +DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index a423555..64b5dbc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -142,6 +142,7 @@ lschlv2 arm arm926ejs lsxl buffalo lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index b14093f..60e2450 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */

+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif + #include "asm/arch/config.h"

#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -211,6 +218,15 @@ int get_scl(void); /* * Environment variables configurations */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ +#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ +#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 #define CONFIG_ENV_EEPROM_IS_ON_I2C @@ -218,11 +234,11 @@ int get_scl(void); #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT

#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -248,17 +264,27 @@ int get_scl(void); "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0"

-/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " xstr(CONFIG_ENV_OFFSET) " " \ + xstr(CONFIG_ENV_TOTAL_SIZE)"\0" +#else +#define CONFIG_KM_NEW_ENV \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" +#endif + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_NEW_ENV \ "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ "" diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index f639edc..34dd0a6 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -6,8 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de + * (C) Copyright 2011-2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com * * See file CREDITS for list of people who contributed to this * project. @@ -36,23 +37,67 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H

-/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ #if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #undef CONFIG_KIRKWOOD_PCIE_INIT +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile NUSA" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_PIGGY4_88E6352 + +#else +#error ("Board unsupported") #endif

+/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h" + #define CONFIG_HOSTNAME km_kirkwood

-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#endif + +#if defined(CONFIG_KM_PIGGY4_88E6352) +/* + * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via + * an Marvell 88E6352 simple switch. + * In this case we have to change the default settings for the etherent mac. + * There is NO ethernet phy. The ARM and Switch are conencted directly over + * RGMII in MAC-MAC mode + * In this case 1GBit full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_1000 |\ + MVGBE_SET_MII_SPEED_TO_100) + +#endif

/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39

Use the generic header km_kirkwood.h and get rid of the board specific header.

changes for v2: rebased because of changes in other patches

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- changes for v2 and v3: rebased because of changes in other patches

board/keymile/km_arm/km_arm.c | 9 ++-- boards.cfg | 2 +- include/configs/km_kirkwood.h | 46 +++++++++++++++++++++ include/configs/mgcoge3un.h | 87 ----------------------------------------- 4 files changed, 51 insertions(+), 93 deletions(-) delete mode 100644 include/configs/mgcoge3un.h

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 498bc36..c88292f 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -114,7 +114,7 @@ u32 kwmpp_config[] = { 0 };

-#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -134,8 +134,7 @@ int startup_allowed(void) } #endif

-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ - defined(CONFIG_KM_PIGGY4_88E6352)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* * All boards with PIGGY4 connected via a simple switch have ethernet always * present. @@ -203,7 +202,7 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -318,7 +317,7 @@ void dram_init_banksize(void) } }

-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))

#define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 808f85b..003c2af 100644 --- a/boards.cfg +++ b/boards.cfg @@ -143,7 +143,7 @@ lsxhl arm arm926ejs lsxl buffalo km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA -mgcoge3un arm arm926ejs km_arm keymile kirkwood +mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index d839a02..f5b9d27 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -58,6 +58,20 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352

+/* KM_MGCOGE3UN */ +#elif defined(CONFIG_KM_MGCOGE3UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE3UN" +#define CONFIG_HOSTNAME mgcoge3un +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6061 + +/* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ @@ -111,7 +125,39 @@

#endif

+#ifdef CONFIG_KM_PIGGY4_88E6061 +/* + * Some keymile boards like mgcoge3un have their PIGGY4 connected via + * an Marvell 88E6061 simple switch. + * In this case we have to change the default settings for the + * ethernet phy connected to the kirkwood. + * In this case 100MB full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) +#endif + /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39

+#ifdef CONFIG_KM_DISABLE_PCI +#undef CONFIG_KIRKWOOD_PCIE_INIT +#endif #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h deleted file mode 100644 index 156821c..0000000 --- a/include/configs/mgcoge3un.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_MGCOGE3UN_H -#define _CONFIG_MGCOGE3UN_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN" -#define CONFIG_HOSTNAME mgcoge3un -#define CONFIG_MGCOGE3UN - -#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ - -/* we use a new RAM type on mgcoge3un board */ -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg - -/* - * mgcoge3un has a fixed link to the marvell switch - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" -#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 - -/* - * PCIe port not used on mgcoge3un - */ -#undef CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_MGCOGE3UN_H */

From: Valentin Longchamp valentin.longchamp@keymile.com

This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD.

This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running

The boards with a PCIe FPGA but without BOCO2 still are supported.

The config option name is CONFIG_KM_FPGA_CONFIG

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- changes for v2 and v3: simply rebased

board/keymile/common/common.h | 5 + board/keymile/km_arm/Makefile | 4 + board/keymile/km_arm/fpga_config.c | 212 ++++++++++++++++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 21 +++- boards.cfg | 2 +- include/configs/km/km_arm.h | 3 + include/configs/km_kirkwood.h | 8 +- 7 files changed, 245 insertions(+), 10 deletions(-) create mode 100644 board/keymile/km_arm/fpga_config.c

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index f457aa3..aab706e 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -131,6 +131,11 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void);

+int trigger_fpga_config(void); +int wait_for_fpga_config(void); +int fpga_reset(void); +int toggle_eeprom_spi_bus(void); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index aa51255..13d485a 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o

COBJS := $(BOARD).o ../common/common.o ../common/ivm.o

+ifdef CONFIG_KM_FPGA_CONFIG +COBJS += fpga_config.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c new file mode 100644 index 0000000..4356b9a --- /dev/null +++ b/board/keymile/km_arm/fpga_config.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> + +/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ +#define KM_XLX_PROGRAM_B_PIN 39 + +#define BOCO_ADDR 0x10 + +#define ID_REG 0x00 +#define BOCO2_ID 0x5b + +static int check_boco2(void) +{ + int ret; + u8 id; + + ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); + if (ret) { + printf("%s: error reading the BOCO id !!\n", __func__); + return ret; + } + + return (id == BOCO2_ID); +} + +static int boco_clear_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval &= ~flags; + ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int boco_set_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval |= flags; + ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +#define SPI_REG 0x06 +#define CFG_EEPROM 0x02 +#define FPGA_PROG 0x04 +#define FPGA_DONE 0x20 + +int trigger_fpga_config(void) +{ + int ret = 0; + + if (check_boco2()) { + /* we have a BOCO2, this has to be triggered here */ + + /* make sure the FPGA_can access the EEPROM */ + ret = boco_clear_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + /* trigger the config start */ + ret = boco_clear_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + /* up signal for pulse end */ + ret = boco_set_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + } else { + /* we do it the old way, with the gpio pin */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + /* small delay for the pulse */ + udelay(10); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + } + + return 0; +} + +int wait_for_fpga_config(void) +{ + int ret = 0; + u8 spictrl; + u32 timeout = 20000; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe FPGA config:"); + do { + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); + if (ret) { + printf("%s: error reading the BOCO spictrl !!\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + return -EFAULT; + } + udelay(10); + } while (!(spictrl & FPGA_DONE)); + + printf(" done\n"); + + return 0; +} + +#define PRST1 0x4 +#define BRIDGE_RST 0x4 + +int fpga_reset(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_clear_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + ret = boco_set_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + return 0; +} + +/* the FPGA was configured, we configure the BOCO2 so that the EEPROM + * is available from the Bobcat SPI bus */ +int toggle_eeprom_spi_bus(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_set_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + return 0; +} + diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 835b72d..e348697 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -268,12 +268,6 @@ int board_early_init_f(void) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); -#endif return 0; }

@@ -282,6 +276,21 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;

+#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif + return 0; }

diff --git a/boards.cfg b/boards.cfg index db7902f..26c0a99 100644 --- a/boards.cfg +++ b/boards.cfg @@ -141,7 +141,7 @@ dns325 arm arm926ejs - d-link lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 60e2450..1a5f04b 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -313,4 +313,7 @@ int get_scl(void); #define CONFIG_POST_EXTERNAL_WORD_FUNCS #define CONFIG_CMD_DIAG

+/* we do the whole PCIe FPGA config stuff here */ +#define BOARD_LATE_INIT + #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 44a3e7a..0a61b7d 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -162,10 +162,12 @@ MVGBE_SET_MII_SPEED_TO_100) #endif

-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 - #ifdef CONFIG_KM_DISABLE_PCI #undef CONFIG_KIRKWOOD_PCIE_INIT #endif + +#ifndef CONFIG_KM_FPGA_CONFIG +#undef BOARD_LATE_INIT +#endif + #endif /* _CONFIG_KM_KIRKWOOD */

From: Valentin Longchamp valentin.longchamp@keymile.com

Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm).

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- changes for v2 and v3: simply rebased

board/keymile/km_arm/km_arm.c | 22 +++++++++++----------- 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e348697..50c95c6 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -328,13 +328,13 @@ void dram_init_banksize(void)

#if (defined(CONFIG_KM_PIGGY4_88E6061))

-#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1)

/* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -346,15 +346,15 @@ void reset_phy(void) return;

/* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n");

/* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n");

/* reset the phy */

From: Valentin Longchamp valentin.longchamp@keymile.com

The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part.

When the FPGA is not reconfigured, we only reset the PCIe part.

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- changes for v2 and v3: simply rebased

board/keymile/km_arm/fpga_config.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 8ac6393..fcc5fe6 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags) #define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20

-static int fpga_done() +static int fpga_done(void) { int ret = 0; u8 regval; @@ -206,25 +206,30 @@ int wait_for_fpga_config(void) }

#define PRST1 0x4 -#define BRIDGE_RST 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04

int fpga_reset(void) { int ret = 0; + u8 resets;

if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0; }

- ret = boco_clear_bits(PRST1, BRIDGE_RST); + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); if (ret) return ret;

/* small delay for the pulse */ udelay(10);

- ret = boco_set_bits(PRST1, BRIDGE_RST); + ret = boco_set_bits(PRST1, resets); if (ret) return ret;

These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u-boot binary are corrupted.

This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output.

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- changes for v3: - nothing changes for v2: - fix comment syntax

board/keymile/km_arm/km_arm.c | 43 ++++++++++++++++++++++++++-------------- include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index eb691f9..ac290fa 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -243,38 +243,51 @@ int misc_init_r(void)

int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp;

+ /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +}

+int board_init(void) +{ /* - * The FLASH_GPIO_PIN switches between using a + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + /* + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);

#if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ + /* + * Reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f + */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;

#if defined(CONFIG_KM_FPGA_CONFIG) trigger_fpga_config(); diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 1a5f04b..3aa5ca1 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -192,6 +192,7 @@ int get_sda(void); int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 #define KM_KIRKWOOD_ENV_WP 38

#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)