From: Konstantin Porotchkin kostap@marvell.com

Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

arch/arm/dts/armada-7040-db-nand.dts | 73 +--- arch/arm/dts/armada-7040-db.dts | 81 ++-- arch/arm/dts/armada-7040.dtsi | 88 +++-- arch/arm/dts/armada-8020.dtsi | 63 ++- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 72 ++-- arch/arm/dts/armada-8040-db.dts | 101 ++--- arch/arm/dts/armada-8040-mcbin.dts | 64 +-- arch/arm/dts/armada-8040-puzzle-m801.dts | 94 ++--- arch/arm/dts/armada-8040.dtsi | 113 ++++-- arch/arm/dts/armada-8k.dtsi | 18 + arch/arm/dts/armada-common.dtsi | 30 ++ arch/arm/dts/armada-cp110-slave.dtsi | 368 ------------------ ...da-cp110-master.dtsi => armada-cp110.dtsi} | 282 ++++++-------- 13 files changed, 503 insertions(+), 944 deletions(-) create mode 100644 arch/arm/dts/armada-8k.dtsi create mode 100644 arch/arm/dts/armada-common.dtsi delete mode 100644 arch/arm/dts/armada-cp110-slave.dtsi rename arch/arm/dts/{armada-cp110-master.dtsi => armada-cp110.dtsi} (55%)

diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index 3a9df21a8c2a..f249c71f6561 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* @@ -58,8 +21,8 @@ };

aliases { - i2c0 = &cpm_i2c0; - spi0 = &cpm_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp0_spi1; };

memory@00000000 { @@ -83,18 +46,18 @@ };

-&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * AUDIO [0-5] * GBE [6-11] @@ -122,9 +85,9 @@ 0xe 0xe 0x0>; };

-&cpm_spi1 { +&cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_spi0_pins>; + pinctrl-0 = <&cp0_spi0_pins>; status = "disabled";

spi-flash@0 { @@ -152,19 +115,19 @@ }; };

-&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

-&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; };

-&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; };

-&cpm_comphy { +&cp0_comphy { phy0 { phy-type = <PHY_TYPE_SGMII2>; phy-speed = <PHY_SPEED_3_125G>; @@ -196,15 +159,15 @@ }; };

-&cpm_nand { +&cp0_nand { status = "okay"; };

-&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; };

-&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; };

@@ -215,7 +178,7 @@ non-removable; };

-&cpm_sdhci0 { +&cp0_sdhci0 { status = "okay"; bus-width = <4>; no-1-8-v; diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index cfd2b4baf34d..6037f12f0e9f 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* @@ -57,8 +20,8 @@ };

aliases { - i2c0 = &cpm_i2c0; - spi0 = &cpm_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp0_spi1; };

memory@00000000 { @@ -82,18 +45,18 @@ };

-&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * TDM [0-11] * SPI [13-16] @@ -115,9 +78,9 @@ 0xE 0xE 0xE >; };

-&cpm_spi1 { +&cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_spi0_pins>; + pinctrl-0 = <&cp0_spi0_pins>; status = "okay";

spi-flash@0 { @@ -145,19 +108,19 @@ }; };

-&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

-&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; };

-&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; };

-&cpm_comphy { +&cp0_comphy { phy0 { phy-type = <PHY_TYPE_SGMII1>; phy-speed = <PHY_SPEED_1_25G>; @@ -188,11 +151,11 @@ }; };

-&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; };

-&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; };

@@ -203,14 +166,14 @@ non-removable; };

-&cpm_sdhci0 { +&cp0_sdhci0 { status = "okay"; bus-width = <4>; no-1-8-v; non-removable; };

-&cpm_mdio { +&cp0_mdio { phy0: ethernet-phy@0 { reg = <0>; }; @@ -219,22 +182,22 @@ }; };

-&cpm_ethernet { +&cp0_ethernet { status = "okay"; };

-&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; /* lane-2 */ };

-&cpm_eth1 { +&cp0_eth1 { status = "okay"; phy = <&phy0>; phy-mode = "sgmii"; };

-&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi index b5be0c4652ed..ee9716a6c6cc 100644 --- a/arch/arm/dts/armada-7040.dtsi +++ b/arch/arm/dts/armada-7040.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* @@ -46,11 +9,56 @@ */

#include <dt-bindings/gpio/gpio.h> +#include "armada-common.dtsi" +#include "armada-8k.dtsi" #include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM

/ { model = "Marvell Armada 7040"; compatible = "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; + +&cp0_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl"; + bank-name ="cp0-110"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; + marvell,function = <3>; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins = < 44 45 46 47 48 49 50 51 + 52 53 54 55 >; + marvell,function = <1>; + }; + cp0_pca0_pins: cp0-pca0_pins { + marvell,pins = <62>; + marvell,function = <0>; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi index 048e5cf5160e..4c71cf35006e 100644 --- a/arch/arm/dts/armada-8020.dtsi +++ b/arch/arm/dts/armada-8020.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* @@ -45,9 +8,27 @@ * two CP110. */

+#include "armada-common.dtsi" +#include "armada-8k.dtsi" #include "armada-ap806-dual.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM + +/* CP110-1 Settings */ +#define CP110_NAME cp1 +#define CP110_NUM 1 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM

/ { model = "Marvell Armada 8020"; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 720c95082b6b..86df6ac0b202 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -15,9 +15,9 @@ };

aliases { - i2c0 = &cpm_i2c0; - i2c1 = &cpm_i2c1; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + spi0 = &cp1_spi1; };

memory@00000000 { @@ -31,14 +31,14 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; startup-delay-us = <300000>; shutdown-delay-us = <500000>; regulator-force-boot-off; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ }; }; }; @@ -66,7 +66,7 @@ status = "okay"; };

-&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -99,57 +99,57 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >;

- cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cp0-pcie-reset-pins { marvell,pins = < 32 >; marvell,function = <0>; };

- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cp0-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; };

- cps_1g_phy_reset: cps-1g-phy-reset { + cp1_1g_phy_reset: cp1-1g-phy-reset { marvell,pins = < 43 >; marvell,function = <0>; }; };

/* uSD slot */ -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width = <4>; status = "okay"; };

-&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

-&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) @@ -179,31 +179,31 @@ }; };

-&cpm_ethernet { +&cp0_ethernet { pinctrl-names = "default"; status = "okay"; };

/* 10G SFI SFP */ -&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; };

-&cps_sata0 { +&cp1_sata0 { status = "okay"; };

-&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <&reg_usb3h0_vbus>; status = "okay"; };

-&cps_utmi0 { +&cp1_utmi0 { status = "okay"; };

-&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -234,9 +234,9 @@ 0xff 0xff 0xff>; };

-&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay";

spi-flash@0 { @@ -261,7 +261,7 @@ }; };

-&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: SATA 1 (RX swapped). Can be PCIe0 @@ -294,30 +294,30 @@ }; };

-&cps_mdio { +&cp1_mdio { phy0: ethernet-phy@0 { reg = <0>; }; };

-&cps_ethernet { +&cp1_ethernet { pinctrl-names = "default"; - pinctrl-0 = <&cps_1g_phy_reset>; + pinctrl-0 = <&cp1_1g_phy_reset>; status = "okay"; };

/* 1G SGMII */ -&cps_eth1 { +&cp1_eth1 { status = "okay"; phy-mode = "sgmii"; phy = <&phy0>; - phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>; };

/* 2.5G to Topaz switch */ -&cps_eth2 { +&cp1_eth2 { status = "okay"; phy-mode = "sgmii"; phy-speed = <2500>; - phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 65b30bbc6485..a2b7c992a406 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016 - 2021 Marvell International Ltd. */

/* @@ -56,8 +19,8 @@ };

aliases { - i2c0 = &cpm_i2c0; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp1_spi1; };

memory@00000000 { @@ -88,7 +51,7 @@ status = "okay"; };

-&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins * [11] CLKOUT_MPP_11 (out) @@ -116,7 +79,7 @@ 0xe 0xe 0xe>; };

-&cpm_comphy { +&cp0_comphy { /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 @@ -146,57 +109,57 @@ };

/* CON6 on CP0 expansion */ -&cpm_pcie0 { +&cp0_pcie0 { status = "okay"; };

-&cpm_pcie1 { +&cp0_pcie1 { status = "disabled"; };

/* CON5 on CP0 expansion */ -&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; };

/* CON4 on CP0 expansion */ -&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

/* CON9 on CP0 expansion */ -&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; };

/* CON10 on CP0 expansion */ -&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; };

-&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; };

-&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; };

-&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width = <4>; status = "okay"; };

-&cps_pinctl { +&cp1_pinctl { /* MPP Bus: * [0-11] RGMII0 * [13-16] SPI1 @@ -215,7 +178,7 @@ 0xff 0xff 0xff>; };

-&cps_comphy { +&cp1_comphy { /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 @@ -245,22 +208,22 @@ };

/* CON6 on CP1 expansion */ -&cps_pcie0 { +&cp1_pcie0 { status = "okay"; };

-&cps_pcie1 { +&cp1_pcie1 { status = "okay"; };

/* CON5 on CP1 expansion */ -&cps_pcie2 { +&cp1_pcie2 { status = "okay"; };

-&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay";

spi-flash@0 { @@ -288,35 +251,35 @@ };

/* CON4 on CP1 expansion */ -&cps_sata0 { +&cp1_sata0 { status = "okay"; };

/* CON9 on CP1 expansion */ -&cps_usb3_0 { +&cp1_usb3_0 { status = "okay"; };

/* CON10 on CP1 expansion */ -&cps_usb3_1 { +&cp1_usb3_1 { status = "okay"; };

-&cps_utmi0 { +&cp1_utmi0 { status = "okay"; };

-&cpm_mdio { +&cp0_mdio { phy1: ethernet-phy@1 { reg = <1>; }; };

-&cpm_ethernet { +&cp0_ethernet { status = "okay"; };

-&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 5a046d9de474..b0a36e328bc9 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2016 - 2021 Marvell International Ltd. */

#include "armada-8040.dtsi" /* include SoC device tree */ @@ -15,12 +15,12 @@ };

aliases { - i2c0 = &cpm_i2c0; - i2c1 = &cpm_i2c1; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + spi0 = &cp1_spi1; gpio0 = &ap_gpio0; - gpio1 = &cpm_gpio0; - gpio2 = &cpm_gpio1; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; };

memory@00000000 { @@ -36,7 +36,7 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -44,7 +44,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ }; }; }; @@ -73,7 +73,7 @@ status = "okay"; };

-&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -108,59 +108,59 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >;

- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cp0-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; };

- cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cp0-pcie-reset-pins { marvell,pins = < 52 >; marvell,function = <0>; }; };

/* uSD slot */ -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width= <4>; status = "okay"; };

/* PCIe x4 */ -&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; };

-&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

-&cpm_mdio { +&cp0_mdio { ge_phy: ethernet-phy@0 { reg = <0>; }; };

-&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x4) @@ -190,30 +190,30 @@ }; };

-&cps_sata0 { +&cp1_sata0 { status = "okay"; };

-&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <&reg_usb3h0_vbus>; status = "okay"; };

-&cps_utmi0 { +&cp1_utmi0 { status = "okay"; };

-&cps_ethernet { +&cp1_ethernet { status = "okay"; };

-&cps_eth1 { +&cp1_eth1 { status = "okay"; phy = <&ge_phy>; phy-mode = "sgmii"; };

-&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -246,9 +246,9 @@ 0xff 0xff 0xff>; };

-&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay";

spi-flash@0 { @@ -275,7 +275,7 @@ }; };

-&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: SGMII1 diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 58edb5b3aa3d..ff46ce50cbc7 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -16,14 +16,14 @@ };

aliases { - i2c0 = &i2c0; - i2c1 = &cpm_i2c0; - i2c2 = &cpm_i2c1; + i2c0 = &ap_i2c0; + i2c1 = &cp0_i2c0; + i2c2 = &cp0_i2c1; i2c3 = &i2c_switch; - spi0 = &spi0; + spi0 = &ap_spi0; gpio0 = &ap_gpio0; - gpio1 = &cpm_gpio0; - gpio2 = &cpm_gpio1; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; gpio3 = &sfpplus_gpio; };

@@ -40,7 +40,7 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -48,12 +48,12 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ }; }; };

-&i2c0 { +&ap_i2c0 { status = "okay"; clock-frequency = <100000>;

@@ -83,7 +83,7 @@ 0 3 0 0 0 0 0 0 0 3 >; };

-&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -118,35 +118,35 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >;

- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cpm-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; };

- cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cpm-pcie-reset-pins { marvell,pins = < 52 >; marvell,function = <0>; }; };

-&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width= <4>; status = "okay"; };

-&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; };

-&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>;

@@ -158,9 +158,9 @@ }; };

-&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>;

@@ -172,44 +172,44 @@ }; };

-&cpm_sata0 { +&cp0_sata0 { status = "okay"; };

-&cpm_ethernet { +&cp0_ethernet { pinctrl-names = "default"; status = "okay"; };

-&cpm_mdio { +&cp0_mdio { status = "okay"; - cpm_ge_phy0: ethernet-phy@1 { + cp0_ge_phy0: ethernet-phy@1 { reg = <0>; };

- cpm_ge_phy1: ethernet-phy@2 { + cp0_ge_phy1: ethernet-phy@2 { reg = <1>; }; };

-&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; };

-&cpm_eth1 { +&cp0_eth1 { status = "okay"; phy-mode = "sgmii"; - phy = <&cpm_ge_phy0>; + phy = <&cp0_ge_phy0>; };

-&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy-mode = "sgmii"; - phy = <&cpm_ge_phy1>; + phy = <&cp0_ge_phy1>; };

-&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) @@ -241,54 +241,54 @@ }; };

-&cps_mdio { +&cp1_mdio { status = "okay"; - cps_ge_phy0: ethernet-phy@3 { + cp1_ge_phy0: ethernet-phy@3 { reg = <1>; };

- cps_ge_phy1: ethernet-phy@4 { + cp1_ge_phy1: ethernet-phy@4 { reg = <0>; }; };

-&cps_pcie0 { +&cp1_pcie0 { num-lanes = <2>; pinctrl-names = "default"; status = "okay"; };

-&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <&reg_usb3h0_vbus>; status = "okay"; };

-&cps_utmi0 { +&cp1_utmi0 { status = "okay"; };

-&cps_ethernet { +&cp1_ethernet { status = "okay"; };

-&cps_eth0 { +&cp1_eth0 { status = "okay"; phy-mode = "sfi"; };

-&cps_eth1 { +&cp1_eth1 { status = "okay"; - phy = <&cps_ge_phy0>; + phy = <&cp1_ge_phy0>; phy-mode = "sgmii"; };

-&cps_eth2 { +&cp1_eth2 { status = "okay"; - phy = <&cps_ge_phy1>; + phy = <&cp1_ge_phy1>; phy-mode = "sgmii"; };

-&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -321,7 +321,7 @@ 0xff 0xff 0xff>; };

-&spi0 { +&ap_spi0 { status = "okay";

spi-flash@0 { @@ -356,7 +356,7 @@ }; };

-&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: PCIe0 (x2) diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi index 96cc112ac9c9..1d77e75d40a9 100644 --- a/arch/arm/dts/armada-8040.dtsi +++ b/arch/arm/dts/armada-8040.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* @@ -46,12 +9,80 @@ */

#include <dt-bindings/gpio/gpio.h> +#include "armada-common.dtsi" +#include "armada-8k.dtsi" #include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM + +/* CP110-1 Settings */ +#define CP110_NAME cp1 +#define CP110_NUM 1 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM +

/ { model = "Marvell Armada 8040"; compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; + +&cp0_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl"; + bank-name ="cp0-110"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; + marvell,function = <3>; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins = < 44 45 46 47 48 49 50 51 + 52 53 54 55 >; + marvell,function = <1>; + }; + cp0_pca0_pins: cp0-pca0_pins { + marvell,pins = <62>; + marvell,function = <0>; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; + +&cp1_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl"; + bank-name ="cp1-110"; + + cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11 >; + marvell,function = <3>; + }; + cp1_spi1_pins: cp1-spi-pins-1 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; diff --git a/arch/arm/dts/armada-8k.dtsi b/arch/arm/dts/armada-8k.dtsi new file mode 100644 index 000000000000..c6af9ce631c1 --- /dev/null +++ b/arch/arm/dts/armada-8k.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 - 2021 Marvell International Ltd. + */ +/* Common definitions used by Armada 8K DTs */ + +/* This defines used to calculate the base address of each CP */ +#define CP110_BASE_OFFSET (0xf2000000) +#define CP110_SPACE_SIZE (0x02000000) +#define CP110_BASE (CP110_BASE_OFFSET + \ + ((CP110_NUM % 2) * CP110_SPACE_SIZE)) + +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) \ + (0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) \ + (CP110_PCIEx_CPU_MEM_BASE(iface)) +#define CP110_PCIE_BUS_MEM_CFG (0x82000000) diff --git a/arch/arm/dts/armada-common.dtsi b/arch/arm/dts/armada-common.dtsi new file mode 100644 index 000000000000..b7dfbda3926f --- /dev/null +++ b/arch/arm/dts/armada-common.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Marvell International Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## _ ## y +#define EVALUATOR(x, y) PASTER(x, y) + +/* This define used to create die label: + * For example: + * CP110 master: + * CP110_LABEL(spi0) -> cp0_spi0 + * CP110 slave: + * CP110_LABEL(usb0) -> cp1_usb0 + */ +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, name) + +#define APPEND_NX(A, B) A ##-## B +#define APPEND(A, B) APPEND_NX(A, B) + +#define STRINGIZE_NX(x) #x +#define STRINGIZE(x) STRINGIZE_NX(x) + +/* Same idea here, but this define convert the name to string: + * For example: + * master: CP110_STRING_LABEL(ppv2) -> "cp0-ppv2" + * slave: CP110_STRING_LABEL(ppv2) -> "cp1-ppv2" + */ +#define CP110_STRING_LABEL(name) STRINGIZE(APPEND(CP110_NAME, name)) diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi deleted file mode 100644 index 6cf217783709..000000000000 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Device Tree file for Marvell Armada CP110 Slave. - */ - -#include <dt-bindings/comphy/comphy_data.h> - -/ { - cp110-slave { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0xf4000000 0x2000000>; - - cps_ethernet: ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; - clock-names = "pp_clk", "gop_clk", "mg_clk"; - status = "disabled"; - dma-coherent; - - cps_eth0: eth0 { - interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - cps_eth1: eth1 { - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; - - cps_eth2: eth2 { - interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; - - cps_mdio: mdio@12a200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x12a200 0x10>; - device-name = "cps-mdio"; - }; - - cps_xmdio: mdio@12a600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,xmdio"; - reg = <0x12a600 0x16>; - status = "disabled"; - device-name = "cps-xmdio"; - }; - - cps_syscon0: system-controller@440000 { - compatible = "marvell,cp110-system-controller0", - "syscon"; - reg = <0x440000 0x1000>; - #clock-cells = <2>; - core-clock-output-names = - "cps-apll", "cps-ppv2-core", "cps-eip", - "cps-core", "cps-nand-core"; - gate-clock-output-names = - "cps-audio", "cps-communit", "cps-nand", - "cps-ppv2", "cps-sdio", "cps-mg-domain", - "cps-mg-core", "cps-xor1", "cps-xor0", - "cps-gop-dp", "none", "cps-pcie_x10", - "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", - "cps-sata", "cps-sata-usb", "cps-main", - "cps-sd-mmc", "none", "none", - "cps-slow-io", "cps-usb3h0", "cps-usb3h1", - "cps-usb3dev", "cps-eip150", "cps-eip197"; - }; - - cps_pinctl: cps-pinctl@440000 { - compatible = "marvell,mvebu-pinctrl", - "marvell,armada-8k-cps-pinctrl"; - bank-name ="cp1-110"; - reg = <0x440000 0x20>; - pin-count = <63>; - max-func = <0xf>; - - cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { - marvell,pins = < 0 1 2 3 4 5 6 7 - 8 9 10 11 >; - marvell,function = <3>; - }; - cps_spi1_pins: cps-spi-pins-1 { - marvell,pins = < 13 14 15 16 >; - marvell,function = <3>; - }; - }; - - cps_gpio0: gpio@440100 { - compatible = "marvell,orion-gpio"; - reg = <0x440100 0x40>; - ngpios = <32>; - gpiobase = <20>; - gpio-controller; - #gpio-cells = <2>; - }; - - cps_gpio1: gpio@440140 { - compatible = "marvell,orion-gpio"; - reg = <0x440140 0x40>; - ngpios = <31>; - gpiobase = <52>; - gpio-controller; - #gpio-cells = <2>; - }; - - cps_sata0: sata@540000 { - compatible = "marvell,armada-8k-ahci"; - reg = <0x540000 0x30000>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 15>; - status = "disabled"; - }; - - cps_usb3_0: usb3@500000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x500000 0x4000>; - dma-coherent; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 22>; - status = "disabled"; - }; - - cps_usb3_1: usb3@510000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x510000 0x4000>; - dma-coherent; - interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 23>; - status = "disabled"; - }; - - cps_xor0: xor@6a0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6a0000 0x1000>, - <0x6b0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 8>; - }; - - cps_xor1: xor@6c0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6c0000 0x1000>, - <0x6d0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 7>; - }; - - cps_spi0: spi@700600 { - compatible = "marvell,armada-380-spi"; - reg = <0x700600 0x50>; - #address-cells = <0x1>; - #size-cells = <0x0>; - cell-index = <1>; - clocks = <&cps_syscon0 0 3>; - status = "disabled"; - }; - - cps_spi1: spi@700680 { - compatible = "marvell,armada-380-spi"; - reg = <0x700680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <2>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_i2c0: i2c@701000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_i2c1: i2c@701100 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_comphy: comphy@441000 { - compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; - reg = <0x441000 0x8>, - <0x120000 0x8>; - mux-bitcount = <4>; - max-lanes = <6>; - }; - - cps_utmi0: utmi@580000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x580000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST0>; - status = "disabled"; - }; - - cps_nand: nand@720000 { - compatible = "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg = <0x720000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&cps_syscon0 1 2>, - <&cps_syscon0 1 17>; - marvell,system-controller = <&cps_syscon0>; - nand-enable-arbiter; - num-cs = <1>; - status = "disabled"; - }; - }; - - cps_pcie0: pcie@f4600000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4600000 0 0x10000>, - <0 0xfaf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <1>; - clocks = <&cps_syscon0 1 13>; - status = "disabled"; - }; - - cps_pcie1: pcie@f4620000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4620000 0 0x10000>, - <0 0xfbf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clocks = <&cps_syscon0 1 11>; - status = "disabled"; - }; - - cps_pcie2: pcie@f4640000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4640000 0 0x10000>, - <0 0xfcf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clocks = <&cps_syscon0 1 12>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110.dtsi similarity index 55% rename from arch/arm/dts/armada-cp110-master.dtsi rename to arch/arm/dts/armada-cp110.dtsi index 7d0d31da306d..d9c445601266 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110.dtsi @@ -1,53 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */

/* - * Device Tree file for Marvell Armada CP110 Master. + * Generic Device Tree describing Marvell Armada CP-110 device */

#include <dt-bindings/comphy/comphy_data.h>

+#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) +#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) + +#define CP110_PCIEx_REG0_BASE(iface) \ + (CP110_BASE + 0x600000 + (iface) * 0x20000) +#define CP110_PCIEx_REG1_BASE(iface) \ + (CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface)) +#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \ + (iface) * 0x4000) + / { - cp110-master { + CP110_NAME { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; @@ -59,56 +32,36 @@ #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&gic>; - ranges = <0x0 0x0 0xf2000000 0x2000000>; - - cpm_ethernet: ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; - clock-names = "pp_clk", "gop_clk", "mg_clk"; - status = "disabled"; - dma-coherent; - - cpm_eth0: eth0 { - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - cpm_eth1: eth1 { - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; + ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;

- cpm_eth2: eth2 { - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; - - cpm_mdio: mdio@12a200 { + CP110_LABEL(mdio): mdio@12a200 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; - device-name = "cpm-mdio"; + device-name = CP110_STRING_LABEL(mdio); + status = "disabled"; };

- cpm_xmdio: mdio@12a600 { + CP110_LABEL(xmdio): mdio@12a600 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,xmdio"; - reg = <0x12a600 0x16>; + reg = <0x12a600 0x200>; + device-name = CP110_STRING_LABEL(xmdio); status = "disabled"; - device-name = "cpm-xmdio"; };

- cpm_syscon0: system-controller@440000 { + CP110_LABEL(sar-reg) { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-cp110"; + reg = <0x400200 0x8>; + sar-driver = "cp110_sar"; + sar-name = CP110_STRING_LABEL(sar); + status = "okay"; + }; + + CP110_LABEL(syscon0): system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon"; reg = <0x440000 0x1000>; @@ -128,43 +81,14 @@ "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; };

- cpm_pinctl: cpm-pinctl@440000 { - compatible = "marvell,mvebu-pinctrl", - "marvell,armada-7k-pinctrl", - "marvell,armada-8k-cpm-pinctrl"; - bank-name ="cp0-110"; + CP110_LABEL(pinctl): pinctl@440000 { + compatible = "marvell,mvebu-pinctrl"; reg = <0x440000 0x20>; pin-count = <63>; max-func = <0xf>; - - cpm_i2c0_pins: cpm-i2c-pins-0 { - marvell,pins = < 37 38 >; - marvell,function = <2>; - }; - cpm_i2c1_pins: cpm-i2c-pins-1 { - marvell,pins = < 35 36 >; - marvell,function = <2>; - }; - cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { - marvell,pins = < 44 45 46 47 48 49 50 51 - 52 53 54 55 >; - marvell,function = <1>; - }; - pca0_pins: cpm-pca0_pins { - marvell,pins = <62>; - marvell,function = <0>; - }; - cpm_sdhci_pins: cpm-sdhi-pins-0 { - marvell,pins = < 56 57 58 59 60 61 >; - marvell,function = <14>; - }; - cpm_spi0_pins: cpm-spi-pins-0 { - marvell,pins = < 13 14 15 16 >; - marvell,function = <3>; - }; };

- cpm_gpio0: gpio@440100 { + CP110_LABEL(gpio0): gpio@440100 { compatible = "marvell,orion-gpio"; reg = <0x440100 0x40>; ngpios = <32>; @@ -173,7 +97,7 @@ #gpio-cells = <2>; };

- cpm_gpio1: gpio@440140 { + CP110_LABEL(gpio1): gpio@440140 { compatible = "marvell,orion-gpio"; reg = <0x440140 0x40>; ngpios = <31>; @@ -182,75 +106,85 @@ #gpio-cells = <2>; };

- cpm_sata0: sata@540000 { + CP110_LABEL(sata0): sata@540000 { compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 15>; + clocks = <&CP110_LABEL(syscon0) 1 15>; status = "disabled"; };

- cpm_usb3_0: usb3@500000 { + CP110_LABEL(usb3_0): usb3@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x500000 0x4000>; dma-coherent; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 22>; + clocks = <&CP110_LABEL(syscon0) 1 22>; status = "disabled"; };

- cpm_usb3_1: usb3@510000 { + CP110_LABEL(usb3_1): usb3@510000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x510000 0x4000>; dma-coherent; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 23>; + clocks = <&CP110_LABEL(syscon0) 1 23>; status = "disabled"; };

- cpm_spi0: spi@700600 { + CP110_LABEL(spi0): spi@700600 { compatible = "marvell,armada-380-spi"; reg = <0x700600 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <1>; - clocks = <&cpm_syscon0 0 3>; + spi-max-frequency = <50000000>; + clocks = <&CP110_LABEL(syscon0) 0 3>; status = "disabled"; };

- cpm_spi1: spi@700680 { + CP110_LABEL(spi1): spi@700680 { compatible = "marvell,armada-380-spi"; reg = <0x700680 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <2>; - clocks = <&cpm_syscon0 1 21>; + spi-max-frequency = <50000000>; + clocks = <&CP110_LABEL(syscon0) 1 21>; status = "disabled"; };

- cpm_i2c0: i2c@701000 { + CP110_LABEL(i2c0): i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&CP110_LABEL(syscon0) 1 21>; status = "disabled"; };

- cpm_i2c1: i2c@701100 { + CP110_LABEL(i2c1): i2c@701100 { compatible = "marvell,mv78230-i2c"; reg = <0x701100 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&CP110_LABEL(syscon0) 1 21>; + status = "disabled"; + }; + + CP110_LABEL(mss_i2c0): i2c@211000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; };

- cpm_comphy: comphy@441000 { + CP110_LABEL(comphy): comphy@441000 { compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; reg = <0x441000 0x8>, <0x120000 0x8>; @@ -258,7 +192,7 @@ max-lanes = <6>; };

- cpm_utmi0: utmi@580000 { + CP110_LABEL(utmi0): utmi@580000 { compatible = "marvell,mvebu-utmi-2.6.0"; reg = <0x580000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ @@ -267,7 +201,7 @@ status = "disabled"; };

- cpm_utmi1: utmi@581000 { + CP110_LABEL(utmi1): utmi@581000 { compatible = "marvell,mvebu-utmi-2.6.0"; reg = <0x581000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ @@ -276,7 +210,7 @@ status = "disabled"; };

- cpm_sdhci0: sdhci@780000 { + CP110_LABEL(sdhci0): sdhci@780000 { compatible = "marvell,armada-8k-sdhci"; reg = <0x780000 0x300>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; @@ -284,28 +218,57 @@ status = "disabled"; };

- cpm_nand: nand@720000 { + CP110_LABEL(nand): nand@720000 { compatible = "marvell,armada-8k-nand-controller", "marvell,armada370-nand-controller"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&cpm_syscon0 1 2>, - <&cpm_syscon0 1 17>; - marvell,system-controller = <&cpm_syscon0>; + clocks = <&CP110_LABEL(syscon0) 1 2>; nand-enable-arbiter; num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; status = "disabled"; };

+ CP110_LABEL(ethernet): ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; + status = "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; + }; + }; };

- cpm_pcie0: pcie@f2600000 { + CP110_LABEL(pcie0): pcie0@600000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2600000 0 0x10000>, - <0 0xf6f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>, + /* Last 512KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -315,22 +278,25 @@

bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0)) + U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; num-lanes = <1>; - clocks = <&cpm_syscon0 1 13>; + clocks = <&CP110_LABEL(syscon0) 1 13>; status = "disabled"; };

- cpm_pcie1: pcie@f2620000 { + CP110_LABEL(pcie1): pcie1@620000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2620000 0 0x10000>, - <0 0xf7f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>, + /* Last 512KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -340,23 +306,26 @@

bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1)) + U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

num-lanes = <1>; - clocks = <&cpm_syscon0 1 11>; + clocks = <&CP110_LABEL(syscon0) 1 11>; status = "disabled"; };

- cpm_pcie2: pcie@f2640000 { + CP110_LABEL(pcie2): pcie2@640000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2640000 0 0x10000>, - <0 0xf8f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>, + /* Last 64KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -366,16 +335,17 @@

bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2)) + U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

num-lanes = <1>; - clocks = <&cpm_syscon0 1 12>; + clocks = <&CP110_LABEL(syscon0) 1 12>; status = "disabled"; }; };

From: Konstantin Porotchkin kostap@marvell.com

Move the default environment location to the end of 4MB flash region. This change allows to accomodate larger flash boot images making space for forthcoming code changes.

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

configs/mvebu_db-88f3720_defconfig | 2 +- configs/mvebu_db_armada8k_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index a6bbe1a7afbc..95019b728a8c 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x180000 +CONFIG_ENV_OFFSET=0x3f0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xd0012000 diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 5d8a1b655cd5..ffe8e029050f 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x180000 +CONFIG_ENV_OFFSET=0x3f0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000

From: Konstantin Porotchkin kostap@marvell.com

This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB. Not all interfaces are supported fully yet.

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de

---

arch/arm/mach-mvebu/Kconfig | 10 +++ board/Marvell/octeontx2_cn913x/MAINTAINERS | 6 ++ board/Marvell/octeontx2_cn913x/Makefile | 8 +++ board/Marvell/octeontx2_cn913x/board.c | 45 ++++++++++++ configs/mvebu_crb_cn9130_defconfig | 84 ++++++++++++++++++++++ 5 files changed, 153 insertions(+) create mode 100644 board/Marvell/octeontx2_cn913x/MAINTAINERS create mode 100644 board/Marvell/octeontx2_cn913x/Makefile create mode 100644 board/Marvell/octeontx2_cn913x/board.c create mode 100644 configs/mvebu_crb_cn9130_defconfig

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0299611cbf94..cda65f74786f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -141,6 +141,13 @@ config TARGET_MVEBU_ARMADA_8K select BOARD_LATE_INIT imply SCSI

+config TARGET_OCTEONTX2_CN913x + bool "Support CN913x platforms" + select ARMADA_8K + imply BOARD_EARLY_INIT_R + select BOARD_LATE_INIT + imply SCSI + config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" select MV78460 @@ -187,6 +194,7 @@ config SYS_BOARD default "turris_omnia" if TARGET_TURRIS_OMNIA default "turris_mox" if TARGET_TURRIS_MOX default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K + default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM @@ -204,6 +212,7 @@ config SYS_CONFIG_NAME default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-88f6820-amc" if TARGET_DB_88F6820_AMC default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K + default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM @@ -222,6 +231,7 @@ config SYS_VENDOR default "Marvell" if TARGET_DB_88F6820_GP default "Marvell" if TARGET_DB_88F6820_AMC default "Marvell" if TARGET_MVEBU_ARMADA_8K + default "Marvell" if TARGET_OCTEONTX2_CN913x default "Marvell" if TARGET_DB_XC3_24G4XG default "Marvell" if TARGET_MVEBU_DB_88F7040 default "solidrun" if TARGET_CLEARFOG diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS b/board/Marvell/octeontx2_cn913x/MAINTAINERS new file mode 100644 index 000000000000..6aadd7a0458f --- /dev/null +++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS @@ -0,0 +1,6 @@ +OCTEONTX2_CN913x BOARD +M: Kostya Porotchkin kostap@marvell.com +S: Maintained +F: board/Marvell/octeontx2_cn913x/ +F: include/configs/octeontx2_cn913x.h +F: configs/mvebu_db_cn91xx_defconfig diff --git a/board/Marvell/octeontx2_cn913x/Makefile b/board/Marvell/octeontx2_cn913x/Makefile new file mode 100644 index 000000000000..8c6ffb932871 --- /dev/null +++ b/board/Marvell/octeontx2_cn913x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Stefan Roese sr@denx.de +# Copyright (C) 2019 Marvell International Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c new file mode 100644 index 000000000000..953e9db9c8e8 --- /dev/null +++ b/board/Marvell/octeontx2_cn913x/board.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Stefan Roese sr@denx.de + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <dm.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int soc_early_init_f(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + soc_early_init_f(); + + return 0; +} + +int board_early_init_r(void) +{ + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + /* Check if any existing regulator should be turned down */ + regulators_enable_boot_off(false); + } + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig new file mode 100644 index 000000000000..03bc44b3446c --- /dev/null +++ b/configs/mvebu_crb_cn9130_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_OCTEONTX2_CN913x=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3f0000 +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="cn9130-crb-A" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Marvell>> " +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_MVEBU_MMC_BOOT=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_AHCI_MVEBU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y