[U-Boot] [PATCH 01/10] spi: Remove MIPS dependency from Broadcom HSSPI driver.
From: Kursad Oney kursad.oney@broadcom.com
This IP exists in both MIPS and ARM cores, so there is no need to tie it up to MIPS only. Remove the dependency.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- drivers/spi/Kconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f459c0a..749917b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -67,7 +67,6 @@ config ATMEL_SPI
config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on ARCH_BMIPS help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom
From: Kursad Oney kursad.oney@broadcom.com
Make the driver compatible with both big and little endian SOCs. Replace big-endian calls with their raw equivalents, expect for writing the command to FIFO. That still has to be in big-endian format.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- drivers/spi/bcm63xx_hsspi.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 4f527fa7..7306531 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -120,9 +120,9 @@ static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
/* clock polarity */ if (mode & SPI_CPOL) - setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); else - clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
return 0; } @@ -146,7 +146,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, set = DIV_ROUND_UP(2048, set); set &= SPI_PFL_CLK_FREQ_MASK; set |= SPI_PFL_CLK_RSTLOOP_MASK; - writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
/* profile signal */ set = 0; @@ -164,7 +164,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, if (priv->speed > SPI_MAX_SYNC_CLOCK) set |= SPI_PFL_SIG_ASYNCIN_MASK;
- clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
/* global control */ set = 0; @@ -182,13 +182,13 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, else set |= BIT(!plat->cs);
- clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); + clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); }
static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) { /* restore cs polarities */ - clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, + clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, priv->cs_pols); }
@@ -247,7 +247,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, SPI_PFL_MODE_MDWRSZ_MASK; if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; - writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
/* transfer loop */ while (data_bytes > 0) { @@ -262,7 +262,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, }
/* set fifo operation */ - writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK), + writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)), priv->regs + HSSPI_FIFO_OP_REG);
/* issue the transfer */ @@ -271,10 +271,10 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, SPI_CMD_PFL_MASK; val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; - writel_be(val, priv->regs + SPI_CMD_REG); + writel(val, priv->regs + SPI_CMD_REG);
/* wait for completion */ - ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG, + ret = wait_for_bit_32(priv->regs + SPI_STAT_REG, SPI_STAT_SRCBUSY_MASK, false, 1000, false); if (ret) { @@ -381,16 +381,16 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) return ret;
/* initialize hardware */ - writel_be(0, priv->regs + SPI_IR_MASK_REG); + writel(0, priv->regs + SPI_IR_MASK_REG);
/* clear pending interrupts */ - writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
/* enable clk gate */ - setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
/* read default cs polarities */ - priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & + priv->cs_pols = readl(priv->regs + SPI_CTL_REG) & SPI_CTL_CS_POL_MASK;
return 0;
From: Kursad Oney kursad.oney@broadcom.com
wait_for_bit_le32 and wait_for_bit_le16 use the raw I/O functions which would default to big-endian on BE systems. Create the generic equivalents to use the native endianness.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- include/wait_bit.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/wait_bit.h b/include/wait_bit.h index 82e09da..e8f444b 100644 --- a/include/wait_bit.h +++ b/include/wait_bit.h @@ -72,12 +72,16 @@ static inline int wait_for_bit_##sfx(const void *reg, \
BUILD_WAIT_FOR_BIT(8, u8, readb) BUILD_WAIT_FOR_BIT(le16, u16, readw) +BUILD_WAIT_FOR_BIT(16, u16, readw) #ifdef readw_be BUILD_WAIT_FOR_BIT(be16, u16, readw_be) +BUILD_WAIT_FOR_BIT(16, u16, readw_be) #endif BUILD_WAIT_FOR_BIT(le32, u32, readl) +BUILD_WAIT_FOR_BIT(32, u32, readl) #ifdef readl_be BUILD_WAIT_FOR_BIT(be32, u32, readl_be) +BUILD_WAIT_FOR_BIT(32, u32, readl_be) #endif
#endif
From: Kursad Oney kursad.oney@broadcom.com
The Broadcom ARM implementations do not yet have a clock framework so one can use a fixed clock as the root clock of the hsspi block. The fixed clock does not have an "enable" routine, since it's always enabled. So when we hit this issue, getting an ENOSYS return, do not bail but continue initialization.
Similarly the block might already have been out of reset, say, when we are booting from a SPI device. So if the reset signal is not configured in the device tree, do not bail out and instead skip deasserting the reset.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- drivers/spi/bcm63xx_hsspi.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 7306531..e82b80c 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -349,32 +349,31 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) return ret;
ret = clk_enable(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret;
ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret;
/* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret;
priv->clk_rate = clk_get_rate(&clk);
ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret;
/* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); - if (ret < 0) - return ret; - - ret = reset_deassert(&rst_ctl); - if (ret < 0) - return ret; + if (ret >= 0) { + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + }
ret = reset_free(&rst_ctl); if (ret < 0)
From: Kursad Oney kursad.oney@broadcom.com
This change adds the hsspi controller to the 63158 dtsi.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- arch/arm/dts/bcm63158.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 175af38..7dd2858 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -10,6 +10,10 @@ #address-cells = <2>; #size-cells = <2>;
+ aliases { + spi0 = &hsspi; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -67,6 +71,14 @@ u-boot,dm-pre-reloc; };
+ hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + refclk50mhz: refclk50mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -192,6 +204,19 @@ status = "disabled"; };
+ hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + nand: nand-controller@ff801800 { compatible = "brcm,nand-bcm63158", "brcm,brcmnand-v5.0",
From: Kursad Oney kursad.oney@broadcom.com
This change adds a spi nor flash device to the bcm963158 board.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- arch/arm/dts/bcm963158.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index 8565944..c2bdd33 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -125,3 +125,15 @@ label = "green:aggregate_link"; }; }; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +};
From: Kursad Oney kursad.oney@broadcom.com
This commit enable the support of the spi-nor for the broadcom reference board bcm963158.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com --- configs/bcm963158_ram_defconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 5eafbaa..825d5a4 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -22,6 +22,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y CONFIG_CMD_CACHE=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y @@ -40,12 +41,18 @@ CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_63158=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPECIFY_CONSOLE_INDEX=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_CONS_INDEX=0 CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_WDT_BCM6345=y
This commit add a hsspi controller in the bcm6858 device tree.
Signed-off-by: Philippe Reynes philippe.reynes@softathome.com Reviewed-by: Kursad Oney kursad.oney@broadcom.com --- arch/arm/dts/bcm6858.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 91f7787..0222562 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -10,6 +10,10 @@ #address-cells = <2>; #size-cells = <2>;
+ aliases { + spi0 = &hsspi; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -67,6 +71,14 @@ u-boot,dm-pre-reloc; };
+ hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + refclk50mhz: refclk50mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -192,6 +204,19 @@ status = "disabled"; };
+ hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + nand: nand-controller@ff801800 { compatible = "brcm,nand-bcm6858", "brcm,brcmnand-v5.0",
This commit add a spi-nor device in the bcm96850xref device tree.
Signed-off-by: Philippe Reynes philippe.reynes@softathome.com Reviewed-by: Kursad Oney kursad.oney@broadcom.com --- arch/arm/dts/bcm968580xref.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index 861e989..a034e38 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -124,3 +124,15 @@ label = "green:wps"; }; }; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +};
This commit enable the support of the spi-nor for the broadcom reference board bcm968580xref.
Signed-off-by: Philippe Reynes philippe.reynes@softathome.com Reviewed-by: Kursad Oney kursad.oney@broadcom.com --- configs/bcm968580xref_ram_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index 49731ee..4bc501f 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -18,6 +18,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y @@ -35,12 +37,19 @@ CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6858=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPECIFY_CONSOLE_INDEX=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_CONS_INDEX=0 CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_BCM6345_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_WDT_BCM6345=y
On Tue, Aug 13, 2019 at 4:57 PM Philippe Reynes philippe.reynes@softathome.com wrote:
From: Kursad Oney kursad.oney@broadcom.com
This IP exists in both MIPS and ARM cores, so there is no need to tie it up to MIPS only. Remove the dependency.
Signed-off-by: Kursad Oney kursad.oney@broadcom.com Reviewed-by: Philippe Reynes philippe.reynes@softathome.com
drivers/spi/Kconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f459c0a..749917b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -67,7 +67,6 @@ config ATMEL_SPI
config BCM63XX_HSSPI bool "BCM63XX HSSPI driver"
depends on ARCH_BMIPS
this should only show up in menuconfig when the SoC is selected where this core is implemented. Thus this should be:
depends on (ARCH_BMIPS || ARCH_BCM6858)
IIRC we chose this approach for the other shared BCM drivers too
help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom-- 2.7.4
participants (2)
-
Daniel Schwierzeck -
Philippe Reynes