From: Fabio Estevam fabio.estevam@nxp.com

Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") ethernet does not work on mx6sabresd.

This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel.

However, on mx6sabresd design we need some additional configuration, such as enabling the 125 MHz AR8031 output that needs to be done in the board file.

This also aligns with the same method that the kernel performs the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.

Signed-off-by: Fabio Estevam fabio.estevam@nxp.com --- board/freescale/mx6sabresd/mx6sabresd.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index e58c03c..a5c2b86 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -360,6 +360,39 @@ int board_mmc_init(bd_t *bis) } #endif

+static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) {