[RESEND,PATCH v2 0/1] RISC-V tracing support
This series add a support of tracing for RISC-V arch.
This series is also available here [1] for testing. [1] https://github.com/pragnesh26992/u-boot/tree/trace
How to test this patch: 1) Enable tracing in "configs/sifive_fu540_defconfig" CONFIG_TRACE=y CONFIG_TRACE_BUFFER_SIZE=0x01000000 CONFIG_TRACE_CALL_DEPTH_LIMIT=15 CONFIG_CMD_TRACE=y
2) make FTRACE=1 sifive_fu540_defconfig 3) make FTRACE=1
Following are the boot messages on FU540 five cores SMP platform:
U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530) Trying to boot from MMC1
U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)
CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB trace: enabled MMC: spi@10050000:mmc@0: 0 *** Warning - bad CRC, using default environment
In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Board serial number should not be 0 !! Net: Error: ethernet@10090000 address not set. No ethernet found.
Hit any key to stop autoboot: 0 => trace stats 178,556 function sites 9,378,800 function calls 1 untracked function calls 1,279,056 traced function calls (8070507 dropped due to overflow) 19 maximum observed call depth 15 call depth limit 9,568,845 calls not traced due to depth => trace calls 0x83000000 0xf00000 Call list dumped to 83000000, size 0xea33d0 =>
Pragnesh Patel (1): riscv: Add timer_get_us() for tracing
drivers/timer/andes_plmt_timer.c | 16 +++++++++++++++- drivers/timer/riscv_timer.c | 14 +++++++++++++- drivers/timer/sifive_clint_timer.c | 16 +++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-)
Add timer_get_us() which is useful for tracing. For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks and For M-mode U-Boot, mtime register will provide the same.
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com --- drivers/timer/andes_plmt_timer.c | 16 +++++++++++++++- drivers/timer/riscv_timer.c | 14 +++++++++++++- drivers/timer/sifive_clint_timer.c | 16 +++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index cec86718c7..9d663e036e 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -13,11 +13,12 @@ #include <timer.h> #include <asm/io.h> #include <linux/err.h> +#include <div64.h>
/* mtime register */ #define MTIME_REG(base) ((ulong)(base))
-static u64 andes_plmt_get_count(struct udevice *dev) +static u64 notrace andes_plmt_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev->priv)); } @@ -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = { .get_count = andes_plmt_get_count, };
+#if CONFIG_IS_ENABLED(RISCV_MMODE) +unsigned long notrace timer_get_us(void) +{ + u64 ticks; + + /* FIXME: gd->arch.plic should contain valid base address */ + ticks = andes_plmt_get_count(gd->arch.plic); + do_div(ticks, CONFIG_SYS_HZ); + return ticks; +} +#endif + static int andes_plmt_probe(struct udevice *dev) { dev->priv = dev_read_addr_ptr(dev); if (!dev->priv) return -EINVAL;
+ gd->arch.plic = dev->priv; return timer_timebase_fallback(dev); }
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 21ae184057..7fa8773da3 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -15,8 +15,9 @@ #include <errno.h> #include <timer.h> #include <asm/csr.h> +#include <div64.h>
-static u64 riscv_timer_get_count(struct udevice *dev) +static u64 notrace riscv_timer_get_count(struct udevice *dev) { __maybe_unused u32 hi, lo;
@@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev) return ((u64)hi << 32) | lo; }
+#if CONFIG_IS_ENABLED(RISCV_SMODE) +unsigned long notrace timer_get_us(void) +{ + u64 ticks; + + ticks = riscv_timer_get_count(NULL); + do_div(ticks, CONFIG_SYS_HZ); + return ticks; +} +#endif + static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index 00ce0f08d6..166655e99d 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -10,11 +10,12 @@ #include <timer.h> #include <asm/io.h> #include <linux/err.h> +#include <div64.h>
/* mtime register */ #define MTIME_REG(base) ((ulong)(base) + 0xbff8)
-static u64 sifive_clint_get_count(struct udevice *dev) +static u64 notrace sifive_clint_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev->priv)); } @@ -23,12 +24,25 @@ static const struct timer_ops sifive_clint_ops = { .get_count = sifive_clint_get_count, };
+#if CONFIG_IS_ENABLED(RISCV_MMODE) +unsigned long notrace timer_get_us(void) +{ + u64 ticks; + + /* FIXME: gd->arch.clint should contain valid base address */ + ticks = sifive_clint_get_count(gd->arch.clint); + do_div(ticks, CONFIG_SYS_HZ); + return ticks; +} +#endif + static int sifive_clint_probe(struct udevice *dev) { dev->priv = dev_read_addr_ptr(dev); if (!dev->priv) return -EINVAL;
+ gd->arch.clint = dev->priv; return timer_timebase_fallback(dev); }
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Pragnesh Patel