[U-Boot] [PATCH 0/5] ARM: Allwinner sun7i (A20) USB Host EHCI support
This patch series adds USB Host EHCI support to the sun7i SoC. It was tested on Cubietruck. Now you could boot from a USB stick or use a compatible Ethernet dongle to add a second Ethernet port in U-Boot.
ehci-sunxi.c contains some code for poking GPIOs. This code will go away once some other patches for sunXi SoCs are applied against upstream. For now this patch series is self-contained and has no dependencies.
Best, Roman Byshko
Roman Byshko (5): sunxi: add defines to control USB Host clocks/resets sunxi: add USB EHCI driver sunxi: add USB options to configs sun7i: add USB EHCI configuration sun7i: cubietruck: enable USB EHCI
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 4 + boards.cfg | 2 +- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-sunxi.c | 236 ++++++++++++++++++++++++++ include/configs/sun7i.h | 8 + include/configs/sunxi-common.h | 6 + 6 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 drivers/usb/host/ehci-sunxi.c
Signed-off-by: Roman Byshko rbyshko@gmail.com --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 928f3f2..fe7348a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -253,4 +253,8 @@ struct sunxi_ccm_reg { #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHYGATE (0x1 << 8) + #endif /* _SUNXI_CLOCK_SUN4I_H */
Signed-off-by: Roman Byshko rbyshko@gmail.com --- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-sunxi.c | 236 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+) create mode 100644 drivers/usb/host/ehci-sunxi.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 04c1a64..c4f5157 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o +obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c new file mode 100644 index 0000000..5817fc7 --- /dev/null +++ b/drivers/usb/host/ehci-sunxi.c @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2014 arokux + * + * arokux arokux@gmail.com + * + * Based on code from + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include "ehci.h" + +#define BIT(x) (1 << (x)) + +#define SUNXI_USB1_IO_BASE 0x01c14000 +#define SUNXI_USB2_IO_BASE 0x01c1c000 + +#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 +#define SUNXI_USB_CSR 0x01c13404 +#define SUNXI_USB_PASSBY_EN 1 + +#define SUNXI_EHCI_AHB_ICHR8_EN BIT(10) +#define SUNXI_EHCI_AHB_INCR4_BURST_EN BIT(9) +#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN BIT(8) +#define SUNXI_EHCI_ULPI_BYPASS_EN BIT(0) + +static struct sunxi_ehci_hcd { + void *ehci_base; + struct usb_hcd *hcd; + int usb_rst_mask; + int ahb_clk_mask; + int gpio_vbus; + void *csr; + int irq; + int id; +} sunxi_echi_hcd[CONFIG_USB_MAX_CONTROLLER_COUNT] = { + [0] = { + .ehci_base = (void *) SUNXI_USB1_IO_BASE, + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST, + .ahb_clk_mask = BIT(AHB_GATE_OFFSET_USB_EHCI0), + .gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO, + .csr = (void*) SUNXI_USB_CSR, + .irq = 39, + .id = 1, + }, +#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) + [1] = { + .ehci_base = (void *) SUNXI_USB2_IO_BASE, + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST, + .ahb_clk_mask = BIT(AHB_GATE_OFFSET_USB_EHCI1), + .gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO, + .csr = (void*) SUNXI_USB_CSR, + .irq = 40, + .id = 2, + } +#endif +}; + +static int sunxi_gpio_output(u32 pin, u32 val) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + + dat = readl(&pio->dat); + if (val) + dat |= 0x1 << num; + else + dat &= ~(0x1 << num); + + writel(dat, &pio->dat); + + return 0; +} + +static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr, + int data, int len) +{ + int temp = 0, j = 0, usbc_bit = 0; + void *dest = sunxi_ehci->csr; + + usbc_bit = BIT(sunxi_ehci->id * 2); + for (j = 0; j < len; j++) { + /* set the bit address to be written */ + temp = readl(dest); + temp &= ~(0xff << 8); + temp |= ((addr + j) << 8); + writel(temp, dest); + + clrbits_le32(dest, usbc_bit); + /* set data bit */ + if (data & 0x1) + temp |= BIT(7); + else + temp &= ~BIT(7); + writeb(temp, dest); + + setbits_le32(dest, usbc_bit); + + clrbits_le32( dest, usbc_bit); + + data >>= 1; + } +} + +static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci) +{ + /* The following comments are machine + * translated from Chinese, you have been warned! + */ + + /* adjust PHY's magnitude and rate */ + usb_phy_write(sunxi_ehci, 0x20, 0x14, 5); + + /* threshold adjustment disconnect */ + usb_phy_write(sunxi_ehci, 0x2a, 3, 2); + + return; +} + +static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable) +{ + unsigned long reg_value = 0; + unsigned long bits = 0; + void *addr = sunxi_ehci->ehci_base + SUNXI_USB_PMU_IRQ_ENABLE; + + bits = SUNXI_EHCI_AHB_ICHR8_EN | + SUNXI_EHCI_AHB_INCR4_BURST_EN | + SUNXI_EHCI_AHB_INCRX_ALIGN_EN | + SUNXI_EHCI_ULPI_BYPASS_EN; + + + reg_value = readl(addr); + + if (enable) + reg_value |= bits; + else + reg_value &= ~bits; + + writel(reg_value, addr); + + return; +} + +static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); + setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); + + sunxi_usb_phy_init(sunxi_ehci); + + sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN); + + /* gpio_direction_output(sunxi_ehci->gpio_vbus, 1); */ + sunxi_gpio_set_cfgpin(sunxi_ehci->gpio_vbus, SUNXI_GPIO_OUTPUT); + sunxi_gpio_output(sunxi_ehci->gpio_vbus, 1); +} + +static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* gpio_direction_output(sunxi_ehci->gpio_vbus, 0); */ + sunxi_gpio_set_cfgpin(sunxi_ehci->gpio_vbus, SUNXI_GPIO_OUTPUT); + sunxi_gpio_output(sunxi_ehci->gpio_vbus, 0); + + sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN); + + clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); + clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); +} + +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index]; + + /* enable common PHY only once */ + if (index == 0) + setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + sunxi_ehci_enable(sunxi_ehci); + + *hccr = sunxi_ehci->ehci_base; + + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + return 0; +} + +int ehci_hcd_stop(int index) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index]; + + sunxi_ehci_disable(sunxi_ehci); + + /* disable common PHY only once, for the last hcd */ + if (index == CONFIG_USB_MAX_CONTROLLER_COUNT - 1) + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + return 0; +}
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c new file mode 100644 index 0000000..5817fc7 --- /dev/null +++ b/drivers/usb/host/ehci-sunxi.c @@ -0,0 +1,236 @@ +/*
- Copyright (C) 2014 arokux
- arokux arokux@gmail.com
The authorship info here contradicts the authorship suggested by the commit email metadata and the S-o-b.
If arokux wrote this patch then the commit message should begin with
From: Arokux X arokux@gmail.com
on the first line and arokux needs to have Signed-off on the patch.
I'm not sure what u-boot policy says about pseudonyms.
- Based on code from
- Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Please use the SPDX tag instead of the full license.
- dat = readl(&pio->dat);
- if (val)
dat |= 0x1 << num;- else
dat &= ~(0x1 << num);- writel(dat, &pio->dat);
This is if (val) setbits_le32(&pio->dat, 1<<num); else clrbits_le32(&pio->dat, 1<<num);
It seems like there are a bunch of similar constructs around the place.
- return 0;
+}
+static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
int data, int len)+{
- int temp = 0, j = 0, usbc_bit = 0;
- void *dest = sunxi_ehci->csr;
- usbc_bit = BIT(sunxi_ehci->id * 2);
- for (j = 0; j < len; j++) {
/* set the bit address to be written */temp = readl(dest);temp &= ~(0xff << 8);temp |= ((addr + j) << 8);writel(temp, dest);
clrsetbits?
clrbits_le32(dest, usbc_bit);/* set data bit */if (data & 0x1)temp |= BIT(7);elsetemp &= ~BIT(7);writeb(temp, dest);
AFAICT this will clobber the clearing of usbc_bit which you just did, since temp was read before that, is that right?
This should probably use the clr/setbits_le32 stuff and if it really is deliberately clobbering usbc_bit I think it needs a comment.
setbits_le32(dest, usbc_bit);clrbits_le32( dest, usbc_bit);
Extra space in this line.
- /* gpio_direction_output(sunxi_ehci->gpio_vbus, 1); */
???
+static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci) +{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- /* gpio_direction_output(sunxi_ehci->gpio_vbus, 0); */
???
Ian.
Signed-off-by: Roman Byshko rbyshko@gmail.com --- include/configs/sunxi-common.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62..c7746bb 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -181,6 +181,12 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #endif
+#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE +#endif + #if !defined CONFIG_ENV_IS_IN_MMC && \ !defined CONFIG_ENV_IS_IN_NAND && \ !defined CONFIG_ENV_IS_IN_FAT && \
Signed-off-by: Roman Byshko rbyshko@gmail.com --- include/configs/sun7i.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 9b693f7..0a1d83e 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -16,6 +16,14 @@
#define CONFIG_SYS_PROMPT "sun7i# "
+#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SUNXI_USB_VBUS0_GPIO 230 +#define CONFIG_SUNXI_USB_VBUS1_GPIO 227 +#endif + /* * Include common sunxi configuration where most the settings are */
Signed-off-by: Roman Byshko rbyshko@gmail.com --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/boards.cfg b/boards.cfg index f16a0e6..e039d4c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,7 +377,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga r.baldyga@samsung.com Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.kang@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII,USB_EHCI - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poirier@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
It was tested on Cubietruck. Now you could boot from a USB stick or use a compatible Ethernet dongle to add a second Ethernet port in U-Boot.
ehci-sunxi.c contains some code for poking GPIOs. This code will go away once some other patches for sunXi SoCs are applied against upstream. For now this patch series is self-contained and has no dependencies.
Which specific patches are required? http://patchwork.ozlabs.org/patch/356566/ Perhaps?
Ian.
On Sat, Jul 12, 2014 at 2:21 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
It was tested on Cubietruck. Now you could boot from a USB stick or use a compatible Ethernet dongle to add a second Ethernet port in U-Boot.
ehci-sunxi.c contains some code for poking GPIOs. This code will go away once some other patches for sunXi SoCs are applied against upstream. For now this patch series is self-contained and has no dependencies.
Which specific patches are required? http://patchwork.ozlabs.org/patch/356566/ Perhaps?
Yes, exactly.
Roman
On Tue, 2014-07-15 at 22:54 +0200, Roman B. wrote:
On Sat, Jul 12, 2014 at 2:21 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
You haven't done this in v2.
Ian.
On Wed, 2014-07-16 at 07:42 +0100, Ian Campbell wrote:
On Tue, 2014-07-15 at 22:54 +0200, Roman B. wrote:
On Sat, Jul 12, 2014 at 2:21 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
You haven't done this in v2.
NM, I see you followed up already to correct that mistake.
Ian.
On Wednesday, July 16, 2014 at 08:46:07 AM, Ian Campbell wrote:
On Wed, 2014-07-16 at 07:42 +0100, Ian Campbell wrote:
On Tue, 2014-07-15 at 22:54 +0200, Roman B. wrote:
On Sat, Jul 12, 2014 at 2:21 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
You haven't done this in v2.
NM, I see you followed up already to correct that mistake.
Where is the V2 ?
Best regards, Marek Vasut
On Wed, Jul 16, 2014 at 11:20 AM, Marek Vasut marex@denx.de wrote:
On Wednesday, July 16, 2014 at 08:46:07 AM, Ian Campbell wrote:
On Wed, 2014-07-16 at 07:42 +0100, Ian Campbell wrote:
On Tue, 2014-07-15 at 22:54 +0200, Roman B. wrote:
On Sat, Jul 12, 2014 at 2:21 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
This patch series adds USB Host EHCI support to the sun7i SoC.
When you repost this please could you CC the USB custodian (Marek Vasut, marex {AT} denx {DOT} de) for his input on the glue code.
You haven't done this in v2.
NM, I see you followed up already to correct that mistake.
Where is the V2 ?
It is here
http://lists.denx.de/pipermail/u-boot/2014-July/thread.html#183792
Best, Roman
participants (4)
-
Ian Campbell -
Marek Vasut -
Roman B. -
Roman Byshko