[U-Boot] [PATCH v2 00/10] mx7: add dt support for Colibri iMX7S/iMX7D

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[U-Boot] [PATCH 1/2] rockchip: add...

Stefan Agner

2 Aug 2016 2 Aug '16

7:50 a.m.

From: Stefan Agner stefan.agner@toradex.com

This patchset adds device tree support for Colibri iMX7S/iMX7D. It is the first device tree enabled board for any i.MX 7 SoC hence the patchset adds some common infrastructure: - Add device tree support for serial_mxc. - imx7.dtsi - I descided to leave the s/d suffix since the SoCs are very similar and boards will likely use runtime detection to distinguish the two available SoCs. - The pinmux file imx7d-pinfunc.h is taken from the Kernel and stored in the same place

Otherwise the conversion is quite straightforward and simplified the board code somewhat. Two patches enhance the board support with PMIC support, which has been the driver for this conversion.

Changes since v1: - Add Linux kernel commit hash for imx7d-pinfunc.h - Removed obsolete init declaration in PMIC header file - Rebased and added Acks

-- Stefan

Stefan Agner (10): dm: imx: serial: support device tree pinctrl: imx: do not announce driver initialization arm: dts: imx7: add pinctrl defines arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree colibri_imx7: remove legancy I2C support colibri_imx7: remove legancy UART platform data power: pmic: add Ricoh RN5T567 PMIC support arm: dts: imx7: add Ricoh RN5T567 PMIC node colibri_imx7: use Ricoh RN5T567 to reboot the board configs: enable device tree for Colibri iMX7

arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7-colibri.dts | 97 ++ arch/arm/dts/imx7.dtsi | 194 ++++ arch/arm/dts/imx7d-pinfunc.h | 1151 ++++++++++++++++++++++++ board/toradex/colibri_imx7/colibri_imx7.c | 92 +- configs/colibri_imx7_defconfig | 10 +- doc/device-tree-bindings/pmic/rn5t567.txt | 17 + doc/device-tree-bindings/serial/mxc-serial.txt | 8 + drivers/pinctrl/nxp/pinctrl-imx.c | 2 +- drivers/power/pmic/Kconfig | 8 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 ++ drivers/serial/serial_mxc.c | 28 +- include/configs/colibri_imx7.h | 3 +- include/power/rn5t567_pmic.h | 113 +++ 15 files changed, 1734 insertions(+), 56 deletions(-) create mode 100644 arch/arm/dts/imx7-colibri.dts create mode 100644 arch/arm/dts/imx7.dtsi create mode 100644 arch/arm/dts/imx7d-pinfunc.h create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 doc/device-tree-bindings/serial/mxc-serial.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/power/rn5t567_pmic.h

-- 2.9.0

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Stefan Agner

2 Aug 2 Aug

7:50 a.m.

New subject: [U-Boot] [PATCH v2 01/10] dm: imx: serial: support device tree

From: Stefan Agner stefan.agner@toradex.com

Support instatiation through device tree. Also parse the fsl,dte-mode property to determine whether DTE mode shall be used.

Signed-off-by: Stefan Agner stefan.agner@toradex.com Reviewed-by: Simon Glass sjg@chromium.org ---

doc/device-tree-bindings/serial/mxc-serial.txt | 8 ++++++++ drivers/serial/serial_mxc.c | 28 ++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 doc/device-tree-bindings/serial/mxc-serial.txt

diff --git a/doc/device-tree-bindings/serial/mxc-serial.txt b/doc/device-tree-bindings/serial/mxc-serial.txt new file mode 100644 index 0000000..ede92a4 --- /dev/null +++ b/doc/device-tree-bindings/serial/mxc-serial.txt @@ -0,0 +1,8 @@ +NXP i.MX (MXC) UART + +Required properties: +- compatible: must be "fsl,imx7d-uart" +- reg: start address and size of the registers + +Optional properties: +- fsl,dte-mode: use DTE mode diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 8545714..d645bcf 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -108,6 +108,8 @@ #define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */

+DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_DM_SERIAL

#ifndef CONFIG_MXC_UART_BASE @@ -135,8 +137,6 @@ #define UBRC 0xac /* Baud Rate Count Register */ #define UTS 0xb4 /* UART Test Register (mx31) */

-DECLARE_GLOBAL_DATA_PTR; - #define TXTL 2 /* reset default */ #define RXTL 1 /* reset default */ #define RFDIV 4 /* divide input clock by 2 */ @@ -347,9 +347,33 @@ static const struct dm_serial_ops mxc_serial_ops = { .setbrg = mxc_serial_setbrg, };

+static int mxc_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct mxc_serial_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = (struct mxc_uart *)addr; + + plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "fsl,dte-mode"); + return 0; +} + +static const struct udevice_id mxc_serial_ids[] = { + { .compatible = "fsl,imx7d-uart" }, + { } +}; + U_BOOT_DRIVER(serial_mxc) = { .name = "serial_mxc", .id = UCLASS_SERIAL, + .of_match = mxc_serial_ids, + .ofdata_to_platdata = mxc_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata), .probe = mxc_serial_probe, .ops = &mxc_serial_ops, .flags = DM_FLAG_PRE_RELOC,

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 02/10] pinctrl: imx: do not announce driver initialization

From: Stefan Agner stefan.agner@toradex.com

It is not usual that drivers announce when they have been initialized. use dev_dbg to announce device initialization.

Signed-off-by: Stefan Agner stefan.agner@toradex.com Reviewed-by: Simon Glass sjg@chromium.org ---

drivers/pinctrl/nxp/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 40b0616..949d0f3 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -222,7 +222,7 @@ int imx_pinctrl_probe(struct udevice *dev, return -ENOMEM; }

- dev_info(dev, "initialized IMX pinctrl driver\n"); + dev_dbg(dev, "initialized IMX pinctrl driver\n");

return 0; }

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 03/10] arm: dts: imx7: add pinctrl defines

From: Stefan Agner stefan.agner@toradex.com

Add pinctrl defines for NXP i.MX 7Solo/7Dual SoC. The pinctrl format is compatible to the Linux kernel, hence this file is a simple copy from the Linux kernel (commit 97f5c1817b7e).

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

arch/arm/dts/imx7d-pinfunc.h | 1151 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1151 insertions(+) create mode 100644 arch/arm/dts/imx7d-pinfunc.h

diff --git a/arch/arm/dts/imx7d-pinfunc.h new file mode 100644 index 0000000..32d2464 --- /dev/null +++ b/arch/arm/dts/imx7d-pinfunc.h @@ -0,0 +1,1151 @@ +/* + * Copyright (C) 2014-2015 Freescale + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DTS_IMX7D_PINFUNC_H +#define __DTS_IMX7D_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg + */ + +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA +#define MX7D_PAD_GPIO1_IO07__CCM_STOP +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL +#define MX7D_PAD_GPIO1_IO08__KPP_COL5 +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA +#define MX7D_PAD_GPIO1_IO10__KPP_COL6 +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX +#define MX7D_PAD_GPIO1_IO12__CM4_NMI +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 +#define MX7D_PAD_GPIO1_IO15__SD3_WP +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 +#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 +#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD +#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 +#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 +#define MX7D_PAD_EPDC_DATA00__EIM_AD0 +#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 +#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 +#define MX7D_PAD_EPDC_DATA00__LCD_CLK +#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 +#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK +#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 +#define MX7D_PAD_EPDC_DATA01__KPP_COL3 +#define MX7D_PAD_EPDC_DATA01__EIM_AD1 +#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 +#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 +#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE +#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 +#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B +#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 +#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 +#define MX7D_PAD_EPDC_DATA02__EIM_AD2 +#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 +#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 +#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC +#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 +#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN +#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 +#define MX7D_PAD_EPDC_DATA03__KPP_COL2 +#define MX7D_PAD_EPDC_DATA03__EIM_AD3 +#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 +#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 +#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC +#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 +#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD +#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS +#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 +#define MX7D_PAD_EPDC_DATA04__EIM_AD4 +#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 +#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 +#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL +#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 +#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD +#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK +#define MX7D_PAD_EPDC_DATA05__KPP_COL1 +#define MX7D_PAD_EPDC_DATA05__EIM_AD5 +#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 +#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 +#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE +#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 +#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK +#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B +#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 +#define MX7D_PAD_EPDC_DATA06__EIM_AD6 +#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 +#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 +#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B +#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 +#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B +#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B +#define MX7D_PAD_EPDC_DATA07__KPP_COL0 +#define MX7D_PAD_EPDC_DATA07__EIM_AD7 +#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 +#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 +#define MX7D_PAD_EPDC_DATA07__JTAG_DONE +#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 +#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD +#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 +#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX +#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX +#define MX7D_PAD_EPDC_DATA08__EIM_OE +#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 +#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 +#define MX7D_PAD_EPDC_DATA08__LCD_BUSY +#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK +#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 +#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK +#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 +#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX +#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX +#define MX7D_PAD_EPDC_DATA09__EIM_RW +#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 +#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE +#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 +#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B +#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 +#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS +#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS +#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B +#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 +#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE +#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 +#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN +#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 +#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS +#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS +#define MX7D_PAD_EPDC_DATA11__EIM_BCLK +#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 +#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 +#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 +#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD +#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS +#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX +#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX +#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B +#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 +#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK +#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 +#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD +#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK +#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX +#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX +#define MX7D_PAD_EPDC_DATA13__EIM_WAIT +#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 +#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 +#define MX7D_PAD_EPDC_DATA13__LCD_CS +#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE +#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 +#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK +#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B +#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS +#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS +#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 +#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 +#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP +#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 +#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B +#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B +#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS +#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS +#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B +#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 +#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 +#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN +#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM +#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK +#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN +#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 +#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 +#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 +#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 +#define MX7D_PAD_EPDC_SDCLK__LCD_CLK +#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 +#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE +#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD +#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 +#define MX7D_PAD_EPDC_SDLE__KPP_COL4 +#define MX7D_PAD_EPDC_SDLE__EIM_AD11 +#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 +#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE +#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 +#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 +#define MX7D_PAD_EPDC_SDOE__KPP_COL5 +#define MX7D_PAD_EPDC_SDOE__EIM_AD12 +#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 +#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR +#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 +#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 +#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 +#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 +#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 +#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 +#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 +#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL +#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 +#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 +#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 +#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC +#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER +#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 +#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 +#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 +#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN +#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 +#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 +#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 +#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 +#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 +#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD +#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 +#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 +#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 +#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 +#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK +#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 +#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 +#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 +#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 +#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 +#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE +#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 +#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 +#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 +#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 +#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 +#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN +#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 +#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL +#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 +#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL +#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 +#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 +#define MX7D_PAD_EPDC_GDRL__LCD_RD_E +#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 +#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP +#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 +#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC +#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER +#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 +#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 +#define MX7D_PAD_EPDC_GDSP__LCD_BUSY +#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 +#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 +#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK +#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 +#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 +#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 +#define MX7D_PAD_EPDC_BDR0__LCD_CS +#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 +#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 +#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN +#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK +#define MX7D_PAD_EPDC_BDR1__EIM_AD8 +#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 +#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE +#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 +#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM +#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA +#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS +#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 +#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 +#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC +#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 +#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT +#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB +#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL +#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 +#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC +#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 +#define MX7D_PAD_LCD_CLK__LCD_CLK +#define MX7D_PAD_LCD_CLK__ECSPI4_MISO +#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN +#define MX7D_PAD_LCD_CLK__CSI_DATA16 +#define MX7D_PAD_LCD_CLK__UART2_DCE_RX +#define MX7D_PAD_LCD_CLK__UART2_DTE_TX +#define MX7D_PAD_LCD_CLK__GPIO3_IO0 +#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE +#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI +#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN +#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 +#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX +#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX +#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 +#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC +#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK +#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN +#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 +#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS +#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS +#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 +#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC +#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 +#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN +#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 +#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS +#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS +#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 +#define MX7D_PAD_LCD_RESET__LCD_RESET +#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 +#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI +#define MX7D_PAD_LCD_RESET__CSI_FIELD +#define MX7D_PAD_LCD_RESET__EIM_DTACK_B +#define MX7D_PAD_LCD_RESET__GPIO3_IO4 +#define MX7D_PAD_LCD_DATA00__LCD_DATA0 +#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 +#define MX7D_PAD_LCD_DATA00__CSI_DATA20 +#define MX7D_PAD_LCD_DATA00__EIM_DATA0 +#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 +#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 +#define MX7D_PAD_LCD_DATA01__LCD_DATA1 +#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 +#define MX7D_PAD_LCD_DATA01__CSI_DATA21 +#define MX7D_PAD_LCD_DATA01__EIM_DATA1 +#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 +#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 +#define MX7D_PAD_LCD_DATA02__LCD_DATA2 +#define MX7D_PAD_LCD_DATA02__GPT1_CLK +#define MX7D_PAD_LCD_DATA02__CSI_DATA22 +#define MX7D_PAD_LCD_DATA02__EIM_DATA2 +#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 +#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 +#define MX7D_PAD_LCD_DATA03__LCD_DATA3 +#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 +#define MX7D_PAD_LCD_DATA03__CSI_DATA23 +#define MX7D_PAD_LCD_DATA03__EIM_DATA3 +#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 +#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 +#define MX7D_PAD_LCD_DATA04__LCD_DATA4 +#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 +#define MX7D_PAD_LCD_DATA04__CSI_VSYNC +#define MX7D_PAD_LCD_DATA04__EIM_DATA4 +#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 +#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 +#define MX7D_PAD_LCD_DATA05__LCD_DATA5 +#define MX7D_PAD_LCD_DATA05__CSI_HSYNC +#define MX7D_PAD_LCD_DATA05__EIM_DATA5 +#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 +#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 +#define MX7D_PAD_LCD_DATA06__LCD_DATA6 +#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK +#define MX7D_PAD_LCD_DATA06__EIM_DATA6 +#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 +#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 +#define MX7D_PAD_LCD_DATA07__LCD_DATA7 +#define MX7D_PAD_LCD_DATA07__CSI_MCLK +#define MX7D_PAD_LCD_DATA07__EIM_DATA7 +#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 +#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 +#define MX7D_PAD_LCD_DATA08__LCD_DATA8 +#define MX7D_PAD_LCD_DATA08__CSI_DATA9 +#define MX7D_PAD_LCD_DATA08__EIM_DATA8 +#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 +#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 +#define MX7D_PAD_LCD_DATA09__LCD_DATA9 +#define MX7D_PAD_LCD_DATA09__CSI_DATA8 +#define MX7D_PAD_LCD_DATA09__EIM_DATA9 +#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 +#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 +#define MX7D_PAD_LCD_DATA10__LCD_DATA10 +#define MX7D_PAD_LCD_DATA10__CSI_DATA7 +#define MX7D_PAD_LCD_DATA10__EIM_DATA10 +#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 +#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 +#define MX7D_PAD_LCD_DATA11__LCD_DATA11 +#define MX7D_PAD_LCD_DATA11__CSI_DATA6 +#define MX7D_PAD_LCD_DATA11__EIM_DATA11 +#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 +#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 +#define MX7D_PAD_LCD_DATA12__LCD_DATA12 +#define MX7D_PAD_LCD_DATA12__CSI_DATA5 +#define MX7D_PAD_LCD_DATA12__EIM_DATA12 +#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 +#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 +#define MX7D_PAD_LCD_DATA13__LCD_DATA13 +#define MX7D_PAD_LCD_DATA13__CSI_DATA4 +#define MX7D_PAD_LCD_DATA13__EIM_DATA13 +#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 +#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 +#define MX7D_PAD_LCD_DATA14__LCD_DATA14 +#define MX7D_PAD_LCD_DATA14__CSI_DATA3 +#define MX7D_PAD_LCD_DATA14__EIM_DATA14 +#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 +#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 +#define MX7D_PAD_LCD_DATA15__LCD_DATA15 +#define MX7D_PAD_LCD_DATA15__CSI_DATA2 +#define MX7D_PAD_LCD_DATA15__EIM_DATA15 +#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 +#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 +#define MX7D_PAD_LCD_DATA16__LCD_DATA16 +#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 +#define MX7D_PAD_LCD_DATA16__CSI_DATA1 +#define MX7D_PAD_LCD_DATA16__EIM_CRE +#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 +#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 +#define MX7D_PAD_LCD_DATA17__LCD_DATA17 +#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 +#define MX7D_PAD_LCD_DATA17__CSI_DATA0 +#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN +#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 +#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 +#define MX7D_PAD_LCD_DATA18__LCD_DATA18 +#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 +#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO +#define MX7D_PAD_LCD_DATA18__CSI_DATA15 +#define MX7D_PAD_LCD_DATA18__EIM_CS2_B +#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 +#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 +#define MX7D_PAD_LCD_DATA19__EIM_CS3_B +#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 +#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 +#define MX7D_PAD_LCD_DATA19__LCD_DATA19 +#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 +#define MX7D_PAD_LCD_DATA19__CSI_DATA14 +#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 +#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 +#define MX7D_PAD_LCD_DATA20__I2C3_SCL +#define MX7D_PAD_LCD_DATA20__LCD_DATA20 +#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 +#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT +#define MX7D_PAD_LCD_DATA20__CSI_DATA13 +#define MX7D_PAD_LCD_DATA21__LCD_DATA21 +#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 +#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT +#define MX7D_PAD_LCD_DATA21__CSI_DATA12 +#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 +#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 +#define MX7D_PAD_LCD_DATA21__I2C3_SDA +#define MX7D_PAD_LCD_DATA22__LCD_DATA22 +#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 +#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT +#define MX7D_PAD_LCD_DATA22__CSI_DATA11 +#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 +#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 +#define MX7D_PAD_LCD_DATA22__I2C4_SCL +#define MX7D_PAD_LCD_DATA23__LCD_DATA23 +#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 +#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT +#define MX7D_PAD_LCD_DATA23__CSI_DATA10 +#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 +#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 +#define MX7D_PAD_LCD_DATA23__I2C4_SDA +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX +#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX +#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL +#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY +#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 +#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN +#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 +#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO +#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX +#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX +#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA +#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK +#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 +#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT +#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 +#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX +#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX +#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK +#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 +#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN +#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO +#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX +#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA +#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 +#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY +#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT +#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 +#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC +#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX +#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX +#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC +#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC +#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO +#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN +#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 +#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL +#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX +#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX +#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR +#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK +#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI +#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT +#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 +#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS +#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS +#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC +#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 +#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK +#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN +#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 +#define MX7D_PAD_UART3_RTS_B__SD3_LCTL +#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS +#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS +#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR +#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC +#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 +#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT +#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 +#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT +#define MX7D_PAD_I2C1_SCL__I2C1_SCL +#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS +#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS +#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX +#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO +#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 +#define MX7D_PAD_I2C1_SCL__SD2_VSELECT +#define MX7D_PAD_I2C1_SDA__I2C1_SDA +#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS +#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS +#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX +#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI +#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 +#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 +#define MX7D_PAD_I2C1_SDA__SD3_VSELECT +#define MX7D_PAD_I2C2_SCL__I2C2_SCL +#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX +#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX +#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B +#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK +#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 +#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 +#define MX7D_PAD_I2C2_SCL__SD3_CD_B +#define MX7D_PAD_I2C2_SDA__I2C2_SDA +#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX +#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX +#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB +#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 +#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 +#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 +#define MX7D_PAD_I2C2_SDA__SD3_WP +#define MX7D_PAD_I2C3_SCL__I2C3_SCL +#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS +#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS +#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX +#define MX7D_PAD_I2C3_SCL__CSI_VSYNC +#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 +#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 +#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 +#define MX7D_PAD_I2C3_SDA__I2C3_SDA +#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS +#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS +#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX +#define MX7D_PAD_I2C3_SDA__CSI_HSYNC +#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 +#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 +#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 +#define MX7D_PAD_I2C4_SCL__I2C4_SCL +#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX +#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX +#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B +#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK +#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID +#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 +#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 +#define MX7D_PAD_I2C4_SDA__I2C4_SDA +#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX +#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX +#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB +#define MX7D_PAD_I2C4_SDA__CSI_MCLK +#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID +#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 +#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 +#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK +#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX +#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX +#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 +#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 +#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 +#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM +#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI +#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX +#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX +#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 +#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 +#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 +#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT +#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO +#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS +#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS +#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 +#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 +#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 +#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ +#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 +#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS +#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS +#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 +#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 +#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 +#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 +#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK +#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX +#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX +#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 +#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 +#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 +#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 +#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 +#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI +#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX +#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX +#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 +#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 +#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 +#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 +#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 +#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 +#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 +#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO +#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS +#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS +#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 +#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 +#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 +#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS +#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS +#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 +#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 +#define MX7D_PAD_ECSPI2_SS0__LCD_RESET +#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 +#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE +#define MX7D_PAD_SD1_CD_B__SD1_CD_B +#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX +#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX +#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO +#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 +#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 +#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 +#define MX7D_PAD_SD1_WP__SD1_WP +#define MX7D_PAD_SD1_WP__UART6_DCE_TX +#define MX7D_PAD_SD1_WP__UART6_DTE_RX +#define MX7D_PAD_SD1_WP__ECSPI4_MOSI +#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 +#define MX7D_PAD_SD1_WP__GPIO5_IO1 +#define MX7D_PAD_SD1_WP__CCM_CLKO2 +#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B +#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK +#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS +#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS +#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK +#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 +#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 +#define MX7D_PAD_SD1_CLK__SD1_CLK +#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC +#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS +#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS +#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 +#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 +#define MX7D_PAD_SD1_CLK__GPIO5_IO3 +#define MX7D_PAD_SD1_CMD__SD1_CMD +#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK +#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 +#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 +#define MX7D_PAD_SD1_CMD__GPIO5_IO4 +#define MX7D_PAD_SD1_DATA0__SD1_DATA0 +#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 +#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX +#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX +#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 +#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 +#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 +#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 +#define MX7D_PAD_SD1_DATA1__SD1_DATA1 +#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK +#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX +#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX +#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 +#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 +#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 +#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 +#define MX7D_PAD_SD1_DATA2__SD1_DATA2 +#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC +#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS +#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS +#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY +#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 +#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 +#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 +#define MX7D_PAD_SD1_DATA3__SD1_DATA3 +#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 +#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS +#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS +#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 +#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA +#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 +#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 +#define MX7D_PAD_SD2_CD_B__SD2_CD_B +#define MX7D_PAD_SD2_CD_B__ENET1_MDIO +#define MX7D_PAD_SD2_CD_B__ENET2_MDIO +#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 +#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB +#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 +#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 +#define MX7D_PAD_SD2_WP__SD2_WP +#define MX7D_PAD_SD2_WP__ENET1_MDC +#define MX7D_PAD_SD2_WP__ENET2_MDC +#define MX7D_PAD_SD2_WP__ECSPI3_SS3 +#define MX7D_PAD_SD2_WP__USB_OTG1_ID +#define MX7D_PAD_SD2_WP__GPIO5_IO10 +#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B +#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK +#define MX7D_PAD_SD2_RESET_B__SD2_RESET +#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY +#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID +#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 +#define MX7D_PAD_SD2_CLK__SD2_CLK +#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC +#define MX7D_PAD_SD2_CLK__MQS_RIGHT +#define MX7D_PAD_SD2_CLK__GPT4_CLK +#define MX7D_PAD_SD2_CLK__GPIO5_IO12 +#define MX7D_PAD_SD2_CMD__SD2_CMD +#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK +#define MX7D_PAD_SD2_CMD__MQS_LEFT +#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 +#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD +#define MX7D_PAD_SD2_CMD__GPIO5_IO13 +#define MX7D_PAD_SD2_DATA0__SD2_DATA0 +#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 +#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX +#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX +#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 +#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK +#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 +#define MX7D_PAD_SD2_DATA1__SD2_DATA1 +#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK +#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX +#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX +#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 +#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B +#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 +#define MX7D_PAD_SD2_DATA2__SD2_DATA2 +#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC +#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS +#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS +#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 +#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN +#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 +#define MX7D_PAD_SD2_DATA3__SD2_DATA3 +#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 +#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS +#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS +#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 +#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD +#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 +#define MX7D_PAD_SD3_CLK__SD3_CLK +#define MX7D_PAD_SD3_CLK__NAND_CLE +#define MX7D_PAD_SD3_CLK__ECSPI4_MISO +#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC +#define MX7D_PAD_SD3_CLK__GPT3_CLK +#define MX7D_PAD_SD3_CLK__GPIO6_IO0 +#define MX7D_PAD_SD3_CMD__SD3_CMD +#define MX7D_PAD_SD3_CMD__NAND_ALE +#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI +#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK +#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 +#define MX7D_PAD_SD3_CMD__GPIO6_IO1 +#define MX7D_PAD_SD3_DATA0__SD3_DATA0 +#define MX7D_PAD_SD3_DATA0__NAND_DATA00 +#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 +#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 +#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 +#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 +#define MX7D_PAD_SD3_DATA1__SD3_DATA1 +#define MX7D_PAD_SD3_DATA1__NAND_DATA01 +#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK +#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK +#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 +#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 +#define MX7D_PAD_SD3_DATA2__SD3_DATA2 +#define MX7D_PAD_SD3_DATA2__NAND_DATA02 +#define MX7D_PAD_SD3_DATA2__I2C3_SDA +#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC +#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 +#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 +#define MX7D_PAD_SD3_DATA3__SD3_DATA3 +#define MX7D_PAD_SD3_DATA3__NAND_DATA03 +#define MX7D_PAD_SD3_DATA3__I2C3_SCL +#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 +#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 +#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 +#define MX7D_PAD_SD3_DATA4__SD3_DATA4 +#define MX7D_PAD_SD3_DATA4__NAND_DATA04 +#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX +#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX +#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX +#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 +#define MX7D_PAD_SD3_DATA5__SD3_DATA5 +#define MX7D_PAD_SD3_DATA5__NAND_DATA05 +#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX +#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX +#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX +#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 +#define MX7D_PAD_SD3_DATA6__SD3_DATA6 +#define MX7D_PAD_SD3_DATA6__NAND_DATA06 +#define MX7D_PAD_SD3_DATA6__SD3_WP +#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS +#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS +#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX +#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 +#define MX7D_PAD_SD3_DATA7__SD3_DATA7 +#define MX7D_PAD_SD3_DATA7__NAND_DATA07 +#define MX7D_PAD_SD3_DATA7__SD3_CD_B +#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS +#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS +#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX +#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 +#define MX7D_PAD_SD3_STROBE__SD3_STROBE +#define MX7D_PAD_SD3_STROBE__NAND_RE_B +#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B +#define MX7D_PAD_SD3_RESET_B__NAND_WE_B +#define MX7D_PAD_SD3_RESET_B__SD3_RESET +#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK +#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 +#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 +#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B +#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX +#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX +#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX +#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD +#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 +#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET +#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK +#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX +#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX +#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK +#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 +#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET +#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC +#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS +#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX +#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B +#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 +#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT +#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 +#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B +#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS +#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS +#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX +#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN +#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 +#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET +#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC +#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B +#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC +#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL +#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD +#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 +#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT +#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK +#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B +#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK +#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA +#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA +#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 +#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT +#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 +#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK +#define MX7D_PAD_SAI1_MCLK__NAND_WP_B +#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK +#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY +#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB +#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 +#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK +#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC +#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS +#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 +#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 +#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK +#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS +#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 +#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 +#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 +#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK +#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS +#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS +#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS +#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS +#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 +#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 +#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 +#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 +#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS +#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS +#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS +#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS +#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 +#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 +#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 +#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 +#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT +#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS +#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 +#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 +#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 +#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 +#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT +#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS +#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 +#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 +#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 +#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 +#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX +#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX +#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 +#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 +#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 +#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 +#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX +#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX +#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 +#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 +#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENE +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER +#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 +#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 +#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 +#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 +#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 +#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT +#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 +#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 +#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 +#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 +#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 +#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT +#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY +#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 +#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 +#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 +#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 +#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX +#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO +#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL +#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED +#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 +#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 +#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX +#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 +#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA +#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ +#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 +#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS +#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENE +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK +#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 +#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 +#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 +#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK +#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 +#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 +#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 +#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ +#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 +#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 +#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 +#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK +#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B +#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK +#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK +#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE +#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 +#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 +#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 +#define MX7D_PAD_ENET1_CRS__ENET1_CRS +#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB +#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC +#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 +#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 +#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 +#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 +#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 +#define MX7D_PAD_ENET1_COL__ENET1_COL +#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY +#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 +#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 +#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 +#define MX7D_PAD_ENET1_COL__GPIO7_IO15 +#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 +#define MX7D_PAD_ENET1_COL__CSU_INT_DEB + +#endif /* __DTS_IMX7D_PINFUNC_H */ b/arch/arm/dts/imx7d-pinfunc.h Semiconductor, Inc. mux_mode input_val> 0x0000 0x0030 0x0000 0x0 0x0 0x0000 0x0030 0x0000 0x1 0x0 0x0000 0x0030 0x0000 0x2 0x0 0x0000 0x0030 0x0000 0x3 0x0 0x0000 0x0030 0x0000 0x4 0x0 0x0004 0x0034 0x0000 0x0 0x0 0x0004 0x0034 0x0000 0x1 0x0 0x0004 0x0034 0x0000 0x2 0x0 0x0004 0x0034 0x0000 0x3 0x0 0x0004 0x0034 0x0000 0x4 0x0 0x0004 0x0034 0x0000 0x6 0x0 0x0008 0x0038 0x0000 0x0 0x0 0x0008 0x0038 0x0000 0x1 0x0 0x0008 0x0038 0x0564 0x2 0x3 0x0008 0x0038 0x0000 0x3 0x0 0x0008 0x0038 0x0000 0x5 0x0 0x0008 0x0038 0x0000 0x6 0x0 0x0008 0x0038 0x0734 0x7 0x3 0x000C 0x003C 0x0000 0x0 0x0 0x000C 0x003C 0x0000 0x1 0x0 0x000C 0x003C 0x0570 0x2 0x3 0x000C 0x003C 0x0000 0x3 0x0 0x000C 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-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 04/10] arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree

From: Stefan Agner stefan.agner@toradex.com

Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very similar and hence can share the same device tree for boot loaders purpose.

Signed-off-by: Stefan Agner stefan.agner@toradex.com Reviewed-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7-colibri.dts | 92 ++++++++++++++++++++ arch/arm/dts/imx7.dtsi | 194 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 arch/arm/dts/imx7-colibri.dts create mode 100644 arch/arm/dts/imx7.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7e21083..792dd0f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -262,6 +262,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-twr.dtb \ pcm052.dtb

+dtb-$(CONFIG_MX7) += imx7-colibri.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ k2e-evm.dtb \ diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts new file mode 100644 index 0000000..f2da096 --- /dev/null +++ b/arch/arm/dts/imx7-colibri.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx7.dtsi" + +/ { + model = "Toradex Colibri iMX7S/D"; + compatible = "toradex,imx7-colibri", "fsl,imx7"; + + chosen { + stdout-path = &uart1; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + fsl,pins = < + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f + >; + }; +}; diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi new file mode 100644 index 0000000..755cc46 --- /dev/null +++ b/arch/arm/dts/imx7.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + status = "disabled"; + }; + }; + }; +};

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 05/10] colibri_imx7: remove legancy I2C support

From: Stefan Agner stefan.agner@toradex.com

Remove legancy I2C config and code in favor of upcomming DM/DT enable I2C support.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

board/toradex/colibri_imx7/colibri_imx7.c | 40 ------------------------------- include/configs/colibri_imx7.h | 2 -- 2 files changed, 42 deletions(-)

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 8eedd65..ddb3085 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -12,13 +12,11 @@ #include <asm/gpio.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/iomux-v3.h> -#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <fsl_esdhc.h> -#include <i2c.h> #include <linux/sizes.h> #include <mmc.h> #include <miiphy.h> @@ -38,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;

#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

@@ -48,36 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;

#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

-#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC, - .gp = IMX_GPIO_NR(1, 4), - }, - .sda = { - .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC, - .gp = IMX_GPIO_NR(1, 5), - }, -}; -/* I2C4 for Colibri I2C */ -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC, - .gp = IMX_GPIO_NR(7, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC, - .gp = IMX_GPIO_NR(7, 9), - }, -}; -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -331,11 +296,6 @@ int board_early_init_f(void) { setup_iomux_uart();

-#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); -#endif - return 0; }

diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 9da219c..32b6101 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -59,9 +59,7 @@ #undef CONFIG_BOOTM_RTEMS

/* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000

#define CONFIG_IPADDR 192.168.10.2

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 06/10] colibri_imx7: remove legancy UART platform data

From: Stefan Agner stefan.agner@toradex.com

We now use device tree to provide SoC data to the UART driver, there is no need for the legancy UART platform data.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

board/toradex/colibri_imx7/colibri_imx7.c | 10 ---------- 1 file changed, 10 deletions(-)

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index ddb3085..bd7d5bc 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -368,13 +368,3 @@ int board_ehci_hcd_init(int port) return 0; } #endif - -static struct mxc_serial_platdata mxc_serial_plat = { - .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR, - .use_dte = true, -}; - -U_BOOT_DEVICE(mxc_serial) = { - .name = "serial_mxc", - .platdata = &mxc_serial_plat, -};

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 07/10] power: pmic: add Ricoh RN5T567 PMIC support

From: Stefan Agner stefan.agner@toradex.com

Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7.

Signed-off-by: Stefan Agner stefan.agner@toradex.com Reviewed-by: Simon Glass sjg@chromium.org ---

doc/device-tree-bindings/pmic/rn5t567.txt | 17 +++++ drivers/power/pmic/Kconfig | 8 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 +++++++++++++++++ include/power/rn5t567_pmic.h | 113 ++++++++++++++++++++++++++++++ 5 files changed, 203 insertions(+) create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/power/rn5t567_pmic.h

diff --git a/doc/device-tree-bindings/pmic/rn5t567.txt b/doc/device-tree-bindings/pmic/rn5t567.txt new file mode 100644 index 0000000..e9e6885 --- /dev/null +++ b/doc/device-tree-bindings/pmic/rn5t567.txt @@ -0,0 +1,17 @@ +Ricoh RN5T567 PMIC + +This file describes the binding info for the PMIC driver. + +Required properties: +- compatible: "ricoh,rn5t567" +- reg: depending on strapping, e.g. 0x33 + +With those two properties, the PMIC device can be used to read/write +registers. + +Example: + +rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; +}; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 69f8d51..13d293a 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -127,6 +127,14 @@ config PMIC_S5M8767 driver provides basic register access and sets up the attached regulators if regulator support is enabled.

+config PMIC_RN5T567 + bool "Enable driver for Ricoh RN5T567 PMIC" + depends on DM_PMIC + ---help--- + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. + config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 52b4f71..37d9eb5 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_PMIC_RK808) += rk808.o +obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c new file mode 100644 index 0000000..001e695 --- /dev/null +++ b/drivers/power/pmic/rn5t567.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner stefan.agner@toradex.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <power/rn5t567_pmic.h> +#include <power/pmic.h> + +static int rn5t567_reg_count(struct udevice *dev) +{ + return RN5T567_NUM_OF_REGS; +} + +static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + debug("write error to device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + debug("read error from device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static struct dm_pmic_ops rn5t567_ops = { + .reg_count = rn5t567_reg_count, + .read = rn5t567_read, + .write = rn5t567_write, +}; + +static const struct udevice_id rn5t567_ids[] = { + { .compatible = "ricoh,rn5t567" }, + { } +}; + +U_BOOT_DRIVER(pmic_rn5t567) = { + .name = "rn5t567 pmic", + .id = UCLASS_PMIC, + .of_match = rn5t567_ids, + .ops = &rn5t567_ops, +}; diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h new file mode 100644 index 0000000..9ce601f --- /dev/null +++ b/include/power/rn5t567_pmic.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner stefan.agner@toradex.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __RN5T567_PMIC_H_ +#define __RN5T567_PMIC_H_ + +/* RN5T567 registers */ +enum { + RN5T567_LSIVER = 0x00, + RN5T567_OTPVER = 0x01, + RN5T567_IODAC = 0x02, + RN5T567_VINDAC = 0x03, + RN5T567_OUT32KEN = 0x05, + + RN5T567_CPUCNT = 0x06, + + RN5T567_PSWR = 0x07, + RN5T567_PONHIS = 0x09, + RN5T567_POFFHIS = 0x0A, + RN5T567_WATCHDOG = 0x0B, + RN5T567_WATCHDOGCNT = 0x0C, + RN5T567_PWRFUNC = 0x0D, + RN5T567_SLPCNT = 0x0E, + RN5T567_REPCNT = 0x0F, + RN5T567_PWRONTIMSET = 0x10, + RN5T567_NOETIMSETCNT = 0x11, + RN5T567_PWRIREN = 0x12, + RN5T567_PWRIRQ = 0x13, + RN5T567_PWRMON = 0x14, + RN5T567_PWRIRSEL = 0x15, + + RN5T567_DC1_SLOT = 0x16, + RN5T567_DC2_SLOT = 0x17, + RN5T567_DC3_SLOT = 0x18, + RN5T567_DC4_SLOT = 0x19, + + RN5T567_LDO1_SLOT = 0x1B, + RN5T567_LDO2_SLOT = 0x1C, + RN5T567_LDO3_SLOT = 0x1D, + RN5T567_LDO4_SLOT = 0x1E, + RN5T567_LDO5_SLOT = 0x1F, + + RN5T567_PSO0_SLOT = 0x25, + RN5T567_PSO1_SLOT = 0x26, + RN5T567_PSO2_SLOT = 0x27, + RN5T567_PSO3_SLOT = 0x28, + + RN5T567_LDORTC1_SLOT = 0x2A, + + RN5T567_DC1CTL = 0x2C, + RN5T567_DC1CTL2 = 0x2D, + RN5T567_DC2CTL = 0x2E, + RN5T567_DC2CTL2 = 0x2F, + RN5T567_DC3CTL = 0x30, + RN5T567_DC3CTL2 = 0x31, + RN5T567_DC4CTL = 0x32, + RN5T567_DC4CTL2 = 0x33, + + RN5T567_DC1DAC = 0x36, + RN5T567_DC2DAC = 0x37, + RN5T567_DC3DAC = 0x38, + RN5T567_DC4DAC = 0x39, + + RN5T567_DC1DAC_SLP = 0x3B, + RN5T567_DC2DAC_SLP = 0x3C, + RN5T567_DC3DAC_SLP = 0x3D, + RN5T567_DC4DAC_SLP = 0x3E, + + RN5T567_DCIREN = 0x40, + RN5T567_DCIRQ = 0x41, + RN5T567_DCIRMON = 0x42, + + RN5T567_LDOEN1 = 0x44, + RN5T567_LDOEN2 = 0x45, + RN5T567_LDODIS1 = 0x46, + + RN5T567_LDO1DAC = 0x4C, + RN5T567_LDO2DAC = 0x4D, + RN5T567_LDO3DAC = 0x4E, + RN5T567_LDO4DAC = 0x4F, + RN5T567_LDO5DAC = 0x50, + + RN5T567_LDORTC1DAC = 0x56, + RN5T567_LDORTC2DAC = 0x57, + + RN5T567_LDO1DAC_SLP = 0x58, + RN5T567_LDO2DAC_SLP = 0x59, + RN5T567_LDO3DAC_SLP = 0x5A, + RN5T567_LDO4DAC_SLP = 0x5B, + RN5T567_LDO5DAC_SLP = 0x5C, + + RN5T567_IOSEL = 0x90, + RN5T567_IOOUT = 0x91, + RN5T567_GPEDGE1 = 0x92, + RN5T567_EN_GPIR = 0x94, + RN5T567_IR_GPR = 0x95, + RN5T567_IR_GPF = 0x96, + RN5T567_MON_IOIN = 0x97, + RN5T567_GPLED_FUNC = 0x98, + RN5T567_INTPOL = 0x9C, + RN5T567_INTEN = 0x9D, + RN5T567_INTMON = 0x9E, + + RN5T567_PREVINDAC = 0xB0, + RN5T567_OVTEMP = 0xBC, + + RN5T567_NUM_OF_REGS = 0xBF, +}; + +#endif

-- 2.9.0

Simon Glass

4 Aug 4 Aug

3:16 a.m.

New subject: [U-Boot] [PATCH v2 07/10] power: pmic: add Ricoh RN5T567 PMIC support

+Stephen as an example of a simple PMIC driver.

- Simon

On 1 August 2016 at 23:50, Stefan Agner stefan@agner.ch wrote:

...

From: Stefan Agner stefan.agner@toradex.com

Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7.

Signed-off-by: Stefan Agner stefan.agner@toradex.com Reviewed-by: Simon Glass sjg@chromium.org

doc/device-tree-bindings/pmic/rn5t567.txt | 17 +++++ drivers/power/pmic/Kconfig | 8 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 +++++++++++++++++ include/power/rn5t567_pmic.h | 113 ++++++++++++++++++++++++++++++ 5 files changed, 203 insertions(+) create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/power/rn5t567_pmic.h

diff --git a/doc/device-tree-bindings/pmic/rn5t567.txt b/doc/device-tree-bindings/pmic/rn5t567.txt new file mode 100644 index 0000000..e9e6885 --- /dev/null +++ b/doc/device-tree-bindings/pmic/rn5t567.txt @@ -0,0 +1,17 @@ +Ricoh RN5T567 PMIC

+This file describes the binding info for the PMIC driver.

+Required properties: +- compatible: "ricoh,rn5t567" +- reg: depending on strapping, e.g. 0x33

+With those two properties, the PMIC device can be used to read/write +registers.

+Example:

+rn5t567@33 {
  compatible = "ricoh,rn5t567";
  reg = <0x33>;
+}; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 69f8d51..13d293a 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -127,6 +127,14 @@ config PMIC_S5M8767 driver provides basic register access and sets up the attached regulators if regulator support is enabled.

+config PMIC_RN5T567
  bool "Enable driver for Ricoh RN5T567 PMIC"
  depends on DM_PMIC
  ---help---
  The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
  regulators Real-Time Clock and 4 GPIOs. This driver provides
  register access only.
config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 52b4f71..37d9eb5 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_PMIC_RK808) += rk808.o +obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c new file mode 100644 index 0000000..001e695 --- /dev/null +++ b/drivers/power/pmic/rn5t567.c @@ -0,0 +1,64 @@ +/*

Copyright (C) 2016 Toradex AG

Stefan Agner stefan.agner@toradex.com

SPDX-License-Identifier: GPL-2.0+

*/

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <power/rn5t567_pmic.h> +#include <power/pmic.h>

+static int rn5t567_reg_count(struct udevice *dev) +{
  return RN5T567_NUM_OF_REGS;
+}

+static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff,
                    int len)
+{
  int ret;
  ret = dm_i2c_write(dev, reg, buff, len);
  if (ret) {
          debug("write error to device: %p register: %#x!", dev, reg);
          return ret;
  }
  return 0;
+}

+static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{
  int ret;
  ret = dm_i2c_read(dev, reg, buff, len);
  if (ret) {
          debug("read error from device: %p register: %#x!", dev, reg);
          return ret;
  }
  return 0;
+}

+static struct dm_pmic_ops rn5t567_ops = {
  .reg_count = rn5t567_reg_count,
  .read = rn5t567_read,
  .write = rn5t567_write,
+};

+static const struct udevice_id rn5t567_ids[] = {
  { .compatible = "ricoh,rn5t567" },
  { }
+};

+U_BOOT_DRIVER(pmic_rn5t567) = {
  .name = "rn5t567 pmic",
  .id = UCLASS_PMIC,
  .of_match = rn5t567_ids,
  .ops = &rn5t567_ops,
+}; diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h new file mode 100644 index 0000000..9ce601f --- /dev/null +++ b/include/power/rn5t567_pmic.h @@ -0,0 +1,113 @@ +/*

Copyright (C) 2016 Toradex AG

Stefan Agner stefan.agner@toradex.com

SPDX-License-Identifier: GPL-2.0+

*/

+#ifndef __RN5T567_PMIC_H_ +#define __RN5T567_PMIC_H_

+/* RN5T567 registers */ +enum {
  RN5T567_LSIVER          = 0x00,
  RN5T567_OTPVER          = 0x01,
  RN5T567_IODAC           = 0x02,
  RN5T567_VINDAC          = 0x03,
  RN5T567_OUT32KEN        = 0x05,
  RN5T567_CPUCNT          = 0x06,
  RN5T567_PSWR            = 0x07,
  RN5T567_PONHIS          = 0x09,
  RN5T567_POFFHIS         = 0x0A,
  RN5T567_WATCHDOG        = 0x0B,
  RN5T567_WATCHDOGCNT     = 0x0C,
  RN5T567_PWRFUNC         = 0x0D,
  RN5T567_SLPCNT          = 0x0E,
  RN5T567_REPCNT          = 0x0F,
  RN5T567_PWRONTIMSET     = 0x10,
  RN5T567_NOETIMSETCNT    = 0x11,
  RN5T567_PWRIREN         = 0x12,
  RN5T567_PWRIRQ          = 0x13,
  RN5T567_PWRMON          = 0x14,
  RN5T567_PWRIRSEL        = 0x15,
  RN5T567_DC1_SLOT        = 0x16,
  RN5T567_DC2_SLOT        = 0x17,
  RN5T567_DC3_SLOT        = 0x18,
  RN5T567_DC4_SLOT        = 0x19,
  RN5T567_LDO1_SLOT       = 0x1B,
  RN5T567_LDO2_SLOT       = 0x1C,
  RN5T567_LDO3_SLOT       = 0x1D,
  RN5T567_LDO4_SLOT       = 0x1E,
  RN5T567_LDO5_SLOT       = 0x1F,
  RN5T567_PSO0_SLOT       = 0x25,
  RN5T567_PSO1_SLOT       = 0x26,
  RN5T567_PSO2_SLOT       = 0x27,
  RN5T567_PSO3_SLOT       = 0x28,
  RN5T567_LDORTC1_SLOT    = 0x2A,
  RN5T567_DC1CTL          = 0x2C,
  RN5T567_DC1CTL2         = 0x2D,
  RN5T567_DC2CTL          = 0x2E,
  RN5T567_DC2CTL2         = 0x2F,
  RN5T567_DC3CTL          = 0x30,
  RN5T567_DC3CTL2         = 0x31,
  RN5T567_DC4CTL          = 0x32,
  RN5T567_DC4CTL2         = 0x33,
  RN5T567_DC1DAC          = 0x36,
  RN5T567_DC2DAC          = 0x37,
  RN5T567_DC3DAC          = 0x38,
  RN5T567_DC4DAC          = 0x39,
  RN5T567_DC1DAC_SLP      = 0x3B,
  RN5T567_DC2DAC_SLP      = 0x3C,
  RN5T567_DC3DAC_SLP      = 0x3D,
  RN5T567_DC4DAC_SLP      = 0x3E,
  RN5T567_DCIREN          = 0x40,
  RN5T567_DCIRQ           = 0x41,
  RN5T567_DCIRMON         = 0x42,
  RN5T567_LDOEN1          = 0x44,
  RN5T567_LDOEN2          = 0x45,
  RN5T567_LDODIS1         = 0x46,
  RN5T567_LDO1DAC         = 0x4C,
  RN5T567_LDO2DAC         = 0x4D,
  RN5T567_LDO3DAC         = 0x4E,
  RN5T567_LDO4DAC         = 0x4F,
  RN5T567_LDO5DAC         = 0x50,
  RN5T567_LDORTC1DAC      = 0x56,
  RN5T567_LDORTC2DAC      = 0x57,
  RN5T567_LDO1DAC_SLP     = 0x58,
  RN5T567_LDO2DAC_SLP     = 0x59,
  RN5T567_LDO3DAC_SLP     = 0x5A,
  RN5T567_LDO4DAC_SLP     = 0x5B,
  RN5T567_LDO5DAC_SLP     = 0x5C,
  RN5T567_IOSEL           = 0x90,
  RN5T567_IOOUT           = 0x91,
  RN5T567_GPEDGE1         = 0x92,
  RN5T567_EN_GPIR         = 0x94,
  RN5T567_IR_GPR          = 0x95,
  RN5T567_IR_GPF          = 0x96,
  RN5T567_MON_IOIN        = 0x97,
  RN5T567_GPLED_FUNC      = 0x98,
  RN5T567_INTPOL          = 0x9C,
  RN5T567_INTEN           = 0x9D,
  RN5T567_INTMON          = 0x9E,
  RN5T567_PREVINDAC       = 0xB0,
  RN5T567_OVTEMP          = 0xBC,
  RN5T567_NUM_OF_REGS     = 0xBF,
+};

+#endif

2.9.0

Stefan Agner

2 Aug 2 Aug

7:50 a.m.

New subject: [U-Boot] [PATCH v2 08/10] arm: dts: imx7: add Ricoh RN5T567 PMIC node

From: Stefan Agner stefan.agner@toradex.com

Add device tree node for Ricoh RN5T567. Currently we do not need the individual DC/DC converters or LDO's (and they are also not yet supported by the driver).

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

arch/arm/dts/imx7-colibri.dts | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts index f2da096..cbef5d5 100644 --- a/arch/arm/dts/imx7-colibri.dts +++ b/arch/arm/dts/imx7-colibri.dts @@ -24,6 +24,11 @@ sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; + + rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; + }; };

&i2c4 {

-- 2.9.0

Simon Glass

4 Aug 4 Aug

3:16 a.m.

New subject: [U-Boot] [PATCH v2 08/10] arm: dts: imx7: add Ricoh RN5T567 PMIC node

On 1 August 2016 at 23:50, Stefan Agner stefan@agner.ch wrote:

...

From: Stefan Agner stefan.agner@toradex.com

Add device tree node for Ricoh RN5T567. Currently we do not need the individual DC/DC converters or LDO's (and they are also not yet supported by the driver).

Signed-off-by: Stefan Agner stefan.agner@toradex.com

arch/arm/dts/imx7-colibri.dts | 5 +++++ 1 file changed, 5 insertions(+)

Reviewed-by: Simon Glass sjg@chromium.org

Stefan Agner

2 Aug 2 Aug

7:50 a.m.

New subject: [U-Boot] [PATCH v2 09/10] colibri_imx7: use Ricoh RN5T567 to reboot the board

From: Stefan Agner stefan.agner@toradex.com

Use the external PMIC Ricoh RN5T567 to reliably restart the system.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

board/toradex/colibri_imx7/colibri_imx7.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index bd7d5bc..c64e31e 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -21,6 +21,8 @@ #include <mmc.h> #include <miiphy.h> #include <netdev.h> +#include <power/pmic.h> +#include <power/rn5t567_pmic.h> #include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR; @@ -337,6 +339,46 @@ int board_late_init(void) return 0; }

+#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int reg, ver; + int ret; + + + ret = pmic_get("rn5t567", &dev); + if (ret) + return ret; + ver = pmic_reg_read(dev, RN5T567_LSIVER); + reg = pmic_reg_read(dev, RN5T567_OTPVER); + + printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); + + /* set judge and press timer of N_OE to minimal values */ + pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); + + return 0; +} + +void reset_cpu(ulong addr) +{ + struct udevice *dev; + + pmic_get("rn5t567", &dev); + + /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ + pmic_reg_write(dev, RN5T567_REPCNT, 0x1); + pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); + + /* + * Re-power factor detection on PMIC side is not instant. 1ms + * proved to be enough time until reset takes effect. + */ + mdelay(1); +} +#endif + int checkboard(void) { printf("Model: Toradex Colibri iMX7%c\n",

-- 2.9.0

Stefan Agner

7:50 a.m.

New subject: [U-Boot] [PATCH v2 10/10] configs: enable device tree for Colibri iMX7

From: Stefan Agner stefan.agner@toradex.com

Enable device tree configuration and specify default device tree for Toradex Colibri iMX7. Also configure CONFIG_CUSTOM_BOARDINFO to avoid that board info get printed twice (once from the device tree and one from the runtime detection in board specific code).

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

configs/colibri_imx7_defconfig | 10 +++++++++- include/configs/colibri_imx7.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 50c1201..d78b35c 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -1,8 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_TARGET_COLIBRI_IMX7=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" CONFIG_BOOTDELAY=1 CONFIG_HUSH_PARSER=y @@ -29,6 +32,12 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RN5T567=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y @@ -37,4 +46,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Toradex" CONFIG_G_DNL_VENDOR_NUM=0x1b67 CONFIG_G_DNL_PRODUCT_NUM=0x4020 -CONFIG_OF_LIBFDT=y diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 32b6101..2927818 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -24,6 +24,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT

+#define CONFIG_CUSTOM_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO_LATE

/* Size of malloc() pool */

-- 2.9.0

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