From: Michal Simek monstr@monstr.eu

Here are two major changes which should go together. First is adding LL Temac driver to u-boot and the second is changing Emaclite to NET_MULTI api.

There are some changes for proper initialization too.

Signed-off-by: Michal Simek monstr@monstr.eu Signed-off-by: Michal Simek michal.simek@petalogix.com --- .../xilinx/microblaze-generic/microblaze-generic.c | 16 + drivers/net/Makefile | 1 + drivers/net/xilinx_emaclite.c | 42 ++- drivers/net/xilinx_ll_temac.c | 567 ++++++++++++++++++++ include/configs/microblaze-generic.h | 2 + include/netdev.h | 2 + lib_microblaze/board.c | 21 +- 7 files changed, 634 insertions(+), 17 deletions(-) create mode 100644 drivers/net/xilinx_ll_temac.c

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index f388b77..4ad9eb6 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -27,6 +27,7 @@

#include <common.h> #include <config.h> +#include <netdev.h> #include <asm/microblaze_intc.h> #include <asm/asm.h>

@@ -67,3 +68,18 @@ void fsl_init2 (void) { NULL); } #endif + +int board_eth_init(bd_t *bis) +{ + /* + * This board either has PCI NICs or uses the CPU's TSECs + * pci_eth_init() will return 0 if no NICs found, so in that case + * returning -1 will force cpu_eth_init() to be called. + */ +#ifdef CONFIG_XILINX_EMACLITE + return xilinx_emaclite_initialize(bis); +#endif +#ifdef CONFIG_XILINX_LL_TEMAC + return xilinx_ll_temac_initialize(bis); +#endif +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1c6e402..98cb3a1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,6 +74,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index cf39573..e437d16 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -25,6 +25,7 @@ #include <common.h> #include <net.h> #include <config.h> +#include <malloc.h> #include <asm/io.h>

#undef DEBUG @@ -79,7 +80,7 @@ static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; static u8 emacaddr[ENET_ADDR_LENGTH]; #endif

-void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) +static void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) { unsigned int i; u32 alignbuffer; @@ -106,7 +107,7 @@ void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) } }

-void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) +static void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) { unsigned i; u32 alignbuffer; @@ -133,12 +134,12 @@ void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) *to32ptr++ = alignbuffer; }

-void eth_halt (void) +static void emaclite_halt(struct eth_device *dev) { debug ("eth_halt\n"); }

-int eth_init (bd_t * bis) +static int emaclite_init(struct eth_device *dev, bd_t *bis) { uchar enetaddr[6];

@@ -193,7 +194,7 @@ int eth_init (bd_t * bis) return 0; }

-int xemaclite_txbufferavailable (xemaclite * instanceptr) +static int xemaclite_txbufferavailable (xemaclite * instanceptr) { u32 reg; u32 txpingbusy; @@ -215,8 +216,8 @@ int xemaclite_txbufferavailable (xemaclite * instanceptr) return (!(txpingbusy && txpongbusy)); }

-int eth_send (volatile void *ptr, int len) { - +static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) +{ unsigned int reg; unsigned int baseaddress;

@@ -292,7 +293,8 @@ int eth_send (volatile void *ptr, int len) { return 0; }

-int eth_rx (void) + +static int emaclite_recv(struct eth_device *dev) { unsigned int length; unsigned int reg; @@ -352,3 +354,27 @@ int eth_rx (void) return 1;

} + + +int xilinx_emaclite_initialize (bd_t *bis) +{ + struct eth_device *dev; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "Xilinx Emaclite"); + + dev->iobase = 0; + dev->priv = 0; + dev->init = emaclite_init; + dev->halt = emaclite_halt; + dev->send = emaclite_send; + dev->recv = emaclite_recv; + + eth_register(dev); + + return 0; +} diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c new file mode 100644 index 0000000..4b42b06 --- /dev/null +++ b/drivers/net/xilinx_ll_temac.c @@ -0,0 +1,567 @@ +/* + * + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * Author: Yoshio Kashiwagi kashiwagi@co-nss.co.jp + * + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * Copyright (C) 2008 - 2009 Michal Simek monstr@monstr.eu + * June 2008 Microblaze optimalization, FIFO mode support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <config.h> +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> + +#ifdef XILINX_LLTEMAC_FIFO_BASEADDR +# define FIFO_MODE 1 +#elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR +# define SDMA_MODE 1 +#else +# error Unsupported mode +#endif + +#undef ETH_HALTING + +#ifdef SDMA_MODE +/* XPS_LL_TEMAC SDMA registers definition */ +# define TX_NXTDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x00) +# define TX_CURBUF_ADDR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x04) +# define TX_CURBUF_LENGTH (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x08) +# define TX_CURDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x0c) +# define TX_TAILDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x10) +# define TX_CHNL_CTRL (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x14) +# define TX_IRQ_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x18) +# define TX_CHNL_STS (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x1c) + +# define RX_NXTDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x20) +# define RX_CURBUF_ADDR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x24) +# define RX_CURBUF_LENGTH (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x28) +# define RX_CURDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x2c) +# define RX_TAILDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x30) +# define RX_CHNL_CTRL (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x34) +# define RX_IRQ_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x38) +# define RX_CHNL_STS (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x3c) + +# define DMA_CONTROL_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x40) +#endif + +/* XPS_LL_TEMAC direct registers definition */ +#define TEMAC_RAF0 (XILINX_LLTEMAC_BASEADDR + 0x00) +#define TEMAC_TPF0 (XILINX_LLTEMAC_BASEADDR + 0x04) +#define TEMAC_IFGP0 (XILINX_LLTEMAC_BASEADDR + 0x08) +#define TEMAC_IS0 (XILINX_LLTEMAC_BASEADDR + 0x0c) +#define TEMAC_IP0 (XILINX_LLTEMAC_BASEADDR + 0x10) +#define TEMAC_IE0 (XILINX_LLTEMAC_BASEADDR + 0x14) + +#define TEMAC_MSW0 (XILINX_LLTEMAC_BASEADDR + 0x20) +#define TEMAC_LSW0 (XILINX_LLTEMAC_BASEADDR + 0x24) +#define TEMAC_CTL0 (XILINX_LLTEMAC_BASEADDR + 0x28) +#define TEMAC_RDY0 (XILINX_LLTEMAC_BASEADDR + 0x2c) + +#define XTE_RSE_MIIM_RR_MASK 0x0002 +#define XTE_RSE_MIIM_WR_MASK 0x0004 +#define XTE_RSE_CFG_RR_MASK 0x0020 +#define XTE_RSE_CFG_WR_MASK 0x0040 + +/* XPS_LL_TEMAC indirect registers offset definition */ + +#define RCW0 0x200 +#define RCW1 0x240 +#define TC 0x280 +#define FCC 0x2c0 +#define EMMC 0x300 +#define PHYC 0x320 +#define MC 0x340 +#define UAW0 0x380 +#define UAW1 0x384 +#define MAW0 0x388 +#define MAW1 0x38c +#define AFM 0x390 +#define TIS 0x3a0 +#define TIE 0x3a4 +#define MIIMWD 0x3b0 +#define MIIMAI 0x3b4 + +#define CNTLREG_WRITE_ENABLE_MASK 0x8000 +#define CNTLREG_EMAC1SEL_MASK 0x0400 +#define CNTLREG_ADDRESSCODE_MASK 0x03ff + +#define MDIO_ENABLE_MASK 0x40 +#define MDIO_CLOCK_DIV_MASK 0x3F +#define MDIO_CLOCK_DIV_100MHz 0x28 + +#define ETHER_MTU 1520 + +#ifdef SDMA_MODE +/* CDMAC descriptor status bit definitions */ +# define BDSTAT_ERROR_MASK 0x80 +# define BDSTAT_INT_ON_END_MASK 0x40 +# define BDSTAT_STOP_ON_END_MASK 0x20 +# define BDSTAT_COMPLETED_MASK 0x10 +# define BDSTAT_SOP_MASK 0x08 +# define BDSTAT_EOP_MASK 0x04 +# define BDSTAT_CHANBUSY_MASK 0x02 +# define BDSTAT_CHANRESET_MASK 0x01 + +/* SDMA Buffer Descriptor */ + +typedef struct cdmac_bd_t { + struct cdmac_bd_t *next_p; + unsigned char *phys_buf_p; + unsigned long buf_len; + unsigned char stat; + unsigned char app1_1; + unsigned short app1_2; + unsigned long app2; + unsigned long app3; + unsigned long app4; + unsigned long app5; +} cdmac_bd __attribute((aligned(32))) ; + +static cdmac_bd tx_bd; +static cdmac_bd rx_bd; +#endif + +#ifdef FIFO_MODE +typedef struct ll_fifo_s { + int isr; /* Interrupt Status Register 0x0 */ + int ier; /* Interrupt Enable Register 0x4 */ + int tdfr; /* Transmit data FIFO reset 0x8 */ + int tdfv; /* Transmit data FIFO Vacancy 0xC */ + int tdfd; /* Transmit data FIFO 32bit wide data write port 0x10 */ + int tlf; /* Write Transmit Length FIFO 0x14 */ + int rdfr; /* Read Receive data FIFO reset 0x18 */ + int rdfo; /* Receive data FIFO Occupancy 0x1C */ + int rdfd; /* Read Receive data FIFO 32bit wide data read port 0x20 */ + int rlf; /* Read Receive Length FIFO 0x24 */ + int llr; /* Read LocalLink reset 0x28 */ +} ll_fifo_s; + +ll_fifo_s *ll_fifo = (ll_fifo_s *) (XILINX_LLTEMAC_FIFO_BASEADDR); +#endif + +static unsigned char tx_buffer[ETHER_MTU] __attribute((aligned(32))); +static unsigned char rx_buffer[ETHER_MTU] __attribute((aligned(32))); + +struct xps_ll_temac_private { + int idx; + unsigned char dev_addr[6]; +}; + +#ifdef DEBUG +/* undirect hostif write to ll_temac */ +static void xps_ll_temac_hostif_set(int emac, int phy_addr, + int reg_addr, int phy_data) +{ + out_be32((u32 *)TEMAC_LSW0, phy_data); + out_be32((u32 *)TEMAC_CTL0, CNTLREG_WRITE_ENABLE_MASK | MIIMWD); + out_be32((u32 *)TEMAC_LSW0, (phy_addr << 5) | (reg_addr)); + out_be32((u32 *)TEMAC_CTL0, \ + CNTLREG_WRITE_ENABLE_MASK | MIIMAI | (emac << 10)); + while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_MIIM_WR_MASK)); +} +#endif + +/* undirect hostif read from ll_temac */ +static unsigned int xps_ll_temac_hostif_get(int emac, int phy_addr, int reg_addr) +{ + out_be32((u32 *)TEMAC_LSW0, (phy_addr << 5) | (reg_addr)); + out_be32((u32 *)TEMAC_CTL0, MIIMAI | (emac << 10)); + while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_MIIM_RR_MASK)); + return in_be32((u32 *)TEMAC_LSW0); +} + +/* undirect write to ll_temac */ +static void xps_ll_temac_indirect_set(int emac, int reg_offset, int reg_data) +{ + out_be32((u32 *)TEMAC_LSW0, reg_data); + out_be32((u32 *)TEMAC_CTL0, \ + CNTLREG_WRITE_ENABLE_MASK | (emac << 10) | reg_offset); + while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_CFG_WR_MASK)); +} + +/* undirect read from ll_temac */ +static int xps_ll_temac_indirect_get(int emac, int reg_offset) +{ + out_be32((u32 *)TEMAC_CTL0, (emac << 10) | reg_offset); + while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_CFG_RR_MASK)); + return in_be32((u32 *)TEMAC_LSW0); +} + +#ifdef DEBUG +/* read from phy */ +static void read_phy_reg (int phy_addr) +{ + int j, result; + printf("phy%d ",phy_addr); + for ( j = 0; j < 32; j++) { + result = xps_ll_temac_hostif_get(0, phy_addr, j); + printf("%d: 0x%x ", j, result); + } + puts("\n"); +} +#endif + +static int phy_addr = -1; +static int link = 0; + +/* setting ll_temac and phy to proper setting */ +static int xps_ll_temac_phy_ctrl(void) +{ + int i; + unsigned int result; + unsigned retries = 10; + + if(link == 1) + return 1; /* link is setup */ + + /* wait for link up */ + while (retries-- && + ((xps_ll_temac_hostif_get(0, phy_addr, 1) & 0x24) == 0x24)) + ; + + if(phy_addr == -1) { + for(i = 31; i >= 0; i--) { + result = xps_ll_temac_hostif_get(0, i, 1); + if((result & 0x0ffff) != 0x0ffff) { +#ifdef DEBUG + printf ("phy %x result %x\n", i, result); +#endif + phy_addr = i; + break; + } + } + } + + /* get PHY id */ + i = (xps_ll_temac_hostif_get(0, phy_addr, 2) << 16) | \ + xps_ll_temac_hostif_get(0, phy_addr, 3); +#ifdef DEBUG + printf("LL_TEMAC: Phy ID 0x%x\n", i); +#endif + +#ifdef DEBUG + xps_ll_temac_hostif_set(0, 0, 0, 0x8000); /* phy reset */ +#endif + /* FIXME this part will be replaced by PHY lib */ + /* s3e boards */ + if (i == 0x7c0a3) { + xps_ll_temac_indirect_set(0, EMMC, 0x40000000); /* 100BASE-T/FD */ + link = 1; + return 1; + } + + /* Marwell 88e1111 id - ml50x */ + if (i == 0x1410cc2) { + result = xps_ll_temac_hostif_get(0, phy_addr, 5); + if((result & 0x8000) == 0x8000) { + xps_ll_temac_indirect_set(0, EMMC, 0x80000000); + printf("1000BASE-T/FD\n"); + link = 1; + } else if((result & 0x4000) == 0x4000) { + xps_ll_temac_indirect_set(0, EMMC, 0x40000000); + printf("100BASE-T/FD\n"); + link = 1; + } else { + printf("Unsupported mode\n"); + link = 0; + } + return 1; + } + return 0; +} + +#ifdef SDMA_MODE +/* bd init */ +static void xps_ll_temac_bd_init(void) +{ + memset((void *)&tx_bd, 0, sizeof(cdmac_bd)); + memset((void *)&rx_bd, 0, sizeof(cdmac_bd)); + + rx_bd.phys_buf_p = &rx_buffer[0]; + + rx_bd.next_p = &rx_bd; + rx_bd.buf_len = ETHER_MTU; + flush_cache((u32)&rx_bd, sizeof(cdmac_bd)); + + out_be32((u32 *)RX_CURDESC_PTR, (u32)&rx_bd); + out_be32((u32 *)RX_TAILDESC_PTR, (u32)&rx_bd); + out_be32((u32 *)RX_NXTDESC_PTR, (u32)&rx_bd); /* setup first fd */ + + tx_bd.phys_buf_p = &tx_buffer[0]; + tx_bd.next_p = &tx_bd; + + flush_cache((u32)&tx_bd, sizeof(cdmac_bd)); + out_be32((u32 *)TX_CURDESC_PTR, (u32)&tx_bd); +} +#endif + +#ifdef SDMA_MODE +static int xps_ll_temac_send_sdma(unsigned char *buffer, int length) +{ + if( xps_ll_temac_phy_ctrl() == 0) + return 0; + + memcpy (tx_buffer, buffer, length); + flush_cache ((u32)tx_buffer, length); + + tx_bd.stat = BDSTAT_SOP_MASK | BDSTAT_EOP_MASK | BDSTAT_STOP_ON_END_MASK; + tx_bd.buf_len = length; + flush_cache ((u32)&tx_bd, sizeof(cdmac_bd)); + + out_be32((u32 *)TX_CURDESC_PTR, (u32)&tx_bd); + out_be32((u32 *)TX_TAILDESC_PTR, (u32)&tx_bd); /* DMA start */ + + do { + flush_cache ((u32)&tx_bd, sizeof(cdmac_bd)); + } while(!(((volatile int)tx_bd.stat) & BDSTAT_COMPLETED_MASK)); + + return length; +} + + +static int xps_ll_temac_recv_sdma(void) +{ + int length; + + flush_cache ((u32)&rx_bd, sizeof(cdmac_bd)); + + if(!(rx_bd.stat & BDSTAT_COMPLETED_MASK)) { + return 0; + } + + length = rx_bd.app5; + flush_cache ((u32)rx_bd.phys_buf_p, length); + + rx_bd.buf_len = ETHER_MTU; + rx_bd.stat = 0; + rx_bd.app5 = 0; + + flush_cache ((u32)&rx_bd, sizeof(cdmac_bd)); + out_be32((u32 *)RX_TAILDESC_PTR, (u32)&rx_bd); + + if(length > 0) { + NetReceive(rx_bd.phys_buf_p, length); + } + + return length; +} +#endif + + +#ifdef FIFO_MODE +static void debugll(int count) +{ + printf ("%d fifo isr 0x%08x, fifo_ier 0x%08x, fifo_rdfr 0x%08x, fifo_rdfo 0x%08x fifo_rlr 0x%08x\n",count, ll_fifo->isr, \ + ll_fifo->ier, ll_fifo->rdfr, ll_fifo->rdfo, ll_fifo->rlf); + +} + +static int xps_ll_temac_send_fifo(unsigned char *buffer, int length) +{ + u32 *buf = buffer; + u32 len, i, val; + + len = (length / 4) + 1; + + for (i = 0; i < len; i++) { + val = *buf++; + ll_fifo->tdfd = val; + } + + ll_fifo->tlf = length; + + return length; +} + +static int xps_ll_temac_recv_fifo() +{ + int len, len2, i, val; + int *buf; + buf = &rx_buffer; + + if (ll_fifo->isr & 0x04000000 ) { + ll_fifo->isr = 0xffffffff; /* reset isr */ + + /* while (ll_fifo->isr); */ + len = ll_fifo->rlf & 0x7FF; + len2 = (len / 4) + 1; + + for (i = 0; i < len2; i++) { + val = ll_fifo->rdfd; + *buf++ = val ; + } + + /* debugll(1); */ + NetReceive (&rx_buffer, len); + } + return 0; +} +#endif + +/* setup mac addr */ +static int xps_ll_temac_addr_setup(struct xps_ll_temac_private * lp) +{ + char * env_p; + char * end; + int i, val; + + env_p = getenv("ethaddr"); + if (env_p == NULL) { + printf("cannot get enviroment for "ethaddr".\n"); + return -1; + } + + for (i = 0; i < 6; i++) { + lp->dev_addr[i] = env_p ? simple_strtoul(env_p, &end, 16) : 0; + if (env_p) env_p = (*end) ? end + 1 : end; + } + + /* set up unicast MAC address filter */ + val = ((lp->dev_addr[3] << 24) | (lp->dev_addr[2] << 16) | + (lp->dev_addr[1] << 8) | (lp->dev_addr[0] )); + xps_ll_temac_indirect_set(0, UAW0, val); + val = (lp->dev_addr[5] << 8) | lp->dev_addr[4] ; + xps_ll_temac_indirect_set(0, UAW1, val); + + return 0; +} + +static int xps_ll_temac_init(struct eth_device *dev, bd_t *bis) +{ + struct xps_ll_temac_private *lp = (struct xps_ll_temac_private *)dev->priv; + +#ifdef SDMA_MODE + xps_ll_temac_bd_init(); +#endif +#ifdef FIFO_MODE + ll_fifo->tdfr = 0x000000a5; /* set fifo lenght */ + ll_fifo->rdfr = 0x000000a5; + + /* ll_fifo->isr = 0x0; */ + /* ll_fifo->ier = 0x0; */ +#endif + xps_ll_temac_indirect_set(0, MC, MDIO_ENABLE_MASK | MDIO_CLOCK_DIV_100MHz); + + xps_ll_temac_addr_setup(lp); + xps_ll_temac_indirect_set(0, AFM, 0x00000000); /* Promiscuos mode disable */ + xps_ll_temac_indirect_set(0, RCW1, 0x10000000); /* Enable Receiver */ + xps_ll_temac_indirect_set(0, TC, 0x10000000); /* Enable Transmitter */ + return 0; +} + + +static void xps_ll_temac_halt(void) +{ +#ifdef ETH_HALTING + xps_ll_temac_indirect_set(0, RCW1, 0x00000000); /* Disable Receiver */ + xps_ll_temac_indirect_set(0, TC, 0x00000000); /* Disable Transmitter */ + +#ifdef SDMA_MODE + out_be32((u32 *)DMA_CONTROL_REG, 0x00000001); + while(in_be32((u32 *)DMA_CONTROL_REG) & 1); +#endif +#ifdef FIFO_MODE + /* reset fifos */ +#endif +#endif +} + + +/* halt device */ +static void ll_temac_halt(struct eth_device *dev) +{ + link = 0; + xps_ll_temac_halt(); +} + +static int ll_temac_init(struct eth_device *dev, bd_t *bis) +{ + static int first = 1; + struct xps_ll_temac_private *lp; +#if DEBUG + int i; +#endif + + if(!first) + return 0; + first = 0; + dev = (struct eth_device *) calloc(1, sizeof(struct eth_device)); + if (NULL == dev) + return 0; + + lp = (struct xps_ll_temac_private *) calloc(1, sizeof(struct xps_ll_temac_private)); + if (lp == NULL) + return 0; + dev->priv = lp; + sprintf(dev->name, "eth0"); + + xps_ll_temac_init(dev, bis); + + printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n", + dev->name, 0, XILINX_LLTEMAC_BASEADDR); + +#if DEBUG + for(i = 0;i < 32;i++) { + read_phy_reg(i); + } +#endif + xps_ll_temac_phy_ctrl(); + return 1; +} + + +static int ll_temac_send(struct eth_device *dev, volatile void *packet, int length) +{ +#ifdef SDMA_MODE + return xps_ll_temac_send_sdma((unsigned char *)packet, length); +#endif +#ifdef FIFO_MODE + return xps_ll_temac_send_fifo((unsigned char *)packet, length); +#endif +} + +static int ll_temac_recv(struct eth_device *dev) +{ +#ifdef SDMA_MODE + return xps_ll_temac_recv_sdma(); +#endif +#ifdef FIFO_MODE + return xps_ll_temac_recv_fifo(); +#endif +} + +int xilinx_ll_temac_initialize (bd_t *bis) +{ + struct eth_device *dev; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "Xilinx LL TEMAC"); + + dev->iobase = 0; + dev->priv = 0; + dev->init = ll_temac_init; + dev->halt = ll_temac_halt; + dev->send = ll_temac_send; + dev->recv = ll_temac_recv; + + eth_register(dev); + + return 0; +} diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 72715f6..89e4bcc 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -232,8 +232,10 @@

#ifndef CONFIG_SYS_ENET #undef CONFIG_CMD_NET + #undef CONFIG_NET_MULTI #else #define CONFIG_CMD_PING + #define CONFIG_NET_MULTI #endif

#if defined(CONFIG_SYSTEMACE) diff --git a/include/netdev.h b/include/netdev.h index 50329a3..8da0110 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,6 +78,8 @@ int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); +int xilinx_emaclite_initialize (bd_t *bis); +int xilinx_ll_temac_initialize(bd_t *bis); int sh_eth_initialize(bd_t *bis); int dm9000_initialize(bd_t *bis);

diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index cfed5fe..8d17b03 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -30,6 +30,7 @@ #include <timestamp.h> #include <version.h> #include <watchdog.h> +#include <net.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -41,10 +42,6 @@ extern int gpio_init (void); #ifdef CONFIG_SYS_INTC_0 extern int interrupts_init (void); #endif -#if defined(CONFIG_CMD_NET) -extern int eth_init (bd_t * bis); -extern int getenv_IPaddr (char *); -#endif

/* * Begin and End of memory area for malloc(), and current "brk" @@ -168,14 +165,20 @@ void board_init (void) } #endif

+ /* relocate environment function pointers etc. */ + env_relocate (); + #if defined(CONFIG_CMD_NET) /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - eth_init (bd); -#endif + bd->bi_ip_addr = getenv_IPaddr("ipaddr");

- /* relocate environment function pointers etc. */ - env_relocate (); + printf("Net: "); + eth_initialize(gd->bd); + + uchar enetaddr[6]; + eth_getenv_enetaddr("ethaddr", enetaddr); + printf("MAC: %pM\n", enetaddr); +#endif

/* main_loop */ for (;;) {

From: Michal Simek monstr@monstr.eu

Signed-off-by: Michal Simek monstr@monstr.eu Signed-off-by: Michal Simek michal.simek@petalogix.com --- board/xilinx/microblaze-generic/u-boot.lds | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/board/xilinx/microblaze-generic/u-boot.lds b/board/xilinx/microblaze-generic/u-boot.lds index 5a08680..c20c6dd 100644 --- a/board/xilinx/microblaze-generic/u-boot.lds +++ b/board/xilinx/microblaze-generic/u-boot.lds @@ -60,7 +60,10 @@ SECTIONS .bss ALIGN(0x4): { __bss_start = .; + *(.sbss) + *(.scommon) *(.bss) + *(COMMON) . = ALIGN(4); __bss_end = .; }

From: Michal Simek monstr@monstr.eu

Signed-off-by: Michal Simek monstr@monstr.eu Signed-off-by: Michal Simek michal.simek@petalogix.com --- drivers/net/Makefile | 1 - drivers/net/xilinx_emac.c | 464 ---------------------------------- include/configs/microblaze-generic.h | 5 +- 3 files changed, 1 insertions(+), 469 deletions(-) delete mode 100644 drivers/net/xilinx_emac.c

diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 98cb3a1..4fd53f9 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -72,7 +72,6 @@ COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o -COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o

diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c deleted file mode 100644 index a489aa9..0000000 --- a/drivers/net/xilinx_emac.c +++ /dev/null @@ -1,464 +0,0 @@ -/****************************************************************************** - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" - * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND - * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, - * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, - * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION - * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, - * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE - * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY - * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE - * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR - * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF - * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE. - * - * (C) Copyright 2007-2008 Michal Simek - * Michal SIMEK monstr@monstr.eu - * - * (c) Copyright 2003 Xilinx Inc. - * All rights reserved. - * - ******************************************************************************/ - -#include <config.h> -#include <common.h> -#include <net.h> -#include <asm/io.h> - -#include <asm/asm.h> - -#undef DEBUG - -typedef struct { - u32 regbaseaddress; /* Base address of registers */ - u32 databaseaddress; /* Base address of data for FIFOs */ -} xpacketfifov100b; - -typedef struct { - u32 baseaddress; /* Base address (of IPIF) */ - u32 isstarted; /* Device is currently started 0-no, 1-yes */ - xpacketfifov100b recvfifo; /* FIFO used to receive frames */ - xpacketfifov100b sendfifo; /* FIFO used to send frames */ -} xemac; - -#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ -#define XIIF_V123B_RESET_MASK 0xAUL -#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ - -/* This constant is used with the Reset Register */ -#define XPF_RESET_FIFO_MASK 0x0000000A -#define XPF_COUNT_STATUS_REG_OFFSET 4UL - -/* These constants are used with the Occupancy/Vacancy Count Register. This - * register also contains FIFO status */ -#define XPF_COUNT_MASK 0x0000FFFF -#define XPF_DEADLOCK_MASK 0x20000000 - -/* Offset of the MAC registers from the IPIF base address */ -#define XEM_REG_OFFSET 0x1100UL - -/* - * Register offsets for the Ethernet MAC. Each register is 32 bits. - */ -#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ -#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ -#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ -#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ -#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ -#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ - -#define XEM_PFIFO_OFFSET 0x2000UL -/* Tx registers */ -#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) -/* Rx registers */ -#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) -/* Tx keyhole */ -#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) -/* Rx keyhole */ -#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) - -/* - * EMAC Interrupt Registers (Status and Enable) masks. These registers are - * part of the IPIF IP Interrupt registers - */ -/* A mask for all transmit interrupts, used in polled mode */ -#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ - XEM_EIR_XMIT_ERROR_MASK | \ - XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ - XEM_EIR_XMIT_LFIFO_FULL_MASK) - -/* Xmit complete */ -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL -/* Recv complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL -/* Xmit error */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL -/* Recv error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL -/* Xmit status fifo empty */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL -/* Recv length fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL -/* Xmit length fifo full */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL -/* Recv length fifo overrun */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL -/* Recv length fifo underrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL -/* Xmit status fifo overrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL -/* Transmit status fifo underrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL -/* Transmit length fifo overrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL -/* Transmit length fifo underrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL -/* Transmit pause pkt received */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL - -/* - * EMAC Control Register (ECR) - */ -/* Full duplex mode */ -#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL -/* Reset transmitter */ -#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL -/* Enable transmitter */ -#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL -/* Reset receiver */ -#define XEM_ECR_RECV_RESET_MASK 0x10000000UL -/* Enable receiver */ -#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL -/* Enable PHY */ -#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL -/* Enable xmit pad insert */ -#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL -/* Enable xmit FCS insert */ -#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL -/* Enable unicast addr */ -#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL -/* Enable broadcast addr */ -#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL - -/* - * Transmit Status Register (TSR) - */ -/* Transmit excess deferral */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL -/* Transmit late collision */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL - -#define ENET_MAX_MTU PKTSIZE -#define ENET_ADDR_LENGTH 6 - -static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ - -static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; - -static xemac emac; - -void eth_halt(void) -{ - debug ("eth_halt\n"); -} - -int eth_init(bd_t * bis) -{ - uchar enetaddr[6]; - u32 helpreg; - debug ("EMAC Initialization Started\n\r"); - - if (emac.isstarted) { - puts("Emac is started\n"); - return 0; - } - - memset (&emac, 0, sizeof (xemac)); - - emac.baseaddress = XILINX_EMAC_BASEADDR; - - /* Setting up FIFOs */ - emac.recvfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_RXREG_OFFSET; - emac.recvfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_RXDATA_OFFSET; - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - emac.sendfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_TXREG_OFFSET; - emac.sendfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_TXDATA_OFFSET; - out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - /* Reset the entire IPIF */ - out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, - XIIF_V123B_RESET_MASK); - - /* Stopping EMAC for setting up MAC */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - /* Set the device station address high and low registers */ - helpreg = (enetaddr[0] << 8) | enetaddr[1]; - out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); - helpreg = (enetaddr[2] << 24) | (enetaddr[3] << 16) | - (enetaddr[4] << 8) | enetaddr[5]; - out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); - - helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | - XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | - XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - emac.isstarted = 1; - - /* Enable the transmitter, and receiver */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); - helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - printf("EMAC Initialization complete\n\r"); - return 0; -} - -int eth_send(volatile void *ptr, int len) -{ - u32 intrstatus; - u32 xmitstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 *wordbuffer = (u32 *) ptr; - - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - /* - * Check for overruns and underruns for the transmit status and length - * FIFOs and make sure the send packet FIFO is not deadlocked. - * Any of these conditions is bad enough that we do not want to - * continue. The upper layer software should reset the device to resolve - * the error. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - debug ("Transmitting overrun error\n"); - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - debug ("Transmitting underrun error\n"); - return 0; - } else if (in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { - debug ("Transmitting fifo error\n"); - return 0; - } - - /* - * Before writing to the data FIFO, make sure the length FIFO is not - * full. The data FIFO might not be full yet even though the length FIFO - * is. This avoids an overrun condition on the length FIFO and keeps the - * FIFOs in sync. - * - * Clear the latched LFIFO_FULL bit so next time around the most - * current status is represented - */ - if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); - debug ("Fifo is full\n"); - return 0; - } - - /* get the count of how many words may be inserted into the FIFO */ - fifocount = in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - wordcount = len >> 2; - extrabytecount = len & 0x3; - - if (fifocount < wordcount) { - debug ("Sending packet is larger then size of FIFO\n"); - return 0; - } - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); - } - if (extrabytecount > 0) { - u32 lastword = 0; - u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); - - if (extrabytecount == 1) { - lastword = extrabytesbuffer[0] << 24; - } else if (extrabytecount == 2) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16; - } else if (extrabytecount == 3) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16 | - extrabytesbuffer[2] << 8; - } - out_be32 (emac.sendfifo.databaseaddress, lastword); - } - - /* Loop on the MAC's status to wait for any pause to complete */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - /* Clear the pause status from the transmit status register */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_PAUSE_MASK); - } - - /* - * Set the MAC's transmit packet length register to tell it to transmit - */ - out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); - - /* - * Loop on the MAC's status to wait for the transmit to complete. - * The transmit status is in the FIFO when the XMIT_DONE bit is set. - */ - do { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - } - while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); - - xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); - - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - debug ("Transmitting overrun error\n"); - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - debug ("Transmitting underrun error\n"); - return 0; - } - - /* Clear the interrupt status register of transmit statuses */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_ALL_MASK); - - /* - * Collision errors are stored in the transmit status register - * instead of the interrupt status register - */ - if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || - (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { - debug ("Transmitting collision error\n"); - return 0; - } - return 1; -} - -int eth_rx(void) -{ - u32 pktlength; - u32 intrstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 lastword; - u8 *extrabytesbuffer; - - if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) - & XPF_DEADLOCK_MASK) { - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - debug ("Receiving FIFO deadlock\n"); - return 0; - } - - /* - * Get the interrupt status to know what happened (whether an error - * occurred and/or whether frames have been received successfully). - * When clearing the intr status register, clear only statuses that - * pertain to receive. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - /* - * Before reading from the length FIFO, make sure the length FIFO is not - * empty. We could cause an underrun error if we try to read from an - * empty FIFO. - */ - if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { - /* debug ("Receiving FIFO is empty\n"); */ - return 0; - } - - /* - * Determine, from the MAC, the length of the next packet available - * in the data FIFO (there should be a non-zero length here) - */ - pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); - if (!pktlength) { - return 0; - } - - /* - * Write the RECV_DONE bit in the status register to clear it. This bit - * indicates the RPLR is non-empty, and we know it's set at this point. - * We clear it so that subsequent entry into this routine will reflect - * the current status. This is done because the non-empty bit is latched - * in the IPIF, which means it may indicate a non-empty condition even - * though there is something in the FIFO. - */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - XEM_EIR_RECV_DONE_MASK); - - fifocount = in_be32 (emac.recvfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - - if ((fifocount * 4) < pktlength) { - debug ("Receiving FIFO is smaller than packet size.\n"); - return 0; - } - - wordcount = pktlength >> 2; - extrabytecount = pktlength & 0x3; - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - etherrxbuff[fifocount] = - in_be32 (emac.recvfifo.databaseaddress); - } - - /* - * if there are extra bytes to handle, read the last word from the FIFO - * and insert the extra bytes into the buffer - */ - if (extrabytecount > 0) { - extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); - - lastword = in_be32 (emac.recvfifo.databaseaddress); - - /* - * one extra byte in the last word, put the byte into the next - * location of the buffer, bytes in a word of the FIFO are - * ordered from most significant byte to least - */ - if (extrabytecount == 1) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - } else if (extrabytecount == 2) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - } else if (extrabytecount == 3) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - extrabytesbuffer[2] = (u8) (lastword >> 8); - } - } - NetReceive((uchar *)etherrxbuff, pktlength); - return 1; -} diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 64eb0e0..3fd2211 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -58,10 +58,7 @@ /*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/

/* ethernet */ -#ifdef XILINX_EMAC_BASEADDR - #define CONFIG_XILINX_EMAC 1 - #define CONFIG_SYS_ENET -#elif XILINX_EMACLITE_BASEADDR +#ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 #define CONFIG_SYS_ENET #elif XILINX_LLTEMAC_BASEADDR

monstr@monstr.eu wrote:

From: Michal Simek monstr@monstr.eu

Here are two major changes which should go together. First is adding LL Temac driver to u-boot and the second is changing Emaclite to NET_MULTI api.

There are some changes for proper initialization too.

Signed-off-by: Michal Simek monstr@monstr.eu Signed-off-by: Michal Simek michal.simek@petalogix.com

---

.../xilinx/microblaze-generic/microblaze-generic.c | 16 + drivers/net/Makefile | 1 + drivers/net/xilinx_emaclite.c | 42 ++- drivers/net/xilinx_ll_temac.c | 567 ++++++++++++++++++++ include/configs/microblaze-generic.h | 2 + include/netdev.h | 2 + lib_microblaze/board.c | 21 +- 7 files changed, 634 insertions(+), 17 deletions(-) create mode 100644 drivers/net/xilinx_ll_temac.c

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index f388b77..4ad9eb6 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -27,6 +27,7 @@

#include <common.h> #include <config.h> +#include <netdev.h> #include <asm/microblaze_intc.h> #include <asm/asm.h>

@@ -67,3 +68,18 @@ void fsl_init2 (void) { NULL); } #endif

+int board_eth_init(bd_t *bis) +{

• /*

• * This board either has PCI NICs or uses the CPU's TSECs
  

• * pci_eth_init() will return 0 if no NICs found, so in that case
  

• * returning -1 will force cpu_eth_init() to be called.
  

• */
  
  

Huh? I don't see a call to pci_eth_init() and don't see you using TSECs either.... C&P error, maybe?

+#ifdef CONFIG_XILINX_EMACLITE

• return xilinx_emaclite_initialize(bis);

+#endif +#ifdef CONFIG_XILINX_LL_TEMAC

• return xilinx_ll_temac_initialize(bis);

+#endif +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1c6e402..98cb3a1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,6 +74,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index cf39573..e437d16 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -25,6 +25,7 @@ #include <common.h> #include <net.h> #include <config.h> +#include <malloc.h> #include <asm/io.h>

#undef DEBUG @@ -79,7 +80,7 @@ static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; static u8 emacaddr[ENET_ADDR_LENGTH]; #endif

-void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) +static void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)

While you're in here, can you change 'unsigned' to either 'unsigned int' or 'u32'? Apply globally.

{ unsigned int i; u32 alignbuffer; @@ -106,7 +107,7 @@ void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) } }

-void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) +static void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) { unsigned i; u32 alignbuffer; @@ -133,12 +134,12 @@ void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) *to32ptr++ = alignbuffer; }

-void eth_halt (void) +static void emaclite_halt(struct eth_device *dev) { debug ("eth_halt\n"); }

-int eth_init (bd_t * bis) +static int emaclite_init(struct eth_device *dev, bd_t *bis) { uchar enetaddr[6];

@@ -193,7 +194,7 @@ int eth_init (bd_t * bis) return 0; }

-int xemaclite_txbufferavailable (xemaclite * instanceptr) +static int xemaclite_txbufferavailable (xemaclite * instanceptr) { u32 reg; u32 txpingbusy; @@ -215,8 +216,8 @@ int xemaclite_txbufferavailable (xemaclite * instanceptr) return (!(txpingbusy && txpongbusy)); }

-int eth_send (volatile void *ptr, int len) {

+static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) +{ unsigned int reg; unsigned int baseaddress;

@@ -292,7 +293,8 @@ int eth_send (volatile void *ptr, int len) { return 0; }

-int eth_rx (void)

+static int emaclite_recv(struct eth_device *dev) { unsigned int length; unsigned int reg; @@ -352,3 +354,27 @@ int eth_rx (void) return 1;

}

+int xilinx_emaclite_initialize (bd_t *bis) +{

• struct eth_device *dev;
• dev = malloc(sizeof(*dev));
• if (dev == NULL)

• hang();
  

• memset(dev, 0, sizeof(*dev));
• sprintf(dev->name, "Xilinx Emaclite");
• dev->iobase = 0;
• dev->priv = 0;
• dev->init = emaclite_init;
• dev->halt = emaclite_halt;
• dev->send = emaclite_send;
• dev->recv = emaclite_recv;
• eth_register(dev);
• return 0;

+}

These are pretty basic changes and don't support having more than one device. Is that appropriate for this architecture (I know nothing about microblaze)? I'd prefer for the device to contain state and device information (an object, if you will), but if there can only be one emaclite on an FPGA, then I guess this is OK.

diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c new file mode 100644 index 0000000..4b42b06 --- /dev/null +++ b/drivers/net/xilinx_ll_temac.c @@ -0,0 +1,567 @@ +/*

• • Xilinx xps_ll_temac ethernet driver for u-boot
• • Author: Yoshio Kashiwagi kashiwagi@co-nss.co.jp
• • Copyright (C) 2008 Nissin Systems Co.,Ltd.
• • March 2008 created
• • Copyright (C) 2008 - 2009 Michal Simek monstr@monstr.eu
• • June 2008 Microblaze optimalization, FIFO mode support
• • This program is free software; you can redistribute it and/or modify it
• • under the terms of the GNU General Public License as published by the
• • Free Software Foundation; either version 2 of the License, or (at your
• • option) any later version.
• */

+#include <config.h> +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h>

+#ifdef XILINX_LLTEMAC_FIFO_BASEADDR +# define FIFO_MODE 1 +#elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR +# define SDMA_MODE 1 +#else +# error Unsupported mode

Can you make this error more descriptive please (at least mention which driver)

+#endif

+#undef ETH_HALTING

+#ifdef SDMA_MODE +/* XPS_LL_TEMAC SDMA registers definition */ +# define TX_NXTDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x00) +# define TX_CURBUF_ADDR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x04) +# define TX_CURBUF_LENGTH (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x08) +# define TX_CURDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x0c) +# define TX_TAILDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x10) +# define TX_CHNL_CTRL (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x14) +# define TX_IRQ_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x18) +# define TX_CHNL_STS (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x1c)

+# define RX_NXTDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x20) +# define RX_CURBUF_ADDR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x24) +# define RX_CURBUF_LENGTH (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x28) +# define RX_CURDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x2c) +# define RX_TAILDESC_PTR (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x30) +# define RX_CHNL_CTRL (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x34) +# define RX_IRQ_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x38) +# define RX_CHNL_STS (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x3c)

+# define DMA_CONTROL_REG (XILINX_LLTEMAC_SDMA_CTRL_BASEADDR + 0x40) +#endif

+/* XPS_LL_TEMAC direct registers definition */ +#define TEMAC_RAF0 (XILINX_LLTEMAC_BASEADDR + 0x00) +#define TEMAC_TPF0 (XILINX_LLTEMAC_BASEADDR + 0x04) +#define TEMAC_IFGP0 (XILINX_LLTEMAC_BASEADDR + 0x08) +#define TEMAC_IS0 (XILINX_LLTEMAC_BASEADDR + 0x0c) +#define TEMAC_IP0 (XILINX_LLTEMAC_BASEADDR + 0x10) +#define TEMAC_IE0 (XILINX_LLTEMAC_BASEADDR + 0x14)

+#define TEMAC_MSW0 (XILINX_LLTEMAC_BASEADDR + 0x20) +#define TEMAC_LSW0 (XILINX_LLTEMAC_BASEADDR + 0x24) +#define TEMAC_CTL0 (XILINX_LLTEMAC_BASEADDR + 0x28) +#define TEMAC_RDY0 (XILINX_LLTEMAC_BASEADDR + 0x2c)

Please put these registers in a struct and access it using io accessors (writel, writew etc.). Put the base addresses either in dev->iobase or in a priv data structure pointed to by dev->priv

+#define XTE_RSE_MIIM_RR_MASK 0x0002 +#define XTE_RSE_MIIM_WR_MASK 0x0004 +#define XTE_RSE_CFG_RR_MASK 0x0020 +#define XTE_RSE_CFG_WR_MASK 0x0040

+/* XPS_LL_TEMAC indirect registers offset definition */

+#define RCW0 0x200 +#define RCW1 0x240 +#define TC 0x280 +#define FCC 0x2c0 +#define EMMC 0x300 +#define PHYC 0x320 +#define MC 0x340 +#define UAW0 0x380 +#define UAW1 0x384 +#define MAW0 0x388 +#define MAW1 0x38c +#define AFM 0x390 +#define TIS 0x3a0 +#define TIE 0x3a4 +#define MIIMWD 0x3b0 +#define MIIMAI 0x3b4

+#define CNTLREG_WRITE_ENABLE_MASK 0x8000 +#define CNTLREG_EMAC1SEL_MASK 0x0400 +#define CNTLREG_ADDRESSCODE_MASK 0x03ff

+#define MDIO_ENABLE_MASK 0x40 +#define MDIO_CLOCK_DIV_MASK 0x3F +#define MDIO_CLOCK_DIV_100MHz 0x28

+#define ETHER_MTU 1520

+#ifdef SDMA_MODE +/* CDMAC descriptor status bit definitions */ +# define BDSTAT_ERROR_MASK 0x80 +# define BDSTAT_INT_ON_END_MASK 0x40 +# define BDSTAT_STOP_ON_END_MASK 0x20 +# define BDSTAT_COMPLETED_MASK 0x10 +# define BDSTAT_SOP_MASK 0x08 +# define BDSTAT_EOP_MASK 0x04 +# define BDSTAT_CHANBUSY_MASK 0x02 +# define BDSTAT_CHANRESET_MASK 0x01

+/* SDMA Buffer Descriptor */

+typedef struct cdmac_bd_t {

• struct cdmac_bd_t *next_p;
• unsigned char *phys_buf_p;
• unsigned long buf_len;
• unsigned char stat;
• unsigned char app1_1;
• unsigned short app1_2;
• unsigned long app2;
• unsigned long app3;
• unsigned long app4;
• unsigned long app5;

+} cdmac_bd __attribute((aligned(32))) ;

+static cdmac_bd tx_bd; +static cdmac_bd rx_bd; +#endif

+#ifdef FIFO_MODE +typedef struct ll_fifo_s {

• int isr; /* Interrupt Status Register 0x0 */
• int ier; /* Interrupt Enable Register 0x4 */
• int tdfr; /* Transmit data FIFO reset 0x8 */
• int tdfv; /* Transmit data FIFO Vacancy 0xC */
• int tdfd; /* Transmit data FIFO 32bit wide data write port 0x10 */
• int tlf; /* Write Transmit Length FIFO 0x14 */
• int rdfr; /* Read Receive data FIFO reset 0x18 */
• int rdfo; /* Receive data FIFO Occupancy 0x1C */
• int rdfd; /* Read Receive data FIFO 32bit wide data read port 0x20 */
• int rlf; /* Read Receive Length FIFO 0x24 */
• int llr; /* Read LocalLink reset 0x28 */

+} ll_fifo_s;

+ll_fifo_s *ll_fifo = (ll_fifo_s *) (XILINX_LLTEMAC_FIFO_BASEADDR); +#endif

+static unsigned char tx_buffer[ETHER_MTU] __attribute((aligned(32))); +static unsigned char rx_buffer[ETHER_MTU] __attribute((aligned(32)));

+struct xps_ll_temac_private {

• int idx;
• unsigned char dev_addr[6];

+};

+#ifdef DEBUG +/* undirect hostif write to ll_temac */ +static void xps_ll_temac_hostif_set(int emac, int phy_addr,

• 			int reg_addr, int phy_data)
  

+{

• out_be32((u32 *)TEMAC_LSW0, phy_data);
• out_be32((u32 *)TEMAC_CTL0, CNTLREG_WRITE_ENABLE_MASK | MIIMWD);
• out_be32((u32 *)TEMAC_LSW0, (phy_addr << 5) | (reg_addr));
• out_be32((u32 *)TEMAC_CTL0, \

• 	CNTLREG_WRITE_ENABLE_MASK | MIIMAI | (emac << 10));
  

• while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_MIIM_WR_MASK));

+} +#endif

+/* undirect hostif read from ll_temac */ +static unsigned int xps_ll_temac_hostif_get(int emac, int phy_addr, int reg_addr) +{

• out_be32((u32 *)TEMAC_LSW0, (phy_addr << 5) | (reg_addr));
• out_be32((u32 *)TEMAC_CTL0, MIIMAI | (emac << 10));
• while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_MIIM_RR_MASK));
• return in_be32((u32 *)TEMAC_LSW0);

+}

+/* undirect write to ll_temac */ +static void xps_ll_temac_indirect_set(int emac, int reg_offset, int reg_data) +{

• out_be32((u32 *)TEMAC_LSW0, reg_data);
• out_be32((u32 *)TEMAC_CTL0, \

• 	CNTLREG_WRITE_ENABLE_MASK | (emac << 10) | reg_offset);
  

• while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_CFG_WR_MASK));

+}

+/* undirect read from ll_temac */ +static int xps_ll_temac_indirect_get(int emac, int reg_offset) +{

• out_be32((u32 *)TEMAC_CTL0, (emac << 10) | reg_offset);
• while(! (in_be32((u32 *)TEMAC_RDY0) & XTE_RSE_CFG_RR_MASK));
• return in_be32((u32 *)TEMAC_LSW0);

+}

+#ifdef DEBUG +/* read from phy */ +static void read_phy_reg (int phy_addr) +{

• int j, result;
• printf("phy%d ",phy_addr);
• for ( j = 0; j < 32; j++) {

• result = xps_ll_temac_hostif_get(0, phy_addr, j);
  

• printf("%d: 0x%x ", j, result);
  

• }
• puts("\n");

+} +#endif

+static int phy_addr = -1; +static int link = 0;

+/* setting ll_temac and phy to proper setting */ +static int xps_ll_temac_phy_ctrl(void) +{

• int i;
• unsigned int result;
• unsigned retries = 10;
• if(link == 1)

• return 1; /* link is setup */
  

• /* wait for link up */
• while (retries-- &&

• ((xps_ll_temac_hostif_get(0, phy_addr, 1) & 0x24) == 0x24))
  

• ;
  

• if(phy_addr == -1) {

• for(i = 31; i >= 0; i--) {
  

• 	result = xps_ll_temac_hostif_get(0, i, 1);
  

• 	if((result & 0x0ffff) != 0x0ffff) {
  

+#ifdef DEBUG

• 		printf ("phy %x result %x\n", i, result);
  

+#endif

Please use debug() instead. Apply globally.

• 		phy_addr = i;
  

• 		break;
  

• 	}
  

• }
  

• }
• /* get PHY id */
• i = (xps_ll_temac_hostif_get(0, phy_addr, 2) << 16) | \

• xps_ll_temac_hostif_get(0, phy_addr, 3);
  

+#ifdef DEBUG

• printf("LL_TEMAC: Phy ID 0x%x\n", i);

+#endif

+#ifdef DEBUG

• xps_ll_temac_hostif_set(0, 0, 0, 0x8000); /* phy reset */

+#endif

• /* FIXME this part will be replaced by PHY lib */
• /* s3e boards */
• if (i == 0x7c0a3) {

• xps_ll_temac_indirect_set(0, EMMC, 0x40000000); /* 100BASE-T/FD */
  

• link = 1;
  

• return 1;
  

• }
• /* Marwell 88e1111 id - ml50x */
• if (i == 0x1410cc2) {

• result = xps_ll_temac_hostif_get(0, phy_addr, 5);
  

• if((result & 0x8000) == 0x8000) {
  

• 	xps_ll_temac_indirect_set(0, EMMC, 0x80000000);
  

• 	printf("1000BASE-T/FD\n");
  

• 	link = 1;
  

• } else if((result & 0x4000) == 0x4000) {
  

• 	xps_ll_temac_indirect_set(0, EMMC, 0x40000000);
  

• 	printf("100BASE-T/FD\n");
  

• 	link = 1;
  

• } else {
  

• 	printf("Unsupported mode\n");
  

• 	link = 0;
  

• }
  

• return 1;
  

• }
• return 0;

+}

+#ifdef SDMA_MODE +/* bd init */ +static void xps_ll_temac_bd_init(void) +{

• memset((void *)&tx_bd, 0, sizeof(cdmac_bd));
• memset((void *)&rx_bd, 0, sizeof(cdmac_bd));
• rx_bd.phys_buf_p = &rx_buffer[0];
• rx_bd.next_p = &rx_bd;
• rx_bd.buf_len = ETHER_MTU;
• flush_cache((u32)&rx_bd, sizeof(cdmac_bd));
• out_be32((u32 *)RX_CURDESC_PTR, (u32)&rx_bd);
• out_be32((u32 *)RX_TAILDESC_PTR, (u32)&rx_bd);
• out_be32((u32 *)RX_NXTDESC_PTR, (u32)&rx_bd); /* setup first fd */
• tx_bd.phys_buf_p = &tx_buffer[0];
• tx_bd.next_p = &tx_bd;
• flush_cache((u32)&tx_bd, sizeof(cdmac_bd));
• out_be32((u32 *)TX_CURDESC_PTR, (u32)&tx_bd);

+} +#endif

+#ifdef SDMA_MODE +static int xps_ll_temac_send_sdma(unsigned char *buffer, int length) +{

• if( xps_ll_temac_phy_ctrl() == 0)

• return 0;
  

• memcpy (tx_buffer, buffer, length);
• flush_cache ((u32)tx_buffer, length);
• tx_bd.stat = BDSTAT_SOP_MASK | BDSTAT_EOP_MASK | BDSTAT_STOP_ON_END_MASK;
• tx_bd.buf_len = length;
• flush_cache ((u32)&tx_bd, sizeof(cdmac_bd));
• out_be32((u32 *)TX_CURDESC_PTR, (u32)&tx_bd);
• out_be32((u32 *)TX_TAILDESC_PTR, (u32)&tx_bd); /* DMA start */
• do {

• flush_cache ((u32)&tx_bd, sizeof(cdmac_bd));
  

• } while(!(((volatile int)tx_bd.stat) & BDSTAT_COMPLETED_MASK));
• return length;

+}

+static int xps_ll_temac_recv_sdma(void) +{

• int length;
• flush_cache ((u32)&rx_bd, sizeof(cdmac_bd));
• if(!(rx_bd.stat & BDSTAT_COMPLETED_MASK)) {

• return 0;
  

• }
• length = rx_bd.app5;
• flush_cache ((u32)rx_bd.phys_buf_p, length);
• rx_bd.buf_len = ETHER_MTU;
• rx_bd.stat = 0;
• rx_bd.app5 = 0;
• flush_cache ((u32)&rx_bd, sizeof(cdmac_bd));
• out_be32((u32 *)RX_TAILDESC_PTR, (u32)&rx_bd);
• if(length > 0) {

• NetReceive(rx_bd.phys_buf_p, length);
  

• }
• return length;

+} +#endif

+#ifdef FIFO_MODE +static void debugll(int count) +{

• printf ("%d fifo isr 0x%08x, fifo_ier 0x%08x, fifo_rdfr 0x%08x, fifo_rdfo 0x%08x fifo_rlr 0x%08x\n",count, ll_fifo->isr, \

line's way too long

• ll_fifo->ier, ll_fifo->rdfr, ll_fifo->rdfo, ll_fifo->rlf);

+}

+static int xps_ll_temac_send_fifo(unsigned char *buffer, int length) +{

• u32 *buf = buffer;
• u32 len, i, val;
• len = (length / 4) + 1;
• for (i = 0; i < len; i++) {

• val = *buf++;
  

• ll_fifo->tdfd = val;
  

• }
• ll_fifo->tlf = length;
• return length;

+}

+static int xps_ll_temac_recv_fifo() +{

• int len, len2, i, val;
• int *buf;
• buf = &rx_buffer;
• if (ll_fifo->isr & 0x04000000 ) {

• ll_fifo->isr = 0xffffffff; /* reset isr */
  

• /* while (ll_fifo->isr); */
  

• len = ll_fifo->rlf & 0x7FF;
  

• len2 = (len / 4) + 1;
  

• for (i = 0; i < len2; i++) {
  

• 	val = ll_fifo->rdfd;
  

• 	*buf++ = val ;
  

• }
  

• /* debugll(1); */
  

• NetReceive (&rx_buffer, len);
  

• }
• return 0;

+} +#endif

+/* setup mac addr */ +static int xps_ll_temac_addr_setup(struct xps_ll_temac_private * lp) +{

• char * env_p;
• char * end;
• int i, val;
• env_p = getenv("ethaddr");
• if (env_p == NULL) {

• printf("cannot get enviroment for \"ethaddr\".\n");
  
  

s/enviroment/environment/

• return -1;
  

• }

Also, your driver does'nt need to get the address from the environment. The net library fills dev->enetaddr in eth_initialize().

• for (i = 0; i < 6; i++) {

• lp->dev_addr[i] = env_p ? simple_strtoul(env_p, &end, 16) : 0;
  

• if (env_p) env_p = (*end) ? end + 1 : end;
  

• }
• /* set up unicast MAC address filter */
• val = ((lp->dev_addr[3] << 24) | (lp->dev_addr[2] << 16) |

• (lp->dev_addr[1] << 8) | (lp->dev_addr[0] ));
  

• xps_ll_temac_indirect_set(0, UAW0, val);
• val = (lp->dev_addr[5] << 8) | lp->dev_addr[4] ;
• xps_ll_temac_indirect_set(0, UAW1, val);
• return 0;

+}

+static int xps_ll_temac_init(struct eth_device *dev, bd_t *bis) +{

• struct xps_ll_temac_private *lp = (struct xps_ll_temac_private *)dev->priv;

+#ifdef SDMA_MODE

• xps_ll_temac_bd_init();

+#endif +#ifdef FIFO_MODE

• ll_fifo->tdfr = 0x000000a5; /* set fifo lenght */

s/lenght/length/

• ll_fifo->rdfr = 0x000000a5;
• /* ll_fifo->isr = 0x0; */
• /* ll_fifo->ier = 0x0; */

+#endif

• xps_ll_temac_indirect_set(0, MC, MDIO_ENABLE_MASK | MDIO_CLOCK_DIV_100MHz);
• xps_ll_temac_addr_setup(lp);
• xps_ll_temac_indirect_set(0, AFM, 0x00000000); /* Promiscuos mode disable */
• xps_ll_temac_indirect_set(0, RCW1, 0x10000000); /* Enable Receiver */
• xps_ll_temac_indirect_set(0, TC, 0x10000000); /* Enable Transmitter */
• return 0;

+}

+static void xps_ll_temac_halt(void) +{ +#ifdef ETH_HALTING

• xps_ll_temac_indirect_set(0, RCW1, 0x00000000); /* Disable Receiver */
• xps_ll_temac_indirect_set(0, TC, 0x00000000); /* Disable Transmitter */

+#ifdef SDMA_MODE

• out_be32((u32 *)DMA_CONTROL_REG, 0x00000001);
• while(in_be32((u32 *)DMA_CONTROL_REG) & 1);

+#endif +#ifdef FIFO_MODE

• /* reset fifos */

+#endif +#endif +}

+/* halt device */ +static void ll_temac_halt(struct eth_device *dev) +{

• link = 0;
• xps_ll_temac_halt();

+}

+static int ll_temac_init(struct eth_device *dev, bd_t *bis) +{

• static int first = 1;
• struct xps_ll_temac_private *lp;

+#if DEBUG

• int i;

+#endif

• if(!first)

• return 0;
  

• first = 0;
• dev = (struct eth_device *) calloc(1, sizeof(struct eth_device));
• if (NULL == dev)

• return 0;
  

• lp = (struct xps_ll_temac_private *) calloc(1, sizeof(struct xps_ll_temac_private));
• if (lp == NULL)

• return 0;
  

• dev->priv = lp;

priv should be set up in initialize()

• sprintf(dev->name, "eth0");

Name should be set up in initialize()

• xps_ll_temac_init(dev, bis);
• printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",

• dev->name, 0, XILINX_LLTEMAC_BASEADDR);
  

+#if DEBUG

• for(i = 0;i < 32;i++) {

• read_phy_reg(i);
  

• }

+#endif

• xps_ll_temac_phy_ctrl();
• return 1;

+}

+static int ll_temac_send(struct eth_device *dev, volatile void *packet, int length) +{ +#ifdef SDMA_MODE

• return xps_ll_temac_send_sdma((unsigned char *)packet, length);

+#endif +#ifdef FIFO_MODE

• return xps_ll_temac_send_fifo((unsigned char *)packet, length);

+#endif +}

+static int ll_temac_recv(struct eth_device *dev) +{ +#ifdef SDMA_MODE

• return xps_ll_temac_recv_sdma();

+#endif +#ifdef FIFO_MODE

• return xps_ll_temac_recv_fifo();

+#endif +}

+int xilinx_ll_temac_initialize (bd_t *bis) +{

• struct eth_device *dev;
• dev = malloc(sizeof(*dev));
• if (dev == NULL)

• hang();
  

• memset(dev, 0, sizeof(*dev));
• sprintf(dev->name, "Xilinx LL TEMAC");
• dev->iobase = 0;
• dev->priv = 0;
• dev->init = ll_temac_init;
• dev->halt = ll_temac_halt;
• dev->send = ll_temac_send;
• dev->recv = ll_temac_recv;
• eth_register(dev);
• return 0;

+}

Same comment as the other driver - this only allows a single instance. Please consider encapsulating things like base addresses in the dev struct, then you can have multiple instances.

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 72715f6..89e4bcc 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -232,8 +232,10 @@

#ifndef CONFIG_SYS_ENET #undef CONFIG_CMD_NET

• #undef CONFIG_NET_MULTI

#else #define CONFIG_CMD_PING

• #define CONFIG_NET_MULTI

#endif

#if defined(CONFIG_SYSTEMACE) diff --git a/include/netdev.h b/include/netdev.h index 50329a3..8da0110 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,6 +78,8 @@ int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); +int xilinx_emaclite_initialize (bd_t *bis); +int xilinx_ll_temac_initialize(bd_t *bis); int sh_eth_initialize(bd_t *bis); int dm9000_initialize(bd_t *bis);

diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index cfed5fe..8d17b03 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -30,6 +30,7 @@ #include <timestamp.h> #include <version.h> #include <watchdog.h> +#include <net.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -41,10 +42,6 @@ extern int gpio_init (void); #ifdef CONFIG_SYS_INTC_0 extern int interrupts_init (void); #endif -#if defined(CONFIG_CMD_NET) -extern int eth_init (bd_t * bis); -extern int getenv_IPaddr (char *); -#endif

/*

• Begin and End of memory area for malloc(), and current "brk"

@@ -168,14 +165,20 @@ void board_init (void) } #endif

• /* relocate environment function pointers etc. */
• env_relocate ();

#if defined(CONFIG_CMD_NET) /* IP Address */

• bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
• eth_init (bd);

-#endif

• bd->bi_ip_addr = getenv_IPaddr("ipaddr");

• /* relocate environment function pointers etc. */
• env_relocate ();

• printf("Net: ");
• eth_initialize(gd->bd);
• uchar enetaddr[6];
• eth_getenv_enetaddr("ethaddr", enetaddr);
• printf("MAC: %pM\n", enetaddr);

+#endif

/* main_loop */ for (;;) {

regards, Ben