This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/ppc4xx/Kconfig | 8 -- board/csb272/Kconfig | 9 -- board/csb272/MAINTAINERS | 6 - board/csb272/Makefile | 9 -- board/csb272/csb272.c | 171 ------------------------ board/csb272/init.S | 196 ---------------------------- board/csb472/Kconfig | 9 -- board/csb472/MAINTAINERS | 6 - board/csb472/Makefile | 9 -- board/csb472/csb472.c | 138 -------------------- board/csb472/init.S | 192 --------------------------- configs/csb272_defconfig | 4 - configs/csb472_defconfig | 4 - include/configs/csb272.h | 282 ---------------------------------------- include/configs/csb472.h | 281 --------------------------------------- 15 files changed, 1324 deletions(-) delete mode 100644 board/csb272/Kconfig delete mode 100644 board/csb272/MAINTAINERS delete mode 100644 board/csb272/Makefile delete mode 100644 board/csb272/csb272.c delete mode 100644 board/csb272/init.S delete mode 100644 board/csb472/Kconfig delete mode 100644 board/csb472/MAINTAINERS delete mode 100644 board/csb472/Makefile delete mode 100644 board/csb472/csb472.c delete mode 100644 board/csb472/init.S delete mode 100644 configs/csb272_defconfig delete mode 100644 configs/csb472_defconfig delete mode 100644 include/configs/csb272.h delete mode 100644 include/configs/csb472.h

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index e8c0ca0..c6bbe12 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -8,12 +8,6 @@ choice prompt "Target select" optional

-config TARGET_CSB272 - bool "Support csb272" - -config TARGET_CSB472 - bool "Support csb472" - config TARGET_LWMON5 bool "Support lwmon5" select SUPPORT_SPL @@ -176,8 +170,6 @@ source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" -source "board/csb272/Kconfig" -source "board/csb472/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" diff --git a/board/csb272/Kconfig b/board/csb272/Kconfig deleted file mode 100644 index eed04f0..0000000 --- a/board/csb272/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CSB272 - -config SYS_BOARD - default "csb272" - -config SYS_CONFIG_NAME - default "csb272" - -endif diff --git a/board/csb272/MAINTAINERS b/board/csb272/MAINTAINERS deleted file mode 100644 index 4bc95ea..0000000 --- a/board/csb272/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CSB272 BOARD -M: Tolunay Orkun torkun@nextio.com -S: Maintained -F: board/csb272/ -F: include/configs/csb272.h -F: configs/csb272_defconfig diff --git a/board/csb272/Makefile b/board/csb272/Makefile deleted file mode 100644 index 36ec9b6..0000000 --- a/board/csb272/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = csb272.o -obj-y += init.o diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c deleted file mode 100644 index dc2c950..0000000 --- a/board/csb272/csb272.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> -#include <miiphy.h> -#include <asm/ppc4xx-emac.h> - -void sdram_init(void); - -/* - * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator - * - * CLKA output => Epson LCD Controller - * CLKB output => Not Connected - * CLKC output => Ethernet - * CLKD output => UART external clock - * - * Note: these values are obtained from device after init by micromonitor -*/ -uchar pll_fs6377_regs[16] = { - 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80, - 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 }; - -/* - * pll_init: Initialize AMIS IC FS6377-01 PLL - * - * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock - * - */ -int pll_init(void) -{ - i2c_set_bus_num(0); - - return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1, - (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); -} - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /* initialize PLL so UART, LCD, Ethernet clocked at correctly */ - (void) get_clocks(); - pll_init(); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB272\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -phys_size_t initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in arch/powerpc/cpu/ppc4xx - */ - sdram_init(); - - tot_size = 0; - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); - - - return 0; /* success */ -} diff --git a/board/csb272/init.S b/board/csb272/init.S deleted file mode 100644 index bf1d986..0000000 --- a/board/csb272/init.S +++ /dev/null @@ -1,196 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr EBC0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr EBC0_CFGDATA,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr SDRAM0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr SDRAM0_CFGDATA,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x007000c0) - mtdcr CPC0_CR0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, CPC0_CR1 - ori r4, r4, 0x4000 - mtdcr CPC0_CR1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(EBC0_CFG, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F128J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(PB1AP, 0x02869200)*/ - WDCR_EBC(PB1AP, 0x07869200) - WDCR_EBC(PB0CR, 0xfe0bc000) - /******************************************************************** - * Memory Bank 1 (Holtek HT6542B PS/2) initialization - *******************************************************************/ - WDCR_EBC(PB1AP, 0x1f869200) - WDCR_EBC(PB1CR, 0xf0818000) - /******************************************************************** - * Memory Bank 2 (Epson S1D13506) initialization - *******************************************************************/ - WDCR_EBC(PB2AP, 0x05860300) - WDCR_EBC(PB2CR, 0xf045a000) - /******************************************************************** - * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization - *******************************************************************/ - WDCR_EBC(PB3AP, 0x0387d200) - WDCR_EBC(PB3CR, 0xf021c000) - /******************************************************************** - * Memory Bank 4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(PB4AP, 0) - WDCR_EBC(PB4CR, 0) - WDCR_EBC(PB5AP, 0) - WDCR_EBC(PB5CR, 0) - WDCR_EBC(PB6AP, 0) - WDCR_EBC(PB6CR, 0) - WDCR_EBC(PB7AP, 0) - WDCR_EBC(PB7CR, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(SDRAM0_CFG, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) - WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(SDRAM0_TR, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(SDRAM0_RTR, 0x10000000) - /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(SDRAM0_CFG,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig deleted file mode 100644 index 53b1e7a..0000000 --- a/board/csb472/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CSB472 - -config SYS_BOARD - default "csb472" - -config SYS_CONFIG_NAME - default "csb472" - -endif diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS deleted file mode 100644 index 25041ed..0000000 --- a/board/csb472/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CSB472 BOARD -M: Tolunay Orkun torkun@nextio.com -S: Maintained -F: board/csb472/ -F: include/configs/csb472.h -F: configs/csb472_defconfig diff --git a/board/csb472/Makefile b/board/csb472/Makefile deleted file mode 100644 index 5f7e8b5..0000000 --- a/board/csb472/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = csb472.o -obj-y += init.o diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c deleted file mode 100644 index b1de18c..0000000 --- a/board/csb472/csb472.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> -#include <miiphy.h> -#include <asm/ppc4xx-emac.h> - -void sdram_init(void); - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB472\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -phys_size_t initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in arch/powerpc/cpu/ppc4xx - */ - sdram_init(); - - tot_size = 0; - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); - - return 0; /* success */ -} diff --git a/board/csb472/init.S b/board/csb472/init.S deleted file mode 100644 index 7383a70..0000000 --- a/board/csb472/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr EBC0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr EBC0_CFGDATA,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr SDRAM0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr SDRAM0_CFGDATA,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x00c01030) - mtdcr CPC0_CR0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, CPC0_CR1 - ori r4, r4, 0x4000 - mtdcr CPC0_CR1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(EBC0_CFG, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F640J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(PB1AP, 0x03055200)*/ - /*WDCR_EBC(PB1AP, 0x04055200)*/ - WDCR_EBC(PB1AP, 0x08055200) - WDCR_EBC(PB0CR, 0xff87a000) - /******************************************************************** - * Memory Bank 3 (Xilinx XC95144 CPLD) initialization - *******************************************************************/ - /*WDCR_EBC(PB3AP, 0x07869200)*/ - WDCR_EBC(PB3AP, 0x04055200) - WDCR_EBC(PB3CR, 0xf081c000) - /******************************************************************** - * Memory Bank 1,2,4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(PB1AP, 0) - WDCR_EBC(PB1CR, 0) - WDCR_EBC(PB2AP, 0) - WDCR_EBC(PB2CR, 0) - WDCR_EBC(PB4AP, 0) - WDCR_EBC(PB4CR, 0) - WDCR_EBC(PB5AP, 0) - WDCR_EBC(PB5CR, 0) - WDCR_EBC(PB6AP, 0) - WDCR_EBC(PB6CR, 0) - WDCR_EBC(PB7AP, 0) - WDCR_EBC(PB7CR, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(SDRAM0_CFG, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) - WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(SDRAM0_TR, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(SDRAM0_RTR, 0x10000000) - /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(SDRAM0_CFG,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/configs/csb272_defconfig b/configs/csb272_defconfig deleted file mode 100644 index c9cc680..0000000 --- a/configs/csb272_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CSB272=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/csb472_defconfig b/configs/csb472_defconfig deleted file mode 100644 index e46b965..0000000 --- a/configs/csb472_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CSB472=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/csb272.h b/include/configs/csb272.h deleted file mode 100644 index 71cb5df..0000000 --- a/include/configs/csb272.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm fe000000 fe100000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CONFIG_SYS_BASE_BAUD -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMSTART -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) -#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h deleted file mode 100644 index 5bd3867..0000000 --- a/include/configs/csb472.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm ff800000 ff900000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMSTART -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) -#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/prodrive/p3p440/Kconfig | 12 -- board/prodrive/p3p440/MAINTAINERS | 6 - board/prodrive/p3p440/Makefile | 9 -- board/prodrive/p3p440/config.mk | 16 -- board/prodrive/p3p440/init.S | 38 ----- board/prodrive/p3p440/p3p440.c | 177 ---------------------- board/prodrive/p3p440/p3p440.h | 24 --- configs/p3p440_defconfig | 4 - include/configs/p3p440.h | 302 -------------------------------------- 10 files changed, 592 deletions(-) delete mode 100644 board/prodrive/p3p440/Kconfig delete mode 100644 board/prodrive/p3p440/MAINTAINERS delete mode 100644 board/prodrive/p3p440/Makefile delete mode 100644 board/prodrive/p3p440/config.mk delete mode 100644 board/prodrive/p3p440/init.S delete mode 100644 board/prodrive/p3p440/p3p440.c delete mode 100644 board/prodrive/p3p440/p3p440.h delete mode 100644 configs/p3p440_defconfig delete mode 100644 include/configs/p3p440.h

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 883463a..b2e3110 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -130,9 +130,6 @@ config TARGET_MIP405 config TARGET_PIP405 bool "Support PIP405"

-config TARGET_P3P440 - bool "Support p3p440" - config TARGET_XPEDITE1000 bool "Support xpedite1000"

@@ -181,7 +178,6 @@ source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" source "board/pcs440ep/Kconfig" -source "board/prodrive/p3p440/Kconfig" source "board/sbc405/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" diff --git a/board/prodrive/p3p440/Kconfig b/board/prodrive/p3p440/Kconfig deleted file mode 100644 index cf53aac..0000000 --- a/board/prodrive/p3p440/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P3P440 - -config SYS_BOARD - default "p3p440" - -config SYS_VENDOR - default "prodrive" - -config SYS_CONFIG_NAME - default "p3p440" - -endif diff --git a/board/prodrive/p3p440/MAINTAINERS b/board/prodrive/p3p440/MAINTAINERS deleted file mode 100644 index 68fd1a9..0000000 --- a/board/prodrive/p3p440/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -P3P440 BOARD -M: Stefan Roese sr@denx.de -S: Maintained -F: board/prodrive/p3p440/ -F: include/configs/p3p440.h -F: configs/p3p440_defconfig diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile deleted file mode 100644 index d62f75d..0000000 --- a/board/prodrive/p3p440/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = p3p440.o -extra-y += init.o diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk deleted file mode 100644 index f18b097..0000000 --- a/board/prodrive/p3p440/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S deleted file mode 100644 index 35b1afa..0000000 --- a/board/prodrive/p3p440/init.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c deleted file mode 100644 index 929e8eb..0000000 --- a/board/prodrive/p3p440/p3p440.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> - -#include "p3p440.h" - -DECLARE_GLOBAL_DATA_PTR; - -void set_led(int color) -{ - switch (color) { - case LED_OFF: - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED); - break; - - case LED_GREEN: - out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED); - break; - - case LED_RED: - out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN); - break; - - case LED_ORANGE: - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED); - break; - } -} - -static int is_monarch(void) -{ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY); - udelay(1000); - - if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO) - return 0; - else - return 1; -} - -static void wait_for_pci_ready(void) -{ - /* - * Configure EREADY_IO as input - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO); - udelay(1000); - - for (;;) { - if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO) - return; - } - -} - -int board_early_init_f(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * Setup pin multiplexing (GPIO/IRQ...) - *-------------------------------------------------------------------*/ - mtdcr(CPC0_GPIO, 0x03F01F80); - - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); - out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: P3P440"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - - if (is_monarch()) { - puts(", Monarch"); - } else { - puts(", None-Monarch"); - } - - putc('\n'); - - return (0); -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - mtebc(PB1CR, 0); /* disable cs */ - mtebc(PB1AP, 0); - mtebc(PB2CR, 0); /* disable cs */ - mtebc(PB2AP, 0); - mtebc(PB3CR, 0); /* disable cs */ - mtebc(PB3AP, 0); - } - - return 0; -} - -/************************************************************************* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - if (is_monarch()) { - wait_for_pci_ready(); - return 1; /* return 1 for host controller */ - } else { - return 0; /* return 0 for adapter controller */ - } -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h deleted file mode 100644 index a164f95..0000000 --- a/board/prodrive/p3p440/p3p440.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __P3P440_H__ -#define __P3P440_H__ - -#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11) -#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18) -#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20) -#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21) -#define CONFIG_SYS_LED_RED (0x80000000 >> 22) - -#define LED_OFF 1 -#define LED_GREEN 2 -#define LED_RED 3 -#define LED_ORANGE 4 - -long int fixed_sdram(void); - -#endif /* __P3P440_H__ */ diff --git a/configs/p3p440_defconfig b/configs/p3p440_defconfig deleted file mode 100644 index 84e683b..0000000 --- a/configs/p3p440_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_P3P440=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h deleted file mode 100644 index eb14003..0000000 --- a/include/configs/p3p440.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * board/config_p3p440.h - configuration for Prodrive P3P440 - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3P440 1 /* Board is P3P440 */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CONFIG_SDRAM_ECC /* enable ECC support */ -#define CONFIG_SYS_SDRAM_TABLE { \ - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ - {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C RTC - *----------------------------------------------------------------------*/ -#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) for environment - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3p440\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/p3p440/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "unlock=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x1c /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_SNTP - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH0 0xFF800000 -#define CONFIG_SYS_FLASH1 0xFF000000 -#define CONFIG_SYS_FLASH2 0xFE800000 -#define CONFIG_SYS_FLASH3 0xFE000000 -#define CONFIG_SYS_USB 0xF0000000 - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03050200 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x03050200 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03050200 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x03050200 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 7 (USB controller) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015000 -#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/sbc405/Kconfig | 9 - board/sbc405/MAINTAINERS | 6 - board/sbc405/Makefile | 8 - board/sbc405/sbc405.c | 91 ----- board/sbc405/strataflash.c | 774 ---------------------------------------- configs/sbc405_defconfig | 4 - include/configs/sbc405.h | 252 ------------- 8 files changed, 1148 deletions(-) delete mode 100644 board/sbc405/Kconfig delete mode 100644 board/sbc405/MAINTAINERS delete mode 100644 board/sbc405/Makefile delete mode 100644 board/sbc405/sbc405.c delete mode 100644 board/sbc405/strataflash.c delete mode 100644 configs/sbc405_defconfig delete mode 100644 include/configs/sbc405.h

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index e379a6f..16c049e 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -8,9 +8,6 @@ choice prompt "Target select" optional

-config TARGET_SBC405 - bool "Support sbc405" - config TARGET_T3CORP bool "Support t3corp"

@@ -174,7 +171,6 @@ source "board/gdsys/intip/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" -source "board/sbc405/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" source "board/xilinx/ml507/Kconfig" diff --git a/board/sbc405/Kconfig b/board/sbc405/Kconfig deleted file mode 100644 index 4e7e843..0000000 --- a/board/sbc405/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SBC405 - -config SYS_BOARD - default "sbc405" - -config SYS_CONFIG_NAME - default "sbc405" - -endif diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS deleted file mode 100644 index 2abad25..0000000 --- a/board/sbc405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SBC405 BOARD -#M: - -S: Maintained -F: board/sbc405/ -F: include/configs/sbc405.h -F: configs/sbc405_defconfig diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile deleted file mode 100644 index 3f2b0e2..0000000 --- a/board/sbc405/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sbc405.o strataflash.o diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c deleted file mode 100644 index cafc844..0000000 --- a/board/sbc405/sbc405.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> -#include <malloc.h> -#include <spd_sdram.h> - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming sbc405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c deleted file mode 100644 index 7ddc97c..0000000 --- a/board/sbc405/strataflash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CONFIG_SYS_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CONFIG_SYS_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *)dest; - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/configs/sbc405_defconfig b/configs/sbc405_defconfig deleted file mode 100644 index 0bc0ab2..0000000 --- a/configs/sbc405_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_SBC405=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h deleted file mode 100644 index b2adea9..0000000 --- a/include/configs/sbc405.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type "? or help" to get on-line help;echo" - -#define CONFIG_RAMBOOT \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOT \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ - - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ - "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ - "f=0x08 tn=sbc405 o=emac \0" \ - "env_startaddr=FF000000\0" \ - "env_endaddr=FF03FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "uboot_startaddr=FFFC0000\0" \ - "uboot_endaddr=FFFFFFFF\0" \ - "update=tftp ${loadaddr} u-boot.bin;" \ - "protect off ${uboot_startaddr} ${uboot_endaddr};" \ - "era ${uboot_startaddr} ${uboot_endaddr};" \ - "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ - "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ - "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ - "era ${env_startaddr} ${env_endaddr};" \ - "protect on ${env_startaddr} ${env_endaddr}\0" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_ENV_OVERWRITE - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.224 -#define CONFIG_SERVERIP 192.168.193.119 -#define CONFIG_GATEWAYIP 192.168.193.97 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc5xx/Kconfig | 4 - board/cmi/Kconfig | 9 - board/cmi/MAINTAINERS | 6 - board/cmi/Makefile | 8 - board/cmi/README | 84 ------- board/cmi/cmi.c | 57 ----- board/cmi/flash.c | 501 ---------------------------------------- configs/cmi_mpc5xx_defconfig | 6 - include/configs/cmi_mpc5xx.h | 240 ------------------- 9 files changed, 915 deletions(-) delete mode 100644 board/cmi/Kconfig delete mode 100644 board/cmi/MAINTAINERS delete mode 100644 board/cmi/Makefile delete mode 100644 board/cmi/README delete mode 100644 board/cmi/cmi.c delete mode 100644 board/cmi/flash.c delete mode 100644 configs/cmi_mpc5xx_defconfig delete mode 100644 include/configs/cmi_mpc5xx.h

diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig index 5275447..d81bfd2 100644 --- a/arch/powerpc/cpu/mpc5xx/Kconfig +++ b/arch/powerpc/cpu/mpc5xx/Kconfig @@ -8,15 +8,11 @@ choice prompt "Target select" optional

-config TARGET_CMI_MPC5XX - bool "Support cmi_mpc5xx" - config TARGET_PATI bool "Support PATI"

endchoice

-source "board/cmi/Kconfig" source "board/mpl/pati/Kconfig"

endmenu diff --git a/board/cmi/Kconfig b/board/cmi/Kconfig deleted file mode 100644 index 6efe6b1..0000000 --- a/board/cmi/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CMI_MPC5XX - -config SYS_BOARD - default "cmi" - -config SYS_CONFIG_NAME - default "cmi_mpc5xx" - -endif diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS deleted file mode 100644 index 60701bf..0000000 --- a/board/cmi/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CMI BOARD -#M: - -S: Maintained -F: board/cmi/ -F: include/configs/cmi_mpc5xx.h -F: configs/cmi_mpc5xx_defconfig diff --git a/board/cmi/Makefile b/board/cmi/Makefile deleted file mode 100644 index cd3bb0d..0000000 --- a/board/cmi/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := flash.o cmi.o diff --git a/board/cmi/README b/board/cmi/README deleted file mode 100644 index 0edd50a..0000000 --- a/board/cmi/README +++ /dev/null @@ -1,84 +0,0 @@ - -Summary: -======== - -This file contains information about the cmi board configuration. -Please see cmi_mpc5xx_config for further details. The cmi board is -a customer specific board but should work with small modifications -on every board which has a MPC5xx and either a 28F128J3A, -28F320J3A or 28F640J3A Intel flash mounted. - -Board Discription: -================== - -* Motorola MPC555 -* RS232 connection -* Intel flash 28F640J3A -* Micron SRAM 1M -* Altera PLD - -Bootstrap: -========== - -In contrast to the usual boot sequence used in U-Boot, on the -cmi board we don't boot from the external flash directly. -Because of we use a 16-bit flash and don't sample a RCW -from the data bus to set the startup buswidth to 16-bit. -Unfortunatly the default width, sampled from the default RCW -is 32-bit. For this reason we burn the proper RCW into the -internal flash shadow location and boot after power-on or -reset from the internal flash and then branch to 0x02000100 -where the U-Boot reset vector handler is located. - -Memory Map: -=========== - -Memory Map after relocation: - - 0x0000 0000 CONFIG_SYS_SDRAM_BASE - : - 0x000F 9FFF - : - : - 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress) - : - 0x0130 7FFF - : - : - 0x0200 0000 CONFIG_SYS_FLASH_BASE - : - 0x027C FFFF - : - : - 0x0300 0000 PLD_BASE - -Flash Partition: - - 0x0200 0000 Block 0 and 1 contain U-Boot except - : environment - : - 0x0201 FFFF - 0x0202 0000 Block 2 contains environment (.ppcenv) - : - 0x0202 FFFF - -See README file for futher information about U-Boot relocation -and partitioning. - -Tested Features: -================ - -* U-Boot commands: go, loads, loadb, all memory features, printenv, - setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version, - coninfo, help (see configuration file for available commands) - -* Blinking led to indicate boot process - -Added or Changed Files: -======================= - -u-boot-0.2.0/board/cmi/* -u-boot-0.2.0/include/configs/cmi_mpc5xx.h - -Regards, -Martin diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c deleted file mode 100644 index 37028c3..0000000 --- a/board/cmi/cmi.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cmi.c - * - * Discription: For generic board specific functions - * - */ - - -#include <common.h> -#include <mpc5xx.h> - -#define SRAM_SIZE 1024000L /* 1M RAM available*/ - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - -/* - * Check the board - */ -int checkboard(void) -{ - puts ("Board: ### No HW ID - assuming CMI board\n"); - return (0); -} - -/* - * Get RAM size. - */ -phys_size_t initdram(int board_type) -{ - return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ -} - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/cmi/flash.c b/board/cmi/flash.c deleted file mode 100644 index d9986f9..0000000 --- a/board/cmi/flash.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: flash.c - * - * Discription: This Driver is for 28F320J3A, 28F640J3A and - * 28F128J3A Intel flashs working in 16 Bit mode. - * They are single bank flashs. - * - * Most of this code is taken from existing u-boot - * source code. - */ - - -#include <common.h> -#include <mpc5xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_ID_MASK 0xFFFF -#define FLASH_BLOCK_SIZE 0x00010000 -#define FLASH_CMD_READ_ID 0x0090 -#define FLASH_CMD_RESET 0x00ff -#define FLASH_CMD_BLOCK_ERASE 0x0020 -#define FLASH_CMD_ERASE_CONFIRM 0x00D0 -#define FLASH_CMD_CLEAR_STATUS 0x0050 -#define FLASH_CMD_SUSPEND_ERASE 0x00B0 -#define FLASH_CMD_WRITE 0x0040 -#define FLASH_CMD_PROTECT 0x0060 -#define FLASH_CMD_PROTECT_SET 0x0001 -#define FLASH_CMD_PROTECT_CLEAR 0x00D0 -#define FLASH_STATUS_DONE 0x0080 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Local function prototypes - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/* - * Initialize flash - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ -#if 1 - debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); -#endif - size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id, - size_b0, size_b0<<20); - } - - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - return size_b0; -} - -/* - * Compute start adress of each sector (block) - */ - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * FLASH_BLOCK_SIZE; - } - return; - - default: - printf ("Don't know sector offsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/* - * Print flash information - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * Get size of flash in bytes. - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - vu_short value; - - /* Read Manufacturer ID */ - addr[0] = FLASH_CMD_READ_ID; - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - - return (info->size); -} - - -/* - * Erase unprotected sectors - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef DEBUG - printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); -#endif - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_BLOCK_ERASE; - *addr = FLASH_CMD_ERASE_CONFIRM; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash erase timeout at address %lx\n", info->start[sect]); - *addr = FLASH_CMD_SUSPEND_ERASE; - *addr = FLASH_CMD_RESET; - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = FLASH_CMD_RESET; - } - } - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int i, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - -} - -/* - * Write 16 bit (short) to flash - */ - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if (!(info->flash_id & FLASH_VENDMASK)) { - return 4; - } - *addr = FLASH_CMD_ERASE_CONFIRM; - *addr = FLASH_CMD_WRITE; - - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* data polling for D7 */ - start = get_timer (0); - - /* wait for error or finish */ - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - - *addr = FLASH_CMD_RESET; - return (0); -} - -/* - * Protects a flash sector - */ - -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - vu_short *addr = (vu_short*)(info->start[sector]); - ulong start; - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_PROTECT; - - if(prot) { - *addr = FLASH_CMD_PROTECT_SET; - } else { - *addr = FLASH_CMD_PROTECT_CLEAR; - } - - /* wait for error or finish */ - start = get_timer (0); - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash protect timeout at address %lx\n", info->start[sector]); - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - /* Set software protect flag */ - info->protect[sector] = prot; - *addr = FLASH_CMD_RESET; - return (0); -} diff --git a/configs/cmi_mpc5xx_defconfig b/configs/cmi_mpc5xx_defconfig deleted file mode 100644 index abebfab..0000000 --- a/configs/cmi_mpc5xx_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_PPC=y -CONFIG_5xx=y -CONFIG_TARGET_CMI_MPC5XX=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h deleted file mode 100644 index d081865..0000000 --- a/include/configs/cmi_mpc5xx.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cmi_mpc5xx.h - * - * Discription: Config header file for cmi - * board using an MPC5xx CPU - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ - -#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */ - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -#define CONFIG_BAUDRATE 57600 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ASKENV - - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_STATUS_LED 1 /* Enable status led */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ - -/* - * Start addresses for the final memory configuration - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */ -#define PLD_BASE 0x03000000 /* PLD */ -#define ANYBUS_BASE 0x03010000 /* Anybus Module */ - -#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ -#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16) -#define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) -#define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE) -#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32) -#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) -#define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) -#define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CONFIG_SYS_DER 0x00000000 - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc5xxx/Kconfig | 4 - board/inka4x0/Kconfig | 9 - board/inka4x0/MAINTAINERS | 6 - board/inka4x0/Makefile | 8 - board/inka4x0/inka4x0.c | 250 --------------------- board/inka4x0/inkadiag.c | 464 --------------------------------------- board/inka4x0/k4h511638c.h | 16 -- board/inka4x0/mt46v16m16-75.h | 16 -- board/inka4x0/mt46v32m16-75.h | 16 -- board/inka4x0/mt48lc16m16a2-75.h | 14 -- configs/inka4x0_defconfig | 4 - include/configs/inka4x0.h | 413 ---------------------------------- 12 files changed, 1220 deletions(-) delete mode 100644 board/inka4x0/Kconfig delete mode 100644 board/inka4x0/MAINTAINERS delete mode 100644 board/inka4x0/Makefile delete mode 100644 board/inka4x0/inka4x0.c delete mode 100644 board/inka4x0/inkadiag.c delete mode 100644 board/inka4x0/k4h511638c.h delete mode 100644 board/inka4x0/mt46v16m16-75.h delete mode 100644 board/inka4x0/mt46v32m16-75.h delete mode 100644 board/inka4x0/mt48lc16m16a2-75.h delete mode 100644 configs/inka4x0_defconfig delete mode 100644 include/configs/inka4x0.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index 526e891..23117ac 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -18,9 +18,6 @@ config TARGET_A4M072 config TARGET_CM5200 bool "Support cm5200"

-config TARGET_INKA4X0 - bool "Support inka4x0" - config TARGET_IPEK01 bool "Support ipek01"

@@ -72,7 +69,6 @@ source "board/a3m071/Kconfig" source "board/a4m072/Kconfig" source "board/cm5200/Kconfig" source "board/ifm/o2dnt2/Kconfig" -source "board/inka4x0/Kconfig" source "board/intercontrol/digsy_mtc/Kconfig" source "board/ipek01/Kconfig" source "board/jupiter/Kconfig" diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig deleted file mode 100644 index 94a41f0..0000000 --- a/board/inka4x0/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_INKA4X0 - -config SYS_BOARD - default "inka4x0" - -config SYS_CONFIG_NAME - default "inka4x0" - -endif diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS deleted file mode 100644 index 246b2d4..0000000 --- a/board/inka4x0/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -INKA4X0 BOARD -M: Detlev Zundel dzu@denx.de -S: Maintained -F: board/inka4x0/ -F: include/configs/inka4x0.h -F: configs/inka4x0_defconfig diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile deleted file mode 100644 index c9a3540..0000000 --- a/board/inka4x0/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2009 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := inka4x0.o inkadiag.o diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c deleted file mode 100644 index 0a32f0e..0000000 --- a/board/inka4x0/inka4x0.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Andreas Pfefferle, DENX Software Engineering, ap@denx.de. - * - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> - -#if defined(CONFIG_DDR_MT46V16M16) -#include "mt46v16m16-75.h" -#elif defined(CONFIG_SDR_MT48LC16M16A2) -#include "mt48lc16m16a2-75.h" -#elif defined(CONFIG_DDR_MT46V32M16) -#include "mt46v32m16.h" -#elif defined(CONFIG_DDR_HYB25D512160BF) -#include "hyb25d512160bf.h" -#elif defined(CONFIG_DDR_K4H511638C) -#include "k4h511638c.h" -#else -#error "INKA4x0 SDRAM: invalid chip type specified!" -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit); - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32(&sdram->mode, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32(&sdram->mode, SDRAM_MODE | 0x04000000); -#endif - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* auto refresh */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit); - - /* set mode register */ - out_be32(&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *) MPC5XXX_SDRAM; - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - long test1, test2; - - /* setup SDRAM chip selects */ - out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */ - out_be32(&mm->sdram1, 0x40000000); /* disabled */ - - /* setup config registers */ - out_be32(&sdram->config1, SDRAM_CONFIG1); - out_be32(&sdram->config2, SDRAM_CONFIG2); - -#if SDRAM_DDR - /* set tap delay */ - out_be32(&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32(&mm->sdram0, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32(&mm->sdram0, 0); /* disabled */ - } - - out_be32(&mm->sdram1, dramsize); /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -int checkboard (void) -{ - puts ("Board: INKA 4X0\n"); - return 0; -} - -void flash_preinit(void) -{ - volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT (CS0) cannot be cleared when - * executing in flash. - */ - clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */ -} - -int misc_init_f (void) -{ - volatile struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - volatile struct mpc5xxx_gpt *gpt; - char tmp[10]; - int i, br; - - i = getenv_f("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_SYS_BRIGHTNESS; - if (br > 255) - br = 255; - - /* Initialize GPIO output pins. - */ - /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ - for (i = 0; i <= 5; i++) { - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10)); - out_be32(&gpt->emsr, 0x34); - } - - /* Configure GPT7 as PWM timer, 1kHz, no ints. */ - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10)); - out_be32(&gpt->emsr, 0); /* Disable */ - out_be32(&gpt->cir, 0x020000fe); - out_be32(&gpt->pwmcr, (br << 16)); - out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */ - - /* Configure PSC3_6,7 as GPIO output */ - setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - - /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Set LR mirror bit because it is low-active */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7); - - /* Reset Coral-P graphics controller */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Enable display backlight */ - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8); - - /* - * Configure three wire serial interface to RTC (PSC1_4, - * PSC2_4, PSC3_4, PSC3_5) - */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4); - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5); - clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5); - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c deleted file mode 100644 index 0bd12ec..0000000 --- a/board/inka4x0/inkadiag.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2008, 2009 Andreas Pfefferle, - * DENX Software Engineering, ap@denx.de. - * (C) Copyright 2009 Detlev Zundel, - * DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <common.h> -#include <config.h> -#include <mpc5xxx.h> -#include <pci.h> - -#include <command.h> - -/* This is needed for the includes in ns16550.h */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#include <ns16550.h> - -#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START) - -#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */ -#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */ - -#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */ -#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */ - -#define DIGIO_LED0 0x00000001 /* Output 0 */ -#define DIGIO_LED1 0x00000002 /* Output 1 */ -#define DIGIO_LED2 0x00000004 /* Output 2 */ -#define DIGIO_LED3 0x00000008 /* Output 3 */ -#define DIGIO_LED4 0x00000010 /* Output 4 */ -#define DIGIO_LED5 0x00000020 /* Output 5 */ - -#define DIGIO_DRAWER1 0x00000100 /* Output 8 */ -#define DIGIO_DRAWER2 0x00000200 /* Output 9 */ - -#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START) - -#define PSC_OP1_RTS 0x01 -#define PSC_OP0_RTS 0x01 - -/* - * Table with supported baudrates (defined in inka4x0.h) - */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; -#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) - -static unsigned int inka_digin_get_input(void) -{ - return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 | - in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24; -} - -#define LED_HIGH(NUM) \ - do { \ - setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define LED_LOW(NUM) \ - do { \ - clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define CHECK_LED(NUM) \ - do { \ - if (state & (1 << NUM)) { \ - LED_HIGH(NUM); \ - } else { \ - LED_LOW(NUM); \ - } \ - } while (0) - -static void inka_digio_set_output(unsigned int state, int which) -{ - volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (which == 0) { - /* other */ - CHECK_LED(0); - CHECK_LED(1); - CHECK_LED(2); - CHECK_LED(3); - CHECK_LED(4); - CHECK_LED(5); - } else { - if (which == 1) { - /* drawer1 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x1000); - } else { - setbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x1000); - } - } - if (which == 2) { - /* drawer 2 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x2000); - } else { - setbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x2000); - } - } - } - udelay(1); -} - -static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - unsigned int state, val; - - switch (argc) { - case 3: - /* Write a value */ - val = simple_strtol(argv[2], NULL, 16); - - if (strcmp(argv[1], "drawer1") == 0) { - inka_digio_set_output(val, 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - inka_digio_set_output(val, 2); - } else if (strcmp(argv[1], "other") == 0) - inka_digio_set_output(val, 0); - else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - /* fall through */ - case 2: - /* Read a value */ - state = inka_digin_get_input(); - - if (strcmp(argv[1], "drawer1") == 0) { - val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1); - } else if (strcmp(argv[1], "other") == 0) { - val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1)) - | (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2); - } else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - printf("exit code: 0x%X\n", val); - return 0; - default: - return cmd_usage(cmdtp); - } - - return -1; -} - -DECLARE_GLOBAL_DATA_PTR; - -static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate) -{ - unsigned long baseclk; - int div; - - /* reset PSC */ - out_8(&psc->command, PSC_SEL_MODE_REG_1); - - /* select clock sources */ - - out_be16(&psc->psc_clock_select, 0); - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* switch to UART mode */ - out_be32(&psc->sicr, 0); - - /* configure parity, bit length and so on */ - - out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); - out_8(&psc->mode, PSC_MODE_ONE_STOP); - - /* set up UART divisor */ - div = (baseclk + (baudrate / 2)) / baudrate; - out_8(&psc->ctur, (div >> 8) & 0xff); - out_8(&psc->ctlr, div & 0xff); - - /* disable all interrupts */ - out_be16(&psc->psc_imr, 0); - - /* reset and enable Rx/Tx */ - out_8(&psc->command, PSC_RST_RX); - out_8(&psc->command, PSC_RST_TX); - out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE); - - return 0; -} - -static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c) -{ - /* Wait 1 second for last character to go. */ - int i = 0; - - while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10)) - udelay(10); - psc->psc_buffer_8 = c; - -} - -static int ser_getc(volatile struct mpc5xxx_psc *psc) -{ - /* Wait for a character to arrive. */ - int i = 0; - - while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10)) - udelay(10); - - return in_8(&psc->psc_buffer_8); -} - -static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - volatile struct NS16550 *uart; - volatile struct mpc5xxx_psc *psc; - unsigned int num, mode; - int combrd, baudrate, i, j, len; - int address; - - if (argc < 5) - return cmd_usage(cmdtp); - - argc--; - argv++; - - num = simple_strtol(argv[0], NULL, 0); - if (num < 0 || num > 11) { - printf("invalid argument for num: %d\n", num); - return -1; - } - - mode = simple_strtol(argv[1], NULL, 0); - - combrd = 0; - baudrate = simple_strtoul(argv[2], NULL, 10); - for (i=0; i<N_BAUDRATES; ++i) { - if (baudrate == baudrate_table[i]) - break; - } - if (i == N_BAUDRATES) { - printf("## Baudrate %d bps not supported\n", - baudrate); - return 1; - } - combrd = 115200 / baudrate; - - uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3)); - - printf("Testing uart %d.\n\n", num); - - if ((num >= 0) && (num <= 7)) { - if (mode & 1) { - /* turn on 'loopback' mode */ - out_8(&uart->mcr, UART_MCR_LOOP); - } else { - /* - * establish the UART's operational parameters - * set DLAB=1, so rbr accesses DLL - */ - out_8(&uart->lcr, UART_LCR_DLAB); - /* set baudrate */ - out_8(&uart->rbr, combrd); - /* set data-format: 8-N-1 */ - out_8(&uart->lcr, UART_LCR_WLS_8); - } - - if (mode & 2) { - /* set request to send */ - out_8(&uart->mcr, UART_MCR_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00) - return -1; - } - if (mode & 4) { - /* set data terminal ready */ - out_8(&uart->mcr, UART_MCR_DTR); - udelay(10); - /* check data set ready and carrier detect */ - if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD)) - != (UART_MSR_DSR | UART_MSR_DCD)) - return -1; - } - - /* write each message-character, read it back, and display it */ - for (i = 0, len = strlen(argv[3]); i < len; ++i) { - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - out_8(&uart->rbr, argv[3][i]); - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - printf("%c", in_8(&uart->rbr)); - } - printf("\n\n"); - out_8(&uart->mcr, 0x00); - } else { - address = 0; - - switch (num) { - case 8: - address = MPC5XXX_PSC6; - break; - case 9: - address = MPC5XXX_PSC3; - break; - case 10: - address = MPC5XXX_PSC2; - break; - case 11: - address = MPC5XXX_PSC1; - break; - } - psc = (struct mpc5xxx_psc *)address; - ser_init(psc, simple_strtol(argv[2], NULL, 0)); - if (mode & 2) { - /* set request to send */ - out_8(&psc->op0, PSC_OP0_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0) - return -1; - } - len = strlen(argv[3]); - for (i = 0; i < len; ++i) { - ser_putc(psc, argv[3][i]); - printf("%c", ser_getc(psc)); - } - printf("\n\n"); - } - return 0; -} - -#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */ -static void buzzer_turn_on(unsigned int freq) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - const u32 prescale = gd->arch.ipb_clk / freq / 128; - const u32 count = 128; - const u32 width = 64; - - gpt->cir = (prescale << 16) | count; - gpt->pwmcr = width << 16; - gpt->emsr = 3; /* Timer enabled for PWM */ -} - -static void buzzer_turn_off(void) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - gpt->emsr = 0; -} - -static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - - unsigned int period, freq; - int prev, i; - - if (argc != 3) - return cmd_usage(cmdtp); - - argc--; - argv++; - - period = simple_strtol(argv[0], NULL, 0); - if (!period) - printf("Zero period is senseless\n"); - argc--; - argv++; - - freq = simple_strtol(argv[0], NULL, 0); - /* avoid zero prescale in buzzer_turn_on() */ - if (freq > gd->arch.ipb_clk / 128) { - printf("%dHz exceeds maximum (%ldHz)\n", freq, - gd->arch.ipb_clk / 128); - } else if (!freq) - printf("Zero frequency is senseless\n"); - else - buzzer_turn_on(freq); - - clear_ctrlc(); - prev = disable_ctrlc(0); - - printf("Buzzing for %d ms. Type ^C to abort!\n\n", period); - - i = 0; - while (!ctrlc() && (i++ < CONFIG_SYS_HZ)) - udelay(period); - - clear_ctrlc(); - disable_ctrlc(prev); - - buzzer_turn_off(); - - return 0; -} - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -cmd_tbl_t cmd_inkadiag_sub[] = { - U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input", - "<drawer1|drawer2|other> [value] - get or set specified signal"), - U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port", - "<num> <mode> <baudrate> <msg> - test uart num [0..11] in mode\n" - "and baudrate with msg"), - U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer", - "<period> <freq> - turn buzzer on for period ms with freq hz"), - U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help", - "[command] - get help for command"), -}; - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) { - extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items, - cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]); - /* do_help prints command name - we prepend inkadiag to our subcommands! */ -#ifdef CONFIG_SYS_LONGHELP - puts ("inkadiag "); -#endif - return _do_help(&cmd_inkadiag_sub[0], - ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv); -} - -static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - cmd_tbl_t *c; - - c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub)); - - if (c) { - argc--; - argv++; - return c->cmd(c, flag, argc, argv); - } else { - /* Unrecognized command */ - return cmd_usage(cmdtp); - } -} - -U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag, - "inkadiag - inka diagnosis\n", - "[inkadiag what ...]\n" - " - perform a diagnosis on inka hardware\n" - "'inkadiag' performs hardware tests."); diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h deleted file mode 100644 index 054ddaf..0000000 --- a/board/inka4x0/k4h511638c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz m8@semihalf.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h deleted file mode 100644 index 23fc6f0..0000000 --- a/board/inka4x0/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h deleted file mode 100644 index f16f450..0000000 --- a/board/inka4x0/mt46v32m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz m8@semihalf.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa..0000000 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig deleted file mode 100644 index 4c1016a..0000000 --- a/configs/inka4x0_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_INKA4X0=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h deleted file mode 100644 index c7bf531..0000000 --- a/include/configs/inka4x0.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFE00000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ -#endif -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_IPADDR 192.168.100.2 -#define CONFIG_SERVERIP 192.168.100.1 -#define CONFIG_NETMASK 255.255.255.0 -#define HOSTNAME inka4x0 -#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "enable_disp=mw.l 100000 04000000 1;" \ - "cp.l 100000 f0000b20 1;" \ - "cp.l 100000 f0000b28 1\0" \ - "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ - "ide_boot=ext2load ide 0:1 200000 uImage;" \ - "run ideargs addip addcons enable_disp;bootm\0" \ - "brightness=255\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run ide_boot" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xffe00000 -#define CONFIG_SYS_FLASH_SIZE 0x00200000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* - * SDRAM controller configuration - */ -#undef CONFIG_SDR_MT48LC16M16A2 -#undef CONFIG_DDR_MT46V16M16 -#undef CONFIG_DDR_MT46V32M16 -#undef CONFIG_DDR_HYB25D512160BF -#define CONFIG_DDR_K4H511638C - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM - -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) - -#ifdef CONFIG_POST -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII - -/* - * GPIO configuration - * - * use CS1 as gpio_wkup_6 output - * Bit 0 (mask: 0x80000000): 0 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, I2C1 is used for onboard EEPROM - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard - * EEPROM - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 - * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 - * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 - -/* - * RTC configuration - */ -#define CONFIG_RTC_RTC4543 1 /* use external RTC */ - -/* - * Software (bit-bang) three wire serial configuration - * - * Note that we need the ifdefs because otherwise compilation of - * mkimage.c fails. - */ -#define CONFIG_SOFT_TWS 1 - -#ifdef TWS_IMPLEMENTATION -#include <mpc5xxx.h> -#include <asm/io.h> - -#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */ -#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */ -#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */ -#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */ - -static inline void tws_ce(unsigned bit) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - if (bit) - setbits_8(&wu_gpio->dvo, TWS_CE); - else - clrbits_8(&wu_gpio->dvo, TWS_CE); -} - -static inline void tws_wr(unsigned bit) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - if (bit) - setbits_8(&wu_gpio->dvo, TWS_WR); - else - clrbits_8(&wu_gpio->dvo, TWS_WR); -} - -static inline void tws_clk(unsigned bit) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (bit) - setbits_8(&gpio->sint_dvo, TWS_CLK); - else - clrbits_8(&gpio->sint_dvo, TWS_CLK); -} - -static inline void tws_data(unsigned bit) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (bit) - setbits_8(&gpio->sint_dvo, TWS_DATA); - else - clrbits_8(&gpio->sint_dvo, TWS_DATA); -} - -static inline unsigned tws_data_read(void) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - return !!(in_8(&gpio->sint_ival) & TWS_DATA); -} - -static inline void tws_data_config_output(unsigned output) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (output) - setbits_8(&gpio->sint_ddr, TWS_DATA); - else - clrbits_8(&gpio->sint_ddr, TWS_DATA); -} -#endif /* TWS_IMPLEMENTATION */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 32Mbit SRAM @0x30000000 */ -#define CONFIG_SYS_CS1_START 0x30000000 -#define CONFIG_SYS_CS1_SIZE 0x00400000 -#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ - -/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x0001000 -#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ - -/* GPIO in @0x30400000 */ -#define CONFIG_SYS_CS3_START 0x30400000 -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x00015555 -#define CONFIG_USB_CONFIG 0x00001000 -#define CONFIG_USB_STORAGE - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -#define CONFIG_ATAPI 1 - -#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc5xxx/Kconfig | 4 - board/motionpro/Kconfig | 9 - board/motionpro/MAINTAINERS | 6 - board/motionpro/Makefile | 8 - board/motionpro/motionpro.c | 220 ---------------------- configs/motionpro_defconfig | 7 - include/configs/motionpro.h | 390 --------------------------------------- 7 files changed, 644 deletions(-) delete mode 100644 board/motionpro/Kconfig delete mode 100644 board/motionpro/MAINTAINERS delete mode 100644 board/motionpro/Makefile delete mode 100644 board/motionpro/motionpro.c delete mode 100644 configs/motionpro_defconfig delete mode 100644 include/configs/motionpro.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index c7b6892..70018aa 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -18,9 +18,6 @@ config TARGET_A4M072 config TARGET_CM5200 bool "Support cm5200"

-config TARGET_MOTIONPRO - bool "Support motionpro" - config TARGET_MUNICES bool "Support munices"

@@ -64,7 +61,6 @@ source "board/a4m072/Kconfig" source "board/cm5200/Kconfig" source "board/ifm/o2dnt2/Kconfig" source "board/intercontrol/digsy_mtc/Kconfig" -source "board/motionpro/Kconfig" source "board/munices/Kconfig" source "board/phytec/pcm030/Kconfig" source "board/tqc/tqm5200/Kconfig" diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig deleted file mode 100644 index f624f6c..0000000 --- a/board/motionpro/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MOTIONPRO - -config SYS_BOARD - default "motionpro" - -config SYS_CONFIG_NAME - default "motionpro" - -endif diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS deleted file mode 100644 index 2f8b5cb..0000000 --- a/board/motionpro/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MOTIONPRO BOARD -#M: - -S: Maintained -F: board/motionpro/ -F: include/configs/motionpro.h -F: configs/motionpro_defconfig diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile deleted file mode 100644 index 898a384..0000000 --- a/board/motionpro/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := motionpro.o diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c deleted file mode 100644 index 4d0ebaa..0000000 --- a/board/motionpro/motionpro.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for Promess PRO - by Andy Joseph, andy@promessdev.com - * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com - * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 - * Also changed the refresh for 100MHz operation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <miiphy.h> -#include <libfdt.h> - -#if defined(CONFIG_STATUS_LED) -#include <status_led.h> -#endif /* CONFIG_STATUS_LED */ - -/* Kollmorgen DPR initialization data */ -struct init_elem { - unsigned long addr; - unsigned len; - char *data; - } init_seq[] = { - {0x500003F2, 2, "\x86\x00"}, /* HW parameter */ - {0x500003F0, 2, "\x00\x00"}, - {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */ - }; - -/* - * Initialize Kollmorgen DPR - */ -static void kollmorgen_init(void) -{ - unsigned i, j; - vu_char *p; - - for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) { - p = (vu_char *)init_seq[i].addr; - for (j = 0; j < init_seq[i].len; ++j) - *(p + j) = *(init_seq[i].data + j); - } - - printf("DPR: Kollmorgen DPR initialized\n"); -} - - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); - - /* Initialize Kollmorgen DPR */ - kollmorgen_init(); - - return 0; -} - - -/* - * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(), - * PHY goes into FX mode. To take it out of the FX mode and switch into - * desired TX operation, one needs to clear the FX_SEL bit of Mode Control - * Register. - */ -void reset_phy(void) -{ - unsigned short mode_control; - - miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control); - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15, - mode_control & 0xfffe); - return; -} - -#ifndef CONFIG_SYS_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; -} -#endif /* !CONFIG_SYS_RAMBOOT */ - - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -phys_size_t initdram(int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* According to AN3221 (MPC5200B SDRAM Initialization and - * Configuration), the SDelay register must be written a value of - * 0x00000004 as the first step of the SDRAM contorller configuration. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 and disable it */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; - -#else /* !CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* return total ram size */ - return dramsize; -} - - -int checkboard(void) -{ - uchar rev = *(vu_char *)CPLD_REV_REGISTER; - printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev); - return 0; -} - - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - - -#if defined(CONFIG_STATUS_LED) -void __led_init(led_id_t regaddr, int state) -{ - *((vu_long *) regaddr) |= ENABLE_GPIO_OUT; - - if (state == STATUS_LED_ON) - *((vu_long *) regaddr) |= LED_ON; - else - *((vu_long *) regaddr) &= ~LED_ON; -} - -void __led_set(led_id_t regaddr, int state) -{ - if (state == STATUS_LED_ON) - *((vu_long *) regaddr) |= LED_ON; - else - *((vu_long *) regaddr) &= ~LED_ON; -} - -void __led_toggle(led_id_t regaddr) -{ - *((vu_long *) regaddr) ^= LED_ON; -} -#endif /* CONFIG_STATUS_LED */ diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig deleted file mode 100644 index 4d3f909..0000000 --- a/configs/motionpro_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MOTIONPRO=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press "<Esc><Esc>" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h deleted file mode 100644 index 6dc84eb..0000000 --- a/include/configs/motionpro.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -/* CPU and board */ -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_NETCONSOLE 1 /* network console */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x2 -#define CONFIG_PHY_TYPE 0x79c874 -#define CONFIG_RESET_PHY_R 1 - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#undef CONFIG_BOOTARGS - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=motionpro\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.1.106\0" \ - "serverip=192.168.1.100\0" \ - "gatewayip=192.168.1.100\0" \ - "console=ttyPSC0,115200\0" \ - "u-boot_addr=400000\0" \ - "kernel_addr=400000\0" \ - "fdt_addr=700000\0" \ - "ramdisk_addr=800000\0" \ - "multi_image_addr=800000\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ - "bootfile=/tftpboot/motionpro/uImage\0" \ - "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ - "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ - "multi_image_file=kernel+initrd+dtb.img\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fff00000 +${filesize};" \ - "era fff00000 +${filesize}; " \ - "cp.b ${u-boot_addr} fff00000 ${filesize};" \ - "prot on fff00000 +${filesize}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "fat_args=setenv bootargs root=/dev/sda rw\0" \ - "mtdids=nor0=ff000000.flash\0" \ - "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),128k(user_data)\0" \ - "addcons=setenv bootargs ${bootargs} console=${console}\0" \ - "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1 " \ - "console=${console}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "run nfsargs addip addmtd; " \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_self=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ - "run ramargs addip addcons addmtd; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ - "${multi_image_addr} ${multi_image_file}; " \ - "bootm ${multi_image_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run fat_multi" - -/* - * do board-specific init - */ -#define CONFIG_BOARD_EARLY_INIT_R 1 - -/* - * Low level configuration - */ - -/* - * Clock configuration: SYS_XTALIN = 33MHz - */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -/* - * Set IPB speed to 100MHz - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Memory map - */ -/* - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. - * Setting MBAR to otherwise will cause system hang when using SmartDMA such - * as network commands. - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * If building for running out of SDRAM, then MBAR has been set up beforehand - * (e.g., by the BDI). Otherwise we must specify the default boot-up value of - * MBAR, as given in the doccumentation. - */ -#if CONFIG_SYS_TEXT_BASE == 0x00100000 -#define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 -#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */ -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_LOWBOOT 1 -#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */ - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00045D00 - -/* Flash memory addressing */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG - -/* Dual Port SRAM -- Kollmorgen Drive memory addressing */ -#define CONFIG_SYS_CS1_START 0x50000000 -#define CONFIG_SYS_CS1_SIZE 0x10000 -#define CONFIG_SYS_CS1_CFG 0x05055800 - -/* Local register access */ -#define CONFIG_SYS_CS2_START 0x50010000 -#define CONFIG_SYS_CS2_SIZE 0x10000 -#define CONFIG_SYS_CS2_CFG 0x05055800 - -/* Anybus CompactCom Module memory addressing */ -#define CONFIG_SYS_CS3_START 0x50020000 -#define CONFIG_SYS_CS3_SIZE 0x10000 -#define CONFIG_SYS_CS3_CFG 0x05055800 - -/* No burst and dead cycle = 2 for all CSs */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x22222222 - -/* - * SDRAM configuration - */ -/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ -#define SDRAM_CONFIG1 0x62322900 -#define SDRAM_CONFIG2 0x88c70000 -#define SDRAM_CONTROL 0x504f0000 -#define SDRAM_MODE 0x00cd0000 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ - -/* - * MTD configuration - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=motionpro-0" -#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ - "13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),-(user_data)" - -/* - * IDE/ATA configuration - */ -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 -#define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET -#define CONFIG_SYS_ATA_STRIDE 4 -#define CONFIG_DOS_PARTITION - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ - -/* - * RTC configuration - */ -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Status LED configuration - */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED - -#define ENABLE_GPIO_OUT 0x00000024 -#define LED_ON 0x00000010 - -#ifndef __ASSEMBLY__ -/* - * In case of Motion-PRO, a LED is identified by its corresponding - * GPT Enable and Mode Select Register. - */ -typedef volatile unsigned long * led_id_t; - -extern void __led_init(led_id_t id, int state); -extern void __led_toggle(led_id_t id); -extern void __led_set(led_id_t id, int state); -#endif /* __ASSEMBLY__ */ - -/* - * Temperature sensor - */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS { 0x49 } - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Configuration of redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Pin multiplexing configuration - */ - -/* PSC1: UART1 - * PSC2: GPIO (default) - * PSC3: GPIO (default) - * USB: 2xUART4/5 - * Ethernet: Ethernet 100Mbit with MD - * Timer: CAN2/GPIO - * PSC6/IRDA: GPIO (default) - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 - -/* - * Motion-PRO's CPLD revision control register - */ -#define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ - -/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc5xxx/Kconfig | 4 - board/phytec/pcm030/Kconfig | 12 - board/phytec/pcm030/MAINTAINERS | 7 - board/phytec/pcm030/Makefile | 8 - board/phytec/pcm030/README | 42 ---- board/phytec/pcm030/mt46v32m16-75.h | 21 -- board/phytec/pcm030/pcm030.c | 205 ----------------- configs/pcm030_LOWBOOT_defconfig | 5 - configs/pcm030_defconfig | 4 - include/configs/pcm030.h | 430 ------------------------------------ 10 files changed, 738 deletions(-) delete mode 100644 board/phytec/pcm030/Kconfig delete mode 100644 board/phytec/pcm030/MAINTAINERS delete mode 100644 board/phytec/pcm030/Makefile delete mode 100644 board/phytec/pcm030/README delete mode 100644 board/phytec/pcm030/mt46v32m16-75.h delete mode 100644 board/phytec/pcm030/pcm030.c delete mode 100644 configs/pcm030_LOWBOOT_defconfig delete mode 100644 configs/pcm030_defconfig delete mode 100644 include/configs/pcm030.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index b1d7ae8..dc86ac3 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -42,9 +42,6 @@ config TARGET_O3DNT config TARGET_DIGSY_MTC bool "Support digsy_mtc"

-config TARGET_PCM030 - bool "Support pcm030" - config TARGET_CHARON bool "Support charon"

@@ -58,7 +55,6 @@ source "board/a4m072/Kconfig" source "board/cm5200/Kconfig" source "board/ifm/o2dnt2/Kconfig" source "board/intercontrol/digsy_mtc/Kconfig" -source "board/phytec/pcm030/Kconfig" source "board/tqc/tqm5200/Kconfig" source "board/v38b/Kconfig"

diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig deleted file mode 100644 index 3a3eab8..0000000 --- a/board/phytec/pcm030/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PCM030 - -config SYS_BOARD - default "pcm030" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "pcm030" - -endif diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS deleted file mode 100644 index 4e2ab0d..0000000 --- a/board/phytec/pcm030/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PCM030 BOARD -M: Jon Smirl jonsmirl@gmail.com -S: Maintained -F: board/phytec/pcm030/ -F: include/configs/pcm030.h -F: configs/pcm030_defconfig -F: configs/pcm030_LOWBOOT_defconfig diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile deleted file mode 100644 index 2bb49dc..0000000 --- a/board/phytec/pcm030/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pcm030.o diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README deleted file mode 100644 index 05faab6..0000000 --- a/board/phytec/pcm030/README +++ /dev/null @@ -1,42 +0,0 @@ -To build RAMBOOT, replace this section the main Makefile - -pcm030_config \ -pcm030_RAMBOOT_config \ -pcm030_LOWBOOT_config: unconfig - @ >include/config.h - @[ -z "$(findstring LOWBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ - echo "... with LOWBOOT configuration" ; \ - } - @[ -z "$(findstring RAMBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ - config.tmp ; \ - echo "... with RAMBOOT configuration" ; \ - echo "... remember to make sure that MBAR is already \ - switched to 0xF0000000 !!!" ; \ - } - @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec - @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" - -Alternative SDRAM settings: - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 - -/* Settings for XLB = 99 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714b0f00 -#define SDRAM_CONFIG1 0x63611730 -#define SDRAM_CONFIG2 0x47670000 - -The board ships default with the environment in EEPROM -Moving the environment to flash can be more reliable - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h deleted file mode 100644 index 47fc7c0..0000000 --- a/board/phytec/pcm030/mt46v32m16-75.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * Eric Schumann, Phytec Messtechnik - * adapted for mt46v32m16-75 DDR-RAM - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x71500F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x47770000 - -#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c deleted file mode 100644 index ed41de1..0000000 --- a/board/phytec/pcm030/pcm030.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messtechnik GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/io.h> - -#include "mt46v32m16-75.h" - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32 (&sdram->mode, (SDRAM_EMODE)); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, - (SDRAM_MODE | 0x04000000)); -#endif - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - - /* auto refresh */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); - - /* set mode register */ - out_be32 (&sdram->mode, (SDRAM_MODE)); - - /* normal operation */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | hi_addr_bit)); - - /* set CDM clock enable register, set MPC5200B SDRAM bus */ - /* to reduced driver strength */ - out_be32 (&cdm->clock_enable, (0x00CFFFFF)); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make - * real use of CONFIG_SYS_SDRAM_BASE. The code does not - * work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram(int board_type) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - /* 256MB at 0x0 */ - out_be32 (&mm->sdram0, 0x0000001b); - /* disabled */ - out_be32 (&mm->sdram1, 0x10000000); - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - -#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) - /* set tap delay */ - out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32 (&mm->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - /* disabled */ - out_be32 (&mm->sdram0, 0); - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mm->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize + dramsize2; -} - -int checkboard(void) -{ - puts("Board: phyCORE-MPC5200B-tiny\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -#define GPIO_PSC2_4 0x02000000UL - -void init_ide_reset(void) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("init_ide_reset\n"); - - /* Configure PSC2_4 as GPIO output for ATA reset */ - setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); - setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); - /* Deassert reset */ - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} - -void ide_set_reset(int idereset) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} -#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig deleted file mode 100644 index 42389bb..0000000 --- a/configs/pcm030_LOWBOOT_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_PCM030=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig deleted file mode 100644 index df9309e..0000000 --- a/configs/pcm030_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_PCM030=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h deleted file mode 100644 index 83c96a8..0000000 --- a/include/configs/pcm030.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messatechnik GmbH - * - * (C) Copyright 2009 - * Jon Smirl jonsmirl@gmail.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" - -/*----------------------------------------------------------------------------- -High Level Configuration Options -(easy to change) ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ -#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ - /* FEC configuration and IDE */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFF000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ - -/*----------------------------------------------------------------------------- -Serial console configuration ------------------------------------------------------------------------------*/ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ - /*define gps port conf. */ - /* register later on to */ - /*enable UART function! */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */ -#define CONFIG_SYS_LOWBOOT 1 -#endif -/* RAMBOOT will be defined automatically in memory section */ - -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ - "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" - -/*----------------------------------------------------------------------------- -Autobooting ------------------------------------------------------------------------------*/ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ - /* even with bootdelay=0 */ -#undef CONFIG_BOOTARGS - - -#define CONFIG_PREBOOT "echo;" \ - "echo Type "run bootcmd_net" to load Kernel over TFTP and to "\ - "mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uimage=uImage-pcm030\0" \ - "oftree=oftree-pcm030.dtb\0" \ - "jffs2=root-pcm030.jffs2\0" \ - "uboot=u-boot-pcm030.bin\0" \ - "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ - " $(mtdparts) rw\0" \ - "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ - " rootfstype=jffs2\0" \ - "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ - " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ - "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ - " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ - "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ - "0xfff40000\0" \ - " cp.b 0x400000 0xff040000 $(filesize)\0" \ - "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ - "cp.b 0x400000 0xff200000 $(filesize)\0" \ - "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ - " cp.b 0x400000 0xfff40000 $(filesize)\0" \ - "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ - " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run bcmd_flash" - -/*-------------------------------------------------------------------------- -IPB Bus clocking configuration. - ---------------------------------------------------------------------------*/ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/*------------------------------------------------------------------------- - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - * -----------------------------------------------------------------------*/ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#define CONFIG_SYS_XLB_PIPELINING 1 - -/*--------------------------------------------------------------------------- - I2C configuration ----------------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*--------------------------------------------------------------------------- - EEPROM CAT24WC32 configuration ----------------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ -#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_SIZE 2048 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 - -/*--------------------------------------------------------------------------- -RTC configuration ----------------------------------------------------------------------------*/ -#define RTC -#define CONFIG_RTC_PCF8563 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/*--------------------------------------------------------------------------- - Flash configuration ----------------------------------------------------------------------------*/ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - /* (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Use also hardware protection. This seems required, as the BDI uses - * hardware protection. Without this, U-Boot can't work with this sectors, - * as its protection is software only by default - */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/*--------------------------------------------------------------------------- - Environment settings ----------------------------------------------------------------------------*/ - -/* pcm030 ships with environment is EEPROM by default */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ - /*beginning of the EEPROM */ -#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------------- - Memory map ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ - /* bootloader or debugger config */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */ - /* area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------------- - Ethernet configuration ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 - -/*--------------------------------------------------------------------------- - GPIO configuration - ---------------------------------------------------------------------------*/ - -/* GPIO port configuration - * - * Pin mapping: - * - * [29:31] = 01x - * PSC1_0 -> AC97 SDATA out - * PSC1_1 -> AC97 SDTA in - * PSC1_2 -> AC97 SYNC out - * PSC1_3 -> AC97 bitclock out - * PSC1_4 -> AC97 reset out - * - * [25:27] = 001 - * PSC2_0 -> CAN 1 Tx out - * PSC2_1 -> CAN 1 Rx in - * PSC2_2 -> CAN 2 Tx out - * PSC2_3 -> CAN 2 Rx in - * PSC2_4 -> GPIO (claimed for ATA reset, active low) - * - * - * [20:23] = 1100 - * PSC3_0 -> UART Tx out - * PSC3_1 -> UART Rx in - * PSC3_2 -> UART RTS (in/out FIXME) - * PSC3_3 -> UART CTS (in/out FIXME) - * PSC3_4 -> LocalPlus Bus CS6 \ - * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] - * PSC3_6 -> dedicated SPI MOSI out (master case) - * PSC3_7 -> dedicated SPI MISO in (master case) - * PSC3_8 -> dedicated SPI SS out (master case) - * PSC3_9 -> dedicated SPI CLK out (master case) - * - * [18:19] = 01 - * USB_0 -> USB OE out - * USB_1 -> USB Tx- out - * USB_2 -> USB Tx+ out - * USB_3 -> USB RxD (in/out FIXME) - * USB_4 -> USB Rx+ in - * USB_5 -> USB Rx- in - * USB_6 -> USB PortPower out - * USB_7 -> USB speed out - * USB_8 -> USB suspend (in/out FIXME) - * USB_9 -> USB overcurrent in - * - * [17] = 0 - * USB differential mode - * - * [16] = 0 - * PCI enabled - * - * [12:15] = 0101 - * ETH_0 -> ETH Txen - * ETH_1 -> ETH TxD0 - * ETH_2 -> ETH TxD1 - * ETH_3 -> ETH TxD2 - * ETH_4 -> ETH TxD3 - * ETH_5 -> ETH Txerr - * ETH_6 -> ETH MDC - * ETH_7 -> ETH MDIO - * ETH_8 -> ETH RxDv - * ETH_9 -> ETH RxCLK - * ETH_10 -> ETH Collision - * ETH_11 -> ETH TxD - * ETH_12 -> ETH RxD0 - * ETH_13 -> ETH RxD1 - * ETH_14 -> ETH RxD2 - * ETH_15 -> ETH RxD3 - * ETH_16 -> ETH Rxerr - * ETH_17 -> ETH CRS - * - * [9:11] = 101 - * PSC6_0 -> UART RxD in - * PSC6_1 -> UART CTS (in/out FIXME) - * PSC6_2 -> UART TxD out - * PSC6_3 -> UART RTS (in/out FIXME) - * - * [2:3/6:7] = 00/11 - * TMR_0 -> ATA_CS0 out - * TMR_1 -> ATA_CS1 out - * TMR_2 -> GPIO - * TMR_3 -> GPIO - * TMR_4 -> GPIO - * TMR_5 -> GPIO - * TMR_6 -> GPIO - * TMR_7 -> GPIO - * I2C_0 -> I2C 1 Clock out - * I2C_1 -> I2C 1 IO in/out - * I2C_2 -> I2C 2 Clock out - * I2C_3 -> I2C 2 IO in/out - * - * [4] = 1 - * PSC3_5 is used as CS7 - * - * [5] = 1 - * PSC3_4 is used as CS6 - * - * [1] = 0 - * gpio_wkup_7 is GPIO - * - * [0] = 0 - * gpio_wkup_6 is GPIO - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 - -/*----------------------------------------------------------------------------- - Miscellaneous configurable options --------------------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_DISPLAY_BOARDINFO 1 - -/*----------------------------------------------------------------------------- - Various low-level settings ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -/* no burst access on the LPB */ -#define CONFIG_SYS_CS_BURST 0x00000000 -/* one deadcycle for the 33MHz statemachine */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 -/* one additional waitstate for the 33MHz statemachine */ -#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*--------------------------------------------------------------------------- - IDE/ATA stuff Supports IDE harddisk -----------------------------------------------------------------------------*/ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_SYS_ATA_CS_ON_TIMER01 -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CONFIG_IDE_PREINIT -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 -#define CONFIG_ATAPI 1 - -/* we enable IDE and FAT support, so we also need partition support */ -#define CONFIG_DOS_PARTITION 1 - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/socrates/Kconfig | 9 - board/socrates/MAINTAINERS | 6 - board/socrates/Makefile | 15 -- board/socrates/ddr.c | 56 ----- board/socrates/law.c | 44 ---- board/socrates/nand.c | 163 -------------- board/socrates/sdram.c | 96 --------- board/socrates/socrates.c | 434 ------------------------------------- board/socrates/tlb.c | 105 --------- board/socrates/upm_table.h | 59 ------ configs/socrates_defconfig | 5 - include/configs/socrates.h | 446 --------------------------------------- 13 files changed, 1442 deletions(-) delete mode 100644 board/socrates/Kconfig delete mode 100644 board/socrates/MAINTAINERS delete mode 100644 board/socrates/Makefile delete mode 100644 board/socrates/ddr.c delete mode 100644 board/socrates/law.c delete mode 100644 board/socrates/nand.c delete mode 100644 board/socrates/sdram.c delete mode 100644 board/socrates/socrates.c delete mode 100644 board/socrates/tlb.c delete mode 100644 board/socrates/upm_table.h delete mode 100644 configs/socrates_defconfig delete mode 100644 include/configs/socrates.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3e8d0b1..127bd6f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -11,9 +11,6 @@ choice config TARGET_SBC8548 bool "Support sbc8548"

-config TARGET_SOCRATES - bool "Support socrates" - config TARGET_B4860QDS bool "Support B4860QDS" select SUPPORT_SPL @@ -190,7 +187,6 @@ source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" -source "board/socrates/Kconfig" source "board/stx/stxgp3/Kconfig" source "board/stx/stxssa/Kconfig" source "board/xes/xpedite520x/Kconfig" diff --git a/board/socrates/Kconfig b/board/socrates/Kconfig deleted file mode 100644 index ca945c2..0000000 --- a/board/socrates/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SOCRATES - -config SYS_BOARD - default "socrates" - -config SYS_CONFIG_NAME - default "socrates" - -endif diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS deleted file mode 100644 index 293b8e6..0000000 --- a/board/socrates/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SOCRATES BOARD -#M: - -S: Maintained -F: board/socrates/ -F: include/configs/socrates.h -F: configs/socrates_defconfig diff --git a/board/socrates/Makefile b/board/socrates/Makefile deleted file mode 100644 index 79bda71..0000000 --- a/board/socrates/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2008 -# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += socrates.o -obj-y += law.o -obj-y += tlb.o -obj-y += nand.o -obj-y += sdram.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c deleted file mode 100644 index 6bad4da..0000000 --- a/board/socrates/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/socrates/law.c b/board/socrates/law.c deleted file mode 100644 index 449a030..0000000 --- a/board/socrates/law.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x2fff_ffff DDR 512M - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xc00f_ffff FPGA 1M - * 0xc800_0000 0xcbff_ffff LIME 64M - * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xfc00_0000 0xffff_ffff FLASH 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), -#if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c deleted file mode 100644 index 15e6ea6..0000000 --- a/board/socrates/nand.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_SYS_NAND_BASE) -#include <nand.h> -#include <asm/errno.h> -#include <asm/io.h> - -static int state; -static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte); -static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); -static u_char sc_nand_read_byte(struct mtd_info *mtd); -static u16 sc_nand_read_word(struct mtd_info *mtd); -static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); -static int sc_nand_device_ready(struct mtd_info *mtdinfo); - -#define FPGA_NAND_CMD_MASK (0x7 << 28) -#define FPGA_NAND_CMD_COMMAND (0x0 << 28) -#define FPGA_NAND_CMD_ADDR (0x1 << 28) -#define FPGA_NAND_CMD_READ (0x2 << 28) -#define FPGA_NAND_CMD_WRITE (0x3 << 28) -#define FPGA_NAND_BUSY (0x1 << 15) -#define FPGA_NAND_ENABLE (0x1 << 31) -#define FPGA_NAND_DATA_SHIFT 16 - -/** - * sc_nand_write_byte - write one byte to the chip - * @mtd: MTD device structure - * @byte: pointer to data byte to write - */ -static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); -} - -/** - * sc_nand_write_buf - write buffer to chip - * @mtd: MTD device structure - * @buf: data buffer - * @len: number of bytes to write - */ -static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) { - out_be32(this->IO_ADDR_W, - state | (buf[i] << FPGA_NAND_DATA_SHIFT)); - } -} - - -/** - * sc_nand_read_byte - read one byte from the chip - * @mtd: MTD device structure - */ -static u_char sc_nand_read_byte(struct mtd_info *mtd) -{ - u8 byte; - sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); - return byte; -} - -/** - * sc_nand_read_word - read one word from the chip - * @mtd: MTD device structure - */ -static u16 sc_nand_read_word(struct mtd_info *mtd) -{ - u16 word; - sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); - return word; -} - -/** - * sc_nand_read_buf - read chip data into buffer - * @mtd: MTD device structure - * @buf: buffer to store date - * @len: number of bytes to read - */ -static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - int val; - - val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; - - out_be32(this->IO_ADDR_W, val); - for (i = 0; i < len; i++) { - buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; - } -} - -/** - * sc_nand_device_ready - Check the NAND device is ready for next command. - * @mtd: MTD device structure - */ -static int sc_nand_device_ready(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - - if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) - return 0; /* busy */ - return 1; -} - -/** - * sc_nand_hwcontrol - NAND control functions wrapper. - * @mtd: MTD device structure - * @cmd: Command - */ -static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE); - - switch (ctrl & (NAND_ALE | NAND_CLE)) { - case 0: - state |= FPGA_NAND_CMD_WRITE; - break; - - case NAND_ALE: - state |= FPGA_NAND_CMD_ADDR; - break; - - case NAND_CLE: - state |= FPGA_NAND_CMD_COMMAND; - break; - - default: - printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); - } - - if (ctrl & NAND_NCE) - state |= FPGA_NAND_ENABLE; - } - - if (cmd != NAND_CMD_NONE) - sc_nand_write_byte(mtdinfo, cmd); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->cmd_ctrl = sc_nand_hwcontrol; - nand->ecc.mode = NAND_ECC_SOFT; - nand->dev_ready = sc_nand_device_ready; - nand->read_byte = sc_nand_read_byte; - nand->read_word = sc_nand_read_word; - nand->write_buf = sc_nand_write_buf; - nand->read_buf = sc_nand_read_buf; - - return 0; -} - -#endif diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c deleted file mode 100644 index aebd02f..0000000 --- a/board/socrates/sdram.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <spd_sdram.h> - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -phys_size_t fixed_sdram(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; - - asm ("sync;isync;msync"); - udelay(1000); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; - asm ("sync; isync; msync"); - udelay(1000); - - if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { - /* - * OK, size detected -> all done - */ - return CONFIG_SYS_SDRAM_SIZE<<20; - } - - return 0; /* nothing found ! */ -} -#endif - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c deleted file mode 100644 index 953a43f..0000000 --- a/board/socrates/socrates.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <ioports.h> -#include <flash.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/io.h> -#include <i2c.h> -#include <mb862xx.h> -#include <video_fb.h> -#include "upm_table.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ -extern GraphicDevice mb862xx; - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - char buf[64]; - int f; - int i = getenv_f("serial#", buf, sizeof(buf)); -#ifdef CONFIG_PCI - char *src; -#endif - - puts("Board: Socrates"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - -#ifdef CONFIG_PCI - /* Check the PCI_clk sel bit */ - if (in_be32(&gur->porpllsr) & (1<<15)) { - src = "SYSCLK"; - f = CONFIG_SYS_CLK_FREQ; - } else { - src = "PCI_CLK"; - f = CONFIG_PCI_CLK_FREQ; - } - printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); -#else - printf ("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init (); - return 0; -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { - set_lbc_or(0, gd->bd->bi_flashstart | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); - set_lbc_br(0, gd->bd->bi_flashstart | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - } - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - set_lbc_or(1, 0); - set_lbc_br(1, 0); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - sys_info_t sysinfo; - uint clkdiv; - uint lbc_mhz; - uint lcrr = CONFIG_SYS_LBC_LCRR; - - get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; - - /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ - if (lbc_mhz >= 66) - lcrr &= ~LCRR_DBYP; /* DLL Enabled */ - else - lcrr |= LCRR_DBYP; /* DLL Bypass */ - - out_be32 (&lbc->lcrr, lcrr); - asm ("sync;isync;msync"); - - out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ - out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ - out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ - out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ - - /* Init UPMA for FPGA access */ - out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ - upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); - - /* Init UPMB for Lime controller access */ - out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ - upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ -} - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* set and reset the GPIO pin 2 which will reset the W83782G chip */ - out_8((unsigned char*)&gur->gpoutdr, 0x3F ); - out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ - udelay(200); - out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); - - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[12]; - int rc, i = 0; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR FLASH mapping */ - val[i++] = 0; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = gd->bd->bi_flashstart; - val[i++] = gd->bd->bi_flashsize; - - if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { - /* Fixup LIME mapping */ - val[i++] = 2; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_LIME_BASE; - val[i++] = CONFIG_SYS_LIME_SIZE; - } - - /* Fixup FPGA mapping */ - val[i++] = 3; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_FPGA_BASE; - val[i++] = CONFIG_SYS_FPGA_SIZE; - - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update localbus ranges, err=%s\n", - fdt_strerror(rc)); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#define DEFAULT_BRIGHTNESS 25 -#define BACKLIGHT_ENABLE (1 << 31) - -static const gdc_regs init_regs [] = -{ - {0x0100, 0x00010f00}, - {0x0020, 0x801901df}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x01df0320}, - {0x0004, 0x041f0000}, - {0x0008, 0x031f031f}, - {0x000c, 0x017f0349}, - {0x0010, 0x020c0000}, - {0x0014, 0x01df01e9}, - {0x0018, 0x00000000}, - {0x001c, 0x01e00320}, - {0x0100, 0x80010f00}, - {0x0, 0x0} -}; - -const gdc_regs *board_get_regs (void) -{ - return init_regs; -} - -int lime_probe(void) -{ - uint cfg_br2; - uint cfg_or2; - int type; - - cfg_br2 = get_lbc_br(2); - cfg_or2 = get_lbc_or(2); - - /* Configure GPCM for CS2 */ - set_lbc_br(2, 0); - set_lbc_or(2, 0xfc000410); - set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); - - /* Get controller type */ - type = mb862xx_probe(CONFIG_SYS_LIME_BASE); - - /* Restore previous CS2 configuration */ - set_lbc_br(2, 0); - set_lbc_or(2, cfg_or2); - set_lbc_br(2, cfg_br2); - - return (type == MB862XX_TYPE_LIME) ? 1 : 0; -} - -/* Returns Lime base address */ -unsigned int board_video_init (void) -{ - if (!lime_probe()) - return 0; - - mb862xx.winSizeX = 800; - mb862xx.winSizeY = 480; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - mb862xx.gdfBytesPP = 2; - - return CONFIG_SYS_LIME_BASE; -} - -#define W83782D_REG_CFG 0x40 -#define W83782D_REG_BANK_SEL 0x4e -#define W83782D_REG_ADCCLK 0x4b -#define W83782D_REG_BEEP_CTRL 0x4d -#define W83782D_REG_BEEP_CTRL2 0x57 -#define W83782D_REG_PWMOUT1 0x5b -#define W83782D_REG_VBAT 0x5d - -static int w83782d_hwmon_init(void) -{ - u8 buf; - - if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) - return -1; - - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); - - buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, - buf | 0x80); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); - - buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, - (buf & 0xf4) | 0x01); - return 0; -} - -static void board_backlight_brightness(int br) -{ - u32 reg; - u8 buf; - u8 old_buf; - - /* Select bank 0 */ - if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) - goto err; - else - buf = old_buf & 0xf8; - - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) - goto err; - - if (br > 0) { - /* PWMOUT1 duty cycle ctrl */ - buf = 255 / (100 / br); - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) - goto err; - - /* LEDs on */ - reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); - if (!(reg & BACKLIGHT_ENABLE)); - out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), - reg | BACKLIGHT_ENABLE); - } else { - buf = 0; - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) - goto err; - - /* LEDs off */ - reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); - reg &= ~BACKLIGHT_ENABLE; - out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); - } - /* Restore previous bank setting */ - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) - goto err; - - return; -err: - printf("W83782G I2C access failed\n"); -} - -void board_backlight_switch (int flag) -{ - char * param; - int rc; - - if (w83782d_hwmon_init()) - printf ("hwmon IC init failed\n"); - - if (flag) { - param = getenv("brightness"); - rc = param ? simple_strtol(param, NULL, 10) : -1; - if (rc < 0) - rc = DEFAULT_BRIGHTNESS; - } else { - rc = 0; - } - board_backlight_brightness(rc); -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " Board: Socrates"); - } else { - info [0] = '\0'; - } -} -#endif diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c deleted file mode 100644 index f3b093a..0000000 --- a/board/socrates/tlb.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - - /* - * TLB 1: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#if defined(CONFIG_SYS_FPGA_BASE) - /* - * TLB 4: 1M Non-cacheable, guarded - * 0xc0000000 1M FPGA and NAND - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1M, 1), -#endif - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xc8000000 16M LIME GDC framebuffer - * 0xc9fc0000 256K LIME GDC MMIO - * (0xcbfc0000 256K LIME GDC MMIO) - * MMIO is relocatable and could be at 0xcbfc0000 - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h deleted file mode 100644 index 600d5f0..0000000 --- a/board/socrates/upm_table.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __UPM_TABLE_H -#define __UPM_TABLE_H - -/* UPM Table Configuration Code for FPGA access */ -static const unsigned int UPMTableA[] = -{ - 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ - 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ - 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ - 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ - 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ - 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ - 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ - 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ - 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ - 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ -}; - -/* LIME UPM B Table Configuration Code */ -static unsigned int UPMTableB[] = -{ - 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ - 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ - 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ - 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ - 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ - 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ - 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ - 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ - 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ - 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ - 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ -}; -#endif diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig deleted file mode 100644 index 37af82e..0000000 --- a/configs/socrates_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_SOCRATES=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/socrates.h b/include/configs/socrates.h deleted file mode 100644 index 292b514..0000000 --- a/include/configs/socrates.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Wolfgang Denk wd@denx.de - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Socrates - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 -#define CONFIG_SOCRATES 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66666666 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ - -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ - -/* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ - -/* - * Flash on the LocalBus - */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ - -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ - -/* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_HMI_BASE 0xc0010000 -#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND - -/* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ - -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define VIDEO_FB_16BPP_PIXEL_SWAP -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ - -/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ -#define CONFIG_SYS_MB862xx_CCF 0x10000 -/* SDRAM parameter */ -#define CONFIG_SYS_MB862xx_MMR 0x4157BA63 - -/* Serial Port */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 102124 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 102124 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C RTC */ -#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ - -/* I2C W83782G HW-Monitoring IC */ -#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ - -/* I2C temp sensor */ -/* Socrates uses Maxim's DS75, which is compatible with LM75 */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 125 -#define CONFIG_SYS_DTT_LOW_TEMP -55 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - -/* - * General PCI - * Memory space is mapped 1-1. - */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0,1] */ -#define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#endif - - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome on the ABB Socrates Board;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ - "bootfile=/home/tftp/syscon3/uImage\0" \ - "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ - "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ - "uboot_addr=FFFA0000\0" \ - "kernel_addr=FE000000\0" \ - "fdt_addr=FE1E0000\0" \ - "ramdisk_addr=FE200000\0" \ - "fdt_addr_r=B00000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr_r=400000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "boot_nor=run ramargs addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "update_uboot=tftp 100000 ${uboot_file};" \ - "protect off fffa0000 ffffffff;" \ - "era fffa0000 ffffffff;" \ - "cp.b 100000 fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_kernel=tftp 100000 ${bootfile};" \ - "era fe000000 fe1dffff;" \ - "cp.b 100000 fe000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_fdt=tftp 100000 ${fdt_file};" \ - "era fe1e0000 fe1fffff;" \ - "cp.b 100000 fe1e0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_initrd=tftp 100000 ${initrd_file};" \ - "era fe200000 fe9fffff;" \ - "cp.b 100000 fe200000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "clean_data=era fea00000 fff5ffff\0" \ - "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ - "load_usb=usb start;" \ - "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ - "boot_usb=run load_usb usbargs addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr};" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run boot_nor" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ -#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_USB_STORAGE 1 - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 8 - board/stx/stxgp3/Kconfig | 12 - board/stx/stxgp3/MAINTAINERS | 6 - board/stx/stxgp3/Makefile | 12 - board/stx/stxgp3/ddr.c | 46 ---- board/stx/stxgp3/flash.c | 499 --------------------------------------- board/stx/stxgp3/law.c | 42 ---- board/stx/stxgp3/stxgp3.c | 331 -------------------------- board/stx/stxgp3/tlb.c | 114 --------- board/stx/stxssa/Kconfig | 12 - board/stx/stxssa/MAINTAINERS | 7 - board/stx/stxssa/Makefile | 11 - board/stx/stxssa/ddr.c | 47 ---- board/stx/stxssa/law.c | 44 ---- board/stx/stxssa/stxssa.c | 370 ----------------------------- board/stx/stxssa/tlb.c | 90 ------- configs/stxgp3_defconfig | 4 - configs/stxssa_4M_defconfig | 5 - configs/stxssa_defconfig | 4 - include/configs/stxgp3.h | 355 ---------------------------- include/configs/stxssa.h | 441 ---------------------------------- 21 files changed, 2460 deletions(-) delete mode 100644 board/stx/stxgp3/Kconfig delete mode 100644 board/stx/stxgp3/MAINTAINERS delete mode 100644 board/stx/stxgp3/Makefile delete mode 100644 board/stx/stxgp3/ddr.c delete mode 100644 board/stx/stxgp3/flash.c delete mode 100644 board/stx/stxgp3/law.c delete mode 100644 board/stx/stxgp3/stxgp3.c delete mode 100644 board/stx/stxgp3/tlb.c delete mode 100644 board/stx/stxssa/Kconfig delete mode 100644 board/stx/stxssa/MAINTAINERS delete mode 100644 board/stx/stxssa/Makefile delete mode 100644 board/stx/stxssa/ddr.c delete mode 100644 board/stx/stxssa/law.c delete mode 100644 board/stx/stxssa/stxssa.c delete mode 100644 board/stx/stxssa/tlb.c delete mode 100644 configs/stxgp3_defconfig delete mode 100644 configs/stxssa_4M_defconfig delete mode 100644 configs/stxssa_defconfig delete mode 100644 include/configs/stxgp3.h delete mode 100644 include/configs/stxssa.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 127bd6f..8907b03 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -134,12 +134,6 @@ config TARGET_CONTROLCENTERD config TARGET_KMP204X bool "Support kmp204x"

-config TARGET_STXGP3 - bool "Support stxgp3" - -config TARGET_STXSSA - bool "Support stxssa" - config TARGET_XPEDITE520X bool "Support xpedite520x"

@@ -187,8 +181,6 @@ source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" -source "board/stx/stxgp3/Kconfig" -source "board/stx/stxssa/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/board/stx/stxgp3/Kconfig b/board/stx/stxgp3/Kconfig deleted file mode 100644 index 910b31b..0000000 --- a/board/stx/stxgp3/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_STXGP3 - -config SYS_BOARD - default "stxgp3" - -config SYS_VENDOR - default "stx" - -config SYS_CONFIG_NAME - default "stxgp3" - -endif diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS deleted file mode 100644 index bd5743c..0000000 --- a/board/stx/stxgp3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -STXGP3 BOARD -#M: Dan Malek dan@embeddedalley.com -S: Orphan (since 2014-06) -F: board/stx/stxgp3/ -F: include/configs/stxgp3.h -F: configs/stxgp3_defconfig diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile deleted file mode 100644 index 78e2d6c..0000000 --- a/board/stx/stxgp3/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += stxgp3.o -obj-y += law.o -obj-y += tlb.o -obj-y += flash.o -obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c deleted file mode 100644 index 41d4cfe..0000000 --- a/board/stx/stxgp3/ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stx/stxgp3/flash.c b/board/stx/stxgp3/flash.c deleted file mode 100644 index 61066a4..0000000 --- a/board/stx/stxgp3/flash.c +++ /dev/null @@ -1,499 +0,0 @@ -/* - * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. dan@embeddededge.com - * Copied from ADS85xx. - * Updated to support the Silicon Tx GP3 8560. We should only find - * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash), - * but I left other code here in case people order custom boards. - * - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if !defined(CONFIG_SYS_NO_FLASH) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - - case (INTEL_ID_28F640C3T): - info->flash_id += FLASH_28F640C3T; - info->sector_count = 135; - info->size = 0x01000000; - sector_offset = 0x20000; - break; /* => 2x8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table - * The first 127 blocks are large, the last 8 are small. - */ - for (i = 0; i < 127; i++) { - info->start[i] = base; - base += sector_offset; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - for (i = 127; i < 135; i++) { - info->start[i] = base; - base += 0x4000; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if(*addr & 0x00200020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CONFIG_SYS_NO_FLASH */ diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c deleted file mode 100644 index 611fa4b..0000000 --- a/board/stx/stxgp3/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c deleted file mode 100644 index c80d525..0000000 --- a/board/stx/stxgp3/stxgp3.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2003, Embedded Edge, LLC - * Dan Malek, dan@embeddededge.com - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <miiphy.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -static uint64_t next_led_update; -static uint led_bit; - -int -board_early_init_f(void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void -reset_phy(void) -{ - volatile uint *blatch; - - blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; - - /* reset Giga bit Ethernet port if needed here */ - - *blatch &= ~0x000000c0; - udelay(100); - *blatch = 0x000000c1; /* Light one led, too */ - udelay(1000); - -#if 0 /* This is the port we really want to use for debugging. */ - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -#endif -} - -int -checkboard(void) -{ - printf ("Board: Silicon Tx GPPP 8560 Board\n"); - return (0); -} - -/* Blinkin' LEDS for Robert. -*/ -void -show_activity(int flag) -{ - volatile uint *blatch; - - if (next_led_update > get_ticks()) - return; - - blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; - - led_bit >>= 1; - if (led_bit == 0) - led_bit = 0x08; - *blatch = (0xc0 | led_bit); - eieio(); - next_led_update += (get_tbclk() / 4); -} - - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_stxgp3_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_stxgp3_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/stx/stxgp3/tlb.c b/board/stx/stxgp3/tlb.c deleted file mode 100644 index 7c877b2..0000000 --- a/board/stx/stxgp3/tlb.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stx/stxssa/Kconfig b/board/stx/stxssa/Kconfig deleted file mode 100644 index bd47b04..0000000 --- a/board/stx/stxssa/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_STXSSA - -config SYS_BOARD - default "stxssa" - -config SYS_VENDOR - default "stx" - -config SYS_CONFIG_NAME - default "stxssa" - -endif diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS deleted file mode 100644 index b7cc89b..0000000 --- a/board/stx/stxssa/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -STXSSA BOARD -#M: Dan Malek dan@embeddedalley.com -S: Orphan (since 2014-06) -F: board/stx/stxssa/ -F: include/configs/stxssa.h -F: configs/stxssa_defconfig -F: configs/stxssa_4M_defconfig diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile deleted file mode 100644 index b1d4b0a..0000000 --- a/board/stx/stxssa/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += stxssa.o -obj-y += law.o -obj-y += tlb.o -obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c deleted file mode 100644 index 1ccd4c5..0000000 --- a/board/stx/stxssa/ddr.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c deleted file mode 100644 index 72373f5..0000000 --- a/board/stx/stxssa/law.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xfaff_ffff Local bus 128M - * 0xfb00_0000 0xfb00_ffff Config Latch 64K - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c deleted file mode 100644 index 6e4eed8..0000000 --- a/board/stx/stxssa/stxssa.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2005, Embedded Alley Solutions, Inc. - * Dan Malek, dan@embeddedalley.com - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <miiphy.h> -#include <netdev.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -static uint64_t next_led_update; -static uint led_bit; - -void -reset_phy(void) -{ - volatile uint *blatch; -#if 0 - int i; -#endif - blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; - - /* reset Giga bit Ethernet port if needed here */ - -#if 1 - *blatch &= ~0x000000c0; - udelay(100); -#else - *blatch = 0; - asm("eieio"); - for (i=0; i<1000; i++) - udelay(1000); -#endif - *blatch = 0x000000c1; /* Light one led, too */ - udelay(1000); - -#if 0 /* This is the port we really want to use for debugging. */ - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -#endif -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int -board_early_init_f(void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - - /* Why is the phy reset done _after_ the ethernet - * initialization in arch/powerpc/lib/board.c? - * Do it here so it's done before the TSECs are used. - */ - reset_phy(); - - return 0; -} - -int -checkboard(void) -{ - printf ("Board: Silicon Tx GPPP SSA Board\n"); - return (0); -} - -/* Blinkin' LEDS for Robert. -*/ -void -show_activity(int flag) -{ - volatile uint *blatch; - - if (next_led_update > get_ticks()) - return; - - blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; - - led_bit >>= 1; - if (led_bit == 0) - led_bit = 0x08; - *blatch = (0xc0 | led_bit); - eieio(); - next_led_update += (get_tbclk() / 4); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_stxgp3_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose[] = { -#ifndef CONFIG_PCI_PNP - { config_table: pci_stxgp3_config_table,}, -#else - {}, -#endif -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(hose); -#endif /* CONFIG_PCI */ -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Initialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/stx/stxssa/tlb.c b/board/stx/stxssa/tlb.c deleted file mode 100644 index 49c630c..0000000 --- a/board/stx/stxssa/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/stxgp3_defconfig b/configs/stxgp3_defconfig deleted file mode 100644 index 86afe88..0000000 --- a/configs/stxgp3_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXGP3=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/stxssa_4M_defconfig b/configs/stxssa_4M_defconfig deleted file mode 100644 index 7547906..0000000 --- a/configs/stxssa_4M_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXSSA=y -CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M" -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/stxssa_defconfig b/configs/stxssa_defconfig deleted file mode 100644 index c072417..0000000 --- a/configs/stxssa_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXSSA=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h deleted file mode 100644 index 6676f37..0000000 --- a/include/configs/stxgp3.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2003 Embedded Edge, LLC - * Dan Malek dan@embeddededge.com - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 board. - * - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ -#define CONFIG_MPC8560 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* sysclk for MPC85xx - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ - -/* Blinkin' LEDs for Robert :-) -*/ -#define CONFIG_SHOW_ACTIVITY 1 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* Localbus SDRAM is an option, not all boards have it. - * This address, however, is used to configure a 256M local bus - * window that includes the Config latch below. - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* The configuration latch is Chip Select 1. - * It's an 8-bit latch in the lower 8 bits of the word. - */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ -#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ -#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#endif -#define CONFIG_SYS_CCSRBAR 0xfdf00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#if 0 -#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ -#else -/* I did the 'if 0' so we could keep the syntax above if ever needed. */ -#undef CONFIG_SYS_I2C_NOPROBES -#endif - -/* RapdIO Map configuration, mapped 1:1. -*/ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ - -/* Standard 8560 PCI addressing, mapped 1:1. -*/ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ - -#if defined(CONFIG_PCI) /* PCI Ethernet card */ - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#if 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) -#else - #define CONFIG_SYS_FCC_PSMR 0 -#endif - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* MDIO is done through the TSEC0 control. -*/ -#define CONFIG_MII /* MII PHY management */ -#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#endif - -/* Environment */ -/* We use the top boot sector flash, so we have some 16K sectors for env - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) - #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" -#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_CMD_ELF -#endif - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 -#define CONFIG_GATEWAYIP 192.168.85.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_GP3 -#define CONFIG_ROOTPATH "/gppproot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h deleted file mode 100644 index 5b1f3ab..0000000 --- a/include/configs/stxssa.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * (C) Copyright 2005 Embedded Alley Solutions, Inc. - * Dan Malek dan@embeddedalley.com - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA board. - * - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ -#define CONFIG_MPC8560 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_PCI /* PCI ethernet support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* sysclk for MPC85xx - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ - -/* Blinkin' LEDs for Robert :-) -*/ -#define CONFIG_SHOW_ACTIVITY 1 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* Localbus connector. There are many options that can be - * connected here, including sdram or lots of flash. - * This address, however, is used to configure a 256M local bus - * window that includes the Config latch below. - */ -#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ -#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */ - -/* There are various flash options used, we configure for the largest, - * which is 64Mbytes. The CFI works fine and will discover the proper - * sizes. - */ -#ifdef CONFIG_STXSSA_4M -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ -#else -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ -#endif -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */ -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7) - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_PROTECTION - -/* The configuration latch is Chip Select 1. - * It's an 8-bit latch in the lower 8 bits of the word. - */ -#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ -#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#endif - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#undef CONFIG_SYS_I2C_NOPROBES - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C EEPROM. AT24C32, we keep our environment in here. -*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Standard 8555 PCI mapping. - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ - -#if defined(CONFIG_PCI) /* PCI Ethernet card */ -#define CONFIG_MPC85XX_PCI2 1 -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#define CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#if 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) -#else - #define CONFIG_SYS_FCC_PSMR 0 -#endif - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* MDIO is done through the TSEC0 control. -*/ -#define CONFIG_MII /* MII PHY management */ -#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#endif - -/* Environment - default config is in flash, see below */ -#if 0 /* in EEPROM */ -# define CONFIG_ENV_IS_IN_EEPROM 1 -# define CONFIG_ENV_OFFSET 0 -# define CONFIG_ENV_SIZE 2048 -#else /* in flash */ -# define CONFIG_ENV_IS_IN_FLASH 1 -# ifdef CONFIG_STXSSA_4M -# define CONFIG_ENV_SECT_SIZE 0x20000 -# else /* default configuration - 64 MiB flash */ -# define CONFIG_ENV_SECT_SIZE 0x40000 -# endif -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x4000 -# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_CMD_ELF -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -/* - * Environment in EEPROM is compatible with different flash sector sizes, - * but only little space is available, so we use a very simple setup. - * With environment in flash, we use a more powerful default configuration. - */ -#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ -#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 -#define CONFIG_GATEWAYIP 192.168.85.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_SSA -#define CONFIG_ROOTPATH "/gppproot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x1000000 - -#else /* ENV IS IN FLASH -- use a full-blown envionment */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=gp3ssa\0" \ - "bootfile=/tftpboot/gp3ssa/uImage\0" \ - "loadaddr=400000\0" \ - "netdev=eth0\0" \ - "consdev=ttyS1\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC200000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* CONFIG_ENV_IS_IN_EEPROM */ - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/freescale/mpc8541cds/Kconfig | 12 - board/freescale/mpc8541cds/MAINTAINERS | 7 - board/freescale/mpc8541cds/Makefile | 12 - board/freescale/mpc8541cds/ddr.c | 56 ---- board/freescale/mpc8541cds/law.c | 42 --- board/freescale/mpc8541cds/mpc8541cds.c | 427 ----------------------------- board/freescale/mpc8541cds/tlb.c | 96 ------- configs/MPC8541CDS_defconfig | 3 - configs/MPC8541CDS_legacy_defconfig | 4 - include/configs/MPC8541CDS.h | 465 -------------------------------- 11 files changed, 1128 deletions(-) delete mode 100644 board/freescale/mpc8541cds/Kconfig delete mode 100644 board/freescale/mpc8541cds/MAINTAINERS delete mode 100644 board/freescale/mpc8541cds/Makefile delete mode 100644 board/freescale/mpc8541cds/ddr.c delete mode 100644 board/freescale/mpc8541cds/law.c delete mode 100644 board/freescale/mpc8541cds/mpc8541cds.c delete mode 100644 board/freescale/mpc8541cds/tlb.c delete mode 100644 configs/MPC8541CDS_defconfig delete mode 100644 configs/MPC8541CDS_legacy_defconfig delete mode 100644 include/configs/MPC8541CDS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 33123db..912783d 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -43,9 +43,6 @@ config TARGET_P5040DS config TARGET_MPC8536DS bool "Support MPC8536DS"

-config TARGET_MPC8541CDS - bool "Support MPC8541CDS" - config TARGET_MPC8544DS bool "Support MPC8544DS"

@@ -151,7 +148,6 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8541cds/Kconfig" source "board/freescale/mpc8544ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/mpc8555cds/Kconfig" diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig deleted file mode 100644 index 034eab2..0000000 --- a/board/freescale/mpc8541cds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8541CDS - -config SYS_BOARD - default "mpc8541cds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8541CDS" - -endif diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS deleted file mode 100644 index d421b12..0000000 --- a/board/freescale/mpc8541cds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8541CDS BOARD -#M: Kumar Gala kumar.gala@freescale.com -S: Orphan (since 2014-06) -F: board/freescale/mpc8541cds/ -F: include/configs/MPC8541CDS.h -F: configs/MPC8541CDS_defconfig -F: configs/MPC8541CDS_legacy_defconfig diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile deleted file mode 100644 index 78af4b8..0000000 --- a/board/freescale/mpc8541cds/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8541cds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c deleted file mode 100644 index d2ac6c4..0000000 --- a/board/freescale/mpc8541cds/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c deleted file mode 100644 index 39df3f1..0000000 --- a/board/freescale/mpc8541cds/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c deleted file mode 100644 index 7b264dd..0000000 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <libfdt.h> -#include <fdt_support.h> - -#include "../common/cadmus.h" -#include "../common/eeprom.h" -#include "../common/via.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - char buf[32]; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf("PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - strmhz(buf, pci1_speed), - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf("PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf("PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - uint temp_lbcdll; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - - } else { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * Determine which address lines to use baed on CPU board rev. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= LSDMR_BSMA1617; - } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= LSDMR_BSMA1516; - } else { - /* - * Assume something unable to identify itself is - * really old, and likely has lines 16/17 mapped. - */ - lsdmr_common |= LSDMR_BSMA1617; - } - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CONFIG_PCI) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - -#endif /* CONFIG_PCI */ - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(hose); -#endif -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose[0].last_busno - hose[0].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif -#ifdef CONFIG_MPC85XX_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = hose[1].last_busno - hose[1].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c deleted file mode 100644 index fff3b4a..0000000 --- a/board/freescale/mpc8541cds/tlb.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig deleted file mode 100644 index bc9c246..0000000 --- a/configs/MPC8541CDS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8541CDS=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig deleted file mode 100644 index 55478ab..0000000 --- a/configs/MPC8541CDS_legacy_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8541CDS=y -CONFIG_SYS_EXTRA_OPTIONS="LEGACY" diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h deleted file mode 100644 index d24d1ca..0000000 --- a/include/configs/MPC8541CDS.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8541cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8541 1 /* MPC8541 specific */ -#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_FSL_VIA - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xff001001 - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CONFIG_FSL_CADMUS - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CONFIG_SYS_BR3_PRELIM 0xf8000801 -#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ - -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - -#if defined(CONFIG_PCI) - -#define CONFIG_MPC85XX_PCI2 -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/freescale/mpc8548cds/Kconfig | 12 - board/freescale/mpc8548cds/MAINTAINERS | 8 - board/freescale/mpc8548cds/Makefile | 12 - board/freescale/mpc8548cds/ddr.c | 56 --- board/freescale/mpc8548cds/law.c | 19 - board/freescale/mpc8548cds/mpc8548cds.c | 358 ------------------- board/freescale/mpc8548cds/tlb.c | 87 ----- configs/MPC8548CDS_36BIT_defconfig | 4 - configs/MPC8548CDS_defconfig | 3 - configs/MPC8548CDS_legacy_defconfig | 4 - include/configs/MPC8548CDS.h | 605 -------------------------------- 12 files changed, 1172 deletions(-) delete mode 100644 board/freescale/mpc8548cds/Kconfig delete mode 100644 board/freescale/mpc8548cds/MAINTAINERS delete mode 100644 board/freescale/mpc8548cds/Makefile delete mode 100644 board/freescale/mpc8548cds/ddr.c delete mode 100644 board/freescale/mpc8548cds/law.c delete mode 100644 board/freescale/mpc8548cds/mpc8548cds.c delete mode 100644 board/freescale/mpc8548cds/tlb.c delete mode 100644 configs/MPC8548CDS_36BIT_defconfig delete mode 100644 configs/MPC8548CDS_defconfig delete mode 100644 configs/MPC8548CDS_legacy_defconfig delete mode 100644 include/configs/MPC8548CDS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 1922045..d05f943 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -43,9 +43,6 @@ config TARGET_P5040DS config TARGET_MPC8536DS bool "Support MPC8536DS"

-config TARGET_MPC8548CDS - bool "Support MPC8548CDS" - config TARGET_MPC8555CDS bool "Support MPC8555CDS"

@@ -145,7 +142,6 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/mpc8555cds/Kconfig" source "board/freescale/mpc8560ads/Kconfig" source "board/freescale/mpc8568mds/Kconfig" diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig deleted file mode 100644 index 09f3b0b..0000000 --- a/board/freescale/mpc8548cds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8548CDS - -config SYS_BOARD - default "mpc8548cds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8548CDS" - -endif diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS deleted file mode 100644 index 6f22922..0000000 --- a/board/freescale/mpc8548cds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC8548CDS BOARD -#M: - -S: Maintained -F: board/freescale/mpc8548cds/ -F: include/configs/MPC8548CDS.h -F: configs/MPC8548CDS_defconfig -F: configs/MPC8548CDS_36BIT_defconfig -F: configs/MPC8548CDS_legacy_defconfig diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile deleted file mode 100644 index f797df2..0000000 --- a/board/freescale/mpc8548cds/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8548cds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c deleted file mode 100644 index b31ea34..0000000 --- a/board/freescale/mpc8548cds/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c deleted file mode 100644 index 5578fc2..0000000 --- a/board/freescale/mpc8548cds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - /* LBC window - maps 256M */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c deleted file mode 100644 index ca9b43c..0000000 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <tsec.h> -#include <fsl_mdio.h> -#include <netdev.h> - -#include "../common/cadmus.h" -#include "../common/eeprom.h" -#include "../common/via.h" - -void local_bus_init(void); - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint cpu_board_rev = get_cpu_board_revision (); - - puts("Board: MPC8548CDS"); - printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", - get_board_version(), pci_slot); - printf(" Daughtercard Rev: %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - /* - * Initialize local bus. - */ - local_bus_init (); - - /* - * Hack TSEC 3 and 4 IO voltages. - */ - gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ - - ecm->eedr = 0xffffffff; /* clear ecm errors */ - ecm->eeer = 0xffffffff; /* enable ecm errors */ - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - gur->lbiuiplldcr1 = 0x00078080; - if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; - } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; - } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; - } - - lbc->lcrr |= 0x00030000; - - asm("sync;isync;msync"); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * MPC8548 uses "new" 15-16 style addressing. - */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - char buf[32]; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - -#ifdef CONFIG_PCI1 - pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - strmhz(buf, pci_speed), - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - - pci1_hose.config_table = pci_mpc85xxcds_config_table; - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - -#ifdef CONFIG_PCIX_CHECK - if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); - } -#endif - } else { - printf("PCI1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif - -#ifdef CONFIG_PCI2 -{ - uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - if (pci_dual) { - printf("PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf("PCI2: disabled\n"); - } -} -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ -#endif /* CONFIG_PCI2 */ - - fsl_pcie_init_board(first_free_busno); -} - -void configure_rgmii(void) -{ - unsigned short temp; - - /* Change the resistors for the PHY */ - /* This is needed to get the RGMII working for the 1.3+ - * CDS cards */ - if (get_board_version() == 0x13) { - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 18); - - miiphy_read(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, &temp); - - temp = (temp & 0xf03f); - temp |= 2 << 9; /* 36 ohm */ - temp |= 2 << 6; /* 39 ohm */ - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, temp); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 3); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, 0x8000); - } - - return; -} - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif -#ifdef CONFIG_TSEC4 - /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 4); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - configure_rgmii(); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_pci_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c deleted file mode 100644 index 363e043..0000000 --- a/board/freescale/mpc8548cds/tlb.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2008, 2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* - * Entry 0: - * FLASH(cover boot page) 16M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * Entry 1: - * CCSRBAR 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 2: - * LBC SDRAM 64M Cacheable, non-guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, - CONFIG_SYS_LBC_SDRAM_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 2, BOOKE_PAGESZ_64M, 1), - - /* - * Entry 3: - * CADMUS registers 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 4: - * PCI and PCIe MEM 1G Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* - * Entry 5: - * PCI1 IO 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 6: - * PCIe IO 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig deleted file mode 100644 index dfe1fca..0000000 --- a/configs/MPC8548CDS_36BIT_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8548CDS=y -CONFIG_SYS_EXTRA_OPTIONS="36BIT" diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig deleted file mode 100644 index ba52e94..0000000 --- a/configs/MPC8548CDS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8548CDS=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig deleted file mode 100644 index 69c44af..0000000 --- a/configs/MPC8548CDS_legacy_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8548CDS=y -CONFIG_SYS_EXTRA_OPTIONS="LEGACY" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h deleted file mode 100644 index a80221a..0000000 --- a/include/configs/MPC8548CDS.h +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8548cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#endif - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI /* enable any pci type devices */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_FSL_VIA - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ -/* - * Physical Address Map - * - * 32bit: - * 0x0000_0000 0x7fff_ffff DDR 2G cacheable - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable - * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable - * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable - * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable - * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable - * - * 36bit: - * 0x00000_0000 0x07fff_ffff DDR 2G cacheable - * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable - * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable - * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable - * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable - * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable - * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable - * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable - * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable - * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable - * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable - * - */ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_BR0_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_HWCONFIG /* enable hwconfig */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull -#else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ - | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CONFIG_FSL_CADMUS - -#define CADMUS_BASE_ADDR 0xf8000000 -#ifdef CONFIG_PHYS_64BIT -#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull -#else -#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR -#endif -#define CONFIG_SYS_BR3_PRELIM \ - (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull -#else -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ -#endif - -/* - * RapidIO MMU - */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define CONFIG_PHY_MARVELL - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: eTSEC[0-3] */ -#define CONFIG_ETHPRIME "eTSEC0" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "8548cds/uImage.uboot" -#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ecc=off\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/freescale/mpc8560ads/Kconfig | 12 - board/freescale/mpc8560ads/MAINTAINERS | 6 - board/freescale/mpc8560ads/Makefile | 11 - board/freescale/mpc8560ads/ddr.c | 46 --- board/freescale/mpc8560ads/law.c | 42 --- board/freescale/mpc8560ads/mpc8560ads.c | 462 ------------------------------ board/freescale/mpc8560ads/tlb.c | 95 ------- configs/MPC8560ADS_defconfig | 3 - include/configs/MPC8560ADS.h | 488 -------------------------------- 10 files changed, 1169 deletions(-) delete mode 100644 board/freescale/mpc8560ads/Kconfig delete mode 100644 board/freescale/mpc8560ads/MAINTAINERS delete mode 100644 board/freescale/mpc8560ads/Makefile delete mode 100644 board/freescale/mpc8560ads/ddr.c delete mode 100644 board/freescale/mpc8560ads/law.c delete mode 100644 board/freescale/mpc8560ads/mpc8560ads.c delete mode 100644 board/freescale/mpc8560ads/tlb.c delete mode 100644 configs/MPC8560ADS_defconfig delete mode 100644 include/configs/MPC8560ADS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index af73a06..9c58526 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -43,9 +43,6 @@ config TARGET_P5040DS config TARGET_MPC8536DS bool "Support MPC8536DS"

-config TARGET_MPC8560ADS - bool "Support MPC8560ADS" - config TARGET_MPC8568MDS bool "Support MPC8568MDS"

@@ -139,7 +136,6 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8560ads/Kconfig" source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig deleted file mode 100644 index 828c068..0000000 --- a/board/freescale/mpc8560ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8560ADS - -config SYS_BOARD - default "mpc8560ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8560ADS" - -endif diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS deleted file mode 100644 index 96e6da2..0000000 --- a/board/freescale/mpc8560ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8560ADS BOARD -#M: Kumar Gala kumar.gala@freescale.com -S: Orphan (since 2014-06) -F: board/freescale/mpc8560ads/ -F: include/configs/MPC8560ADS.h -F: configs/MPC8560ADS_defconfig diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile deleted file mode 100644 index 685168e..0000000 --- a/board/freescale/mpc8560ads/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8560ads.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c deleted file mode 100644 index 41d4cfe..0000000 --- a/board/freescale/mpc8560ads/ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c deleted file mode 100644 index 41f2e02..0000000 --- a/board/freescale/mpc8560ads/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c deleted file mode 100644 index f99d639..0000000 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_lbc.h> - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -void local_bus_init(void); - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -/* - * MPC8560ADS Board Status & Control Registers - */ -typedef struct bcsr_ { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; -} bcsr_t; - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -} - - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c deleted file mode 100644 index d5ee791..0000000 --- a/board/freescale/mpc8560ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig deleted file mode 100644 index aa84d28..0000000 --- a/configs/MPC8560ADS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8560ADS=y diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h deleted file mode 100644 index 5a481d5..0000000 --- a/include/configs/MPC8560ADS.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8560ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ -#define CONFIG_MPC8560 1 - -/* - * default CCARBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ - | LSDMR_RFCR5 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CONFIG_SYS_BR4_PRELIM 0xf8000801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#ifdef CONFIG_TSEC_ENET - -#ifndef CONFIG_MII -#define CONFIG_MII 1 /* MII PHY management */ -#endif -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -#ifndef CONFIG_MII -#define CONFIG_MII 1 /* MII PHY management */ -#endif - -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyCPM\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8560ads.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/freescale/mpc8569mds/Kconfig | 12 - board/freescale/mpc8569mds/MAINTAINERS | 7 - board/freescale/mpc8569mds/Makefile | 13 - board/freescale/mpc8569mds/README | 77 ----- board/freescale/mpc8569mds/bcsr.c | 50 --- board/freescale/mpc8569mds/bcsr.h | 72 ---- board/freescale/mpc8569mds/ddr.c | 66 ---- board/freescale/mpc8569mds/law.c | 41 --- board/freescale/mpc8569mds/mpc8569mds.c | 585 -------------------------------- board/freescale/mpc8569mds/tlb.c | 95 ------ configs/MPC8569MDS_ATM_defconfig | 4 - configs/MPC8569MDS_defconfig | 3 - include/configs/MPC8569MDS.h | 583 ------------------------------- 14 files changed, 1612 deletions(-) delete mode 100644 board/freescale/mpc8569mds/Kconfig delete mode 100644 board/freescale/mpc8569mds/MAINTAINERS delete mode 100644 board/freescale/mpc8569mds/Makefile delete mode 100644 board/freescale/mpc8569mds/README delete mode 100644 board/freescale/mpc8569mds/bcsr.c delete mode 100644 board/freescale/mpc8569mds/bcsr.h delete mode 100644 board/freescale/mpc8569mds/ddr.c delete mode 100644 board/freescale/mpc8569mds/law.c delete mode 100644 board/freescale/mpc8569mds/mpc8569mds.c delete mode 100644 board/freescale/mpc8569mds/tlb.c delete mode 100644 configs/MPC8569MDS_ATM_defconfig delete mode 100644 configs/MPC8569MDS_defconfig delete mode 100644 include/configs/MPC8569MDS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 2e4edb3..136f3be 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -43,9 +43,6 @@ config TARGET_P5040DS config TARGET_MPC8536DS bool "Support MPC8536DS"

-config TARGET_MPC8569MDS - bool "Support MPC8569MDS" - config TARGET_MPC8572DS bool "Support MPC8572DS"

@@ -133,7 +130,6 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" source "board/freescale/p1022ds/Kconfig" diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig deleted file mode 100644 index 4871857..0000000 --- a/board/freescale/mpc8569mds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8569MDS - -config SYS_BOARD - default "mpc8569mds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8569MDS" - -endif diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS deleted file mode 100644 index c181407..0000000 --- a/board/freescale/mpc8569mds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8569MDS BOARD -#M: - -S: Maintained -F: board/freescale/mpc8569mds/ -F: include/configs/MPC8569MDS.h -F: configs/MPC8569MDS_defconfig -F: configs/MPC8569MDS_ATM_defconfig diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile deleted file mode 100644 index 5f6e021..0000000 --- a/board/freescale/mpc8569mds/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2004-2009 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8569mds.o -obj-y += bcsr.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README deleted file mode 100644 index 3d12a96..0000000 --- a/board/freescale/mpc8569mds/README +++ /dev/null @@ -1,77 +0,0 @@ -Overview --------- -MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform -I/O Board). The mpc8569 PowerTM processor is mounted on PB board. - -Building U-boot ------------ - make MPC8569MDS_config - make - -Memory Map ----------- -0x0000_0000 0x7fff_ffff DDR 2G -0xa000_0000 0xbfff_ffff PCIe MEM 512MB -0xe000_0000 0xe00f_ffff CCSRBAR 1M -0xe280_0000 0xe2ff_ffff PCIe I/O 8M -0xc000_0000 0xdfff_ffff SRIO 512MB -0xf000_0000 0xf3ff_ffff SDRAM 64MB -0xf800_0000 0xf800_7fff BCSR 32KB -0xf800_8000 0xf800_ffff PIB (CS4) 32KB -0xf801_0000 0xf801_7fff PIB (CS5) 32KB -0xfe00_0000 0xffff_ffff Flash 32MB - - -Flashing u-boot Images ---------------- - -Use the following commands to program u-boot image into flash: - - => tftp 1000000 u-boot.bin - => protect off all - => erase fff80000 ffffffff - => cp.b 1000000 fff80000 80000 - - -Setting the correct MAC addresses ------------------------ -The command - "mac", is introduced to set on-board system EEPROM in the format -defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC -addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when -we first get the board. The commands are as follows: - => mac i NXID /* Set NXID to this EEPROM */ - => mac e 01 /* Set Errata, this value is not defined by hardware - designer, we can set whatever we want */ - => mac n a0 /* Set Serial Number. This is not defined by hardware - designer, we can set whatever we want */ - => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */ - - => mac p 8 /* Set the number of mac ports, it should be 8 */ - => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac - address, you can refer to the value on - the sticker of the rear side of the board - */ - ..... - => mac 7 xx:xx:xx:xx:xx:xx - => mac read - => mac save - -After resetting the board, the ethxaddrs will be filled with the mac addresses -if such environment variables are blank(never been set before). If the ethxaddr -has been set but we want to update it, we can use the following commands: - => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */ - => save - => reset - - -Programming the ucode to flash ---------------------------------- -MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's -IRAM so that the QE can work. The ucode binary can be downloaded from -http://opensource.freescale.com/firmware/, and it must be programmed to -the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot -hangs at "Net:" - - -Please note the above two steps(setting mac addresses and programming ucode) are -very important to get the board booting up and working properly. diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c deleted file mode 100644 index 178d9f8..0000000 --- a/board/freescale/mpc8569mds/bcsr.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -#include "bcsr.h" - -void enable_8569mds_flash_write(void) -{ - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); -} - -void disable_8569mds_flash_write(void) -{ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); -} - -void enable_8569mds_qe_uec(void) -{ -#if defined(CONFIG_SYS_UCC_RGMII_MODE) - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), - BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), - BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), - BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), - BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); -#elif defined(CONFIG_SYS_UCC_RMII_MODE) - /* Set UCC1-4 working at RMII mode */ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), - BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), - BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), - BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), - BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); -#endif -} - -void disable_8569mds_brd_eeprom_write_protect(void) -{ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); -} diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h deleted file mode 100644 index 6f4d139..0000000 --- a/board/freescale/mpc8569mds/bcsr.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include <common.h> - -/* BCSR Bit definitions*/ -/****************************************/ -/* BCSR defines */ -/****************************************/ -#define BCSR6_UPC1_EN 0x80 -#define BCSR6_UPC1_POS_EN 0x40 -#define BCSR6_UPC1_ADDR_EN 0x20 -#define BCSR6_UPC1_DEV2 0x10 -#define BCSR6_SD_CARD_1BIT 0x08 -#define BCSR6_SD_CARD_4BITS 0x04 -#define BCSR6_TDM2G_EN 0x02 -#define BCSR6_UCC7_RMII_EN 0x01 - -#define BCSR7_UCC1_GETH_EN 0x80 -#define BCSR7_UCC1_RGMII_EN 0x40 -#define BCSR7_UCC1_RTBI_EN 0x20 -#define BCSR7_GETHRST_MRVL 0x04 -#define BCSR7_BRD_WRT_PROTECT 0x02 - -#define BCSR8_UCC2_GETH_EN 0x80 -#define BCSR8_UCC2_RGMII_EN 0x40 -#define BCSR8_UCC2_RTBI_EN 0x20 -#define BCSR8_UEM_MARVEL_RESET 0x02 - -#define BCSR9_UCC3_GETH_EN 0x80 -#define BCSR9_UCC3_RGMII_EN 0x40 -#define BCSR9_UCC3_RTBI_EN 0x20 -#define BCSR9_UCC3_RMII_EN 0x10 -#define BCSR9_UCC3_UEM_MICREL 0x01 - -#define BCSR10_UCC4_GETH_EN 0x80 -#define BCSR10_UCC4_RGMII_EN 0x40 -#define BCSR10_UCC4_RTBI_EN 0x20 - -#define BCSR11_LED0 0x40 -#define BCSR11_LED1 0x20 -#define BCSR11_LED2 0x10 - -#define BCSR12_UCC6_RMII_EN 0x20 -#define BCSR12_UCC8_RMII_EN 0x20 - -#define BCSR15_SMII6_DIS 0x08 -#define BCSR15_SMII8_DIS 0x04 -#define BCSR15_QEUART_EN 0x01 - -#define BCSR16_UPC1_DEV2 0x02 - -#define BCSR17_nUSBEN 0x80 -#define BCSR17_nUSBLOWSPD 0x40 -#define BCSR17_USBVCC 0x20 -#define BCSR17_USBMODE 0x10 -#define BCSR17_FLASH_nWP 0x01 - -/*BCSR Utils functions*/ - -void enable_8569mds_flash_write(void); -void disable_8569mds_flash_write(void); -void enable_8569mds_qe_uec(void); -void disable_8569mds_brd_eeprom_write_protect(void); - -#endif /* __BCSR_H_ */ diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c deleted file mode 100644 index ef404b1..0000000 --- a/board/freescale/mpc8569mds/ddr.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 4; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0xff; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 2; - - /* - * Enable half drive strength - */ - popts->half_strength_driver_enable = 1; - - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x4; - - /* Rtt and Rtt_W override */ - popts->rtt_override = 1; - popts->rtt_override_value = DDR3_RTT_60_OHM; - popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ -} diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c deleted file mode 100644 index a388ad1..0000000 --- a/board/freescale/mpc8569mds/law.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *3) 0xc000_0000 0xdfff_ffff SRIO 512MB - *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c deleted file mode 100644 index 836578f..0000000 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hwconfig.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <i2c.h> -#include <ioports.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <fsl_esdhc.h> -#include <phy.h> - -#include "bcsr.h" -#if defined(CONFIG_PQ_MDS_PIB) -#include "../common/pq-mds-pib.h" -#endif - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* QE_MUX_MDC */ - {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ - - /* QE_MUX_MDIO */ - {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ - -#if defined(CONFIG_SYS_UCC_RGMII_MODE) - /* UCC_1_RGMII */ - {2, 11, 2, 0, 1}, /* CLK12 */ - {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ - {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ - {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ - {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ - {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ - {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ - {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ - - /* UCC_2_RGMII */ - {2, 16, 2, 0, 3}, /* CLK17 */ - {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ - {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ - {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ - {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ - {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ - {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ - {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ - {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ - {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ - {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ - {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ - {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ - - /* UCC_3_RGMII */ - {2, 11, 2, 0, 1}, /* CLK12 */ - {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ - {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ - {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ - {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ - {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ - {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ - {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ - {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ - {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ - {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ - {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ - {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ - - /* UCC_4_RGMII */ - {2, 16, 2, 0, 3}, /* CLK17 */ - {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ - {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ - {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ - {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ - {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ - {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ - {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ - {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ - {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ - {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ - {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ - {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ - -#elif defined(CONFIG_SYS_UCC_RMII_MODE) - /* UCC_1_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ - - /* UCC_2_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ - {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ - {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ - {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ - {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ - {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ - - /* UCC_3_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ - {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ - {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ - {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ - {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ - {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ - - /* UCC_4_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ - {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ - {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ - {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ - {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ - {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ -#endif - - /* UART1 is muxed with QE PortF bit [9-12].*/ - {5, 12, 2, 0, 3}, /* UART1_SIN */ - {5, 9, 1, 0, 3}, /* UART1_SOUT */ - {5, 10, 2, 0, 3}, /* UART1_CTS_B */ - {5, 11, 1, 0, 2}, /* UART1_RTS_B */ - - /* QE UART */ - {0, 19, 1, 0, 2}, /* QEUART_TX */ - {1, 17, 2, 0, 3}, /* QEUART_RX */ - {0, 25, 1, 0, 1}, /* QEUART_RTS */ - {1, 23, 2, 0, 1}, /* QEUART_CTS */ - - /* QE USB */ - {5, 3, 1, 0, 1}, /* USB_OE */ - {5, 4, 1, 0, 2}, /* USB_TP */ - {5, 5, 1, 0, 2}, /* USB_TN */ - {5, 6, 2, 0, 2}, /* USB_RP */ - {5, 7, 2, 0, 1}, /* USB_RX */ - {5, 8, 2, 0, 1}, /* USB_RN */ - {2, 4, 2, 0, 2}, /* CLK5 */ - - /* SPI Flash, M25P40 */ - {4, 27, 3, 0, 1}, /* SPI_MOSI */ - {4, 28, 3, 0, 1}, /* SPI_MISO */ - {4, 29, 3, 0, 1}, /* SPI_CLK */ - {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ - - {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ -}; - -void local_bus_init(void); - -int board_early_init_f (void) -{ - /* - * Initialize local bus. - */ - local_bus_init (); - - enable_8569mds_flash_write(); - -#ifdef CONFIG_QE - enable_8569mds_qe_uec(); -#endif - -#if CONFIG_SYS_I2C2_OFFSET - /* Enable I2C2 signals instead of SD signals */ - volatile struct ccsr_gur *gur; - gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); - gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; - gur->plppar1 |= PLPPAR1_I2C2_VAL; - gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; - gur->plpdir1 |= PLPDIR1_I2C2_VAL; - - disable_8569mds_brd_eeprom_write_protect(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_NAND_BASE; - const u8 flash_esel = 0; - - /* - * Remap Boot flash to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, /* ts, esel */ - BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ - - return 0; -} - -int checkboard (void) -{ - printf ("Board: 8569 MDS\n"); - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -phys_size_t fixed_sdram(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - uint d_init; - - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); -#if defined (CONFIG_DDR_ECC) - out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); - out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); - out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); -#endif - udelay(500); - - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n\n"); - udelay(500); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - out_be32(&gur->lbiuiplldcr1, 0x00078080); - if (clkdiv == 16) - out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); - else if (clkdiv == 8) - out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); - else if (clkdiv == 4) - out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); - - out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); -} - -static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias) -{ - const char *status = "disabled"; - int off; - int err; - - off = fdt_path_offset(blob, alias); - if (off < 0) { - printf("WARNING: could not find %s alias: %s.\n", alias, - fdt_strerror(off)); - return; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for serial0: %s.\n", - fdt_strerror(err)); - return; - } -} - -/* - * Because of an erratum in prototype boards it is impossible to use eSDHC - * without disabling UART0 (which makes it quite easy to 'brick' the board - * by simply issung 'setenv hwconfig esdhc', and not able to interact with - * U-Boot anylonger). - * - * So, but default we assume that the board is a prototype, which is a most - * safe assumption. There is no way to determine board revision from a - * register, so we use hwconfig. - */ - -static int prototype_board(void) -{ - if (hwconfig_subarg("board", "rev", NULL)) - return hwconfig_subarg_cmp("board", "rev", "prototype"); - return 1; -} - -static int esdhc_disables_uart0(void) -{ - return prototype_board() || - hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); -} - -static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - const char *devtype = "serial"; - const char *compat = "ucc_uart"; - const char *clk = "brg9"; - u32 portnum = 0; - int off = -1; - - if (!hwconfig("qe_uart")) - return; - - if (hwconfig("esdhc") && esdhc_disables_uart0()) { - printf("QE UART: won't enable with esdhc.\n"); - return; - } - - fdt_board_disable_serial(blob, bd, "serial1"); - - while (1) { - const u32 *idx; - int len; - - off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); - if (off < 0) { - printf("WARNING: unable to fixup device tree for " - "QE UART\n"); - return; - } - - idx = fdt_getprop(blob, off, "cell-index", &len); - if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) - continue; - break; - } - - fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); - fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); - fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); - fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); - fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); - - setbits_8(&bcsr[15], BCSR15_QEUART_EN); -} - -#ifdef CONFIG_FSL_ESDHC - -int board_mmc_init(bd_t *bd) -{ - struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - u8 bcsr6 = BCSR6_SD_CARD_1BIT; - - if (!hwconfig("esdhc")) - return 0; - - printf("Enabling eSDHC...\n" - " For eSDHC to function, I2C2 "); - if (esdhc_disables_uart0()) { - printf("and UART0 should be disabled.\n"); - printf(" Redirecting stderr, stdout and stdin to UART1...\n"); - console_assign(stderr, "eserial1"); - console_assign(stdout, "eserial1"); - console_assign(stdin, "eserial1"); - printf("Switched to UART1 (initial log has been printed to " - "UART0).\n"); - - clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, - PLPPAR1_ESDHC_4BITS_VAL); - clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, - PLPDIR1_ESDHC_4BITS_VAL); - bcsr6 |= BCSR6_SD_CARD_4BITS; - } else { - printf("should be disabled.\n"); - } - - /* Assign I2C2 signals to eSDHC. */ - clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, - PLPPAR1_ESDHC_VAL); - clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, - PLPDIR1_ESDHC_VAL); - - /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ - setbits_8(&bcsr[6], bcsr6); - - return fsl_esdhc_mmc_init(bd); -} - -static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) -{ - const char *status = "disabled"; - int off = -1; - - if (!hwconfig("esdhc")) - return; - - if (esdhc_disables_uart0()) - fdt_board_disable_serial(blob, bd, "serial0"); - - while (1) { - const u32 *idx; - int len; - - off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); - if (off < 0) - break; - - idx = fdt_getprop(blob, off, "cell-index", &len); - if (!idx || len != sizeof(*idx)) - continue; - - if (*idx == 1) { - fdt_setprop(blob, off, "status", status, - strlen(status) + 1); - break; - } - } - - if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { - off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); - if (off < 0) { - printf("WARNING: could not find esdhc node\n"); - return; - } - fdt_delprop(blob, off, "sdhci,1-bit-only"); - } -} -#else -static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} -#endif - -static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - - if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) - clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); - else - setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); - - if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { - clrbits_8(&bcsr[17], BCSR17_USBVCC); - clrbits_8(&bcsr[17], BCSR17_USBMODE); - do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", - "peripheral", sizeof("peripheral"), 1); - } else { - setbits_8(&bcsr[17], BCSR17_USBVCC); - setbits_8(&bcsr[17], BCSR17_USBMODE); - } - - clrbits_8(&bcsr[17], BCSR17_nUSBEN); -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ -#if defined(CONFIG_PQ_MDS_PIB) - pib_init(); -#endif - - fsl_pcie_init_board(0); -} -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_SYS_UCC_RMII_MODE) - int nodeoff, off, err; - unsigned int val; - const u32 *ph; - const u32 *index; - - /* fixup device tree for supporting rmii mode */ - nodeoff = -1; - while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, - "ucc_geth")) >= 0) { - err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", - "clk16"); - if (err < 0) { - printf("WARNING: could not set tx-clock-name %s.\n", - fdt_strerror(err)); - break; - } - - err = fdt_fixup_phy_connection(blob, nodeoff, - PHY_INTERFACE_MODE_RMII); - - if (err < 0) { - printf("WARNING: could not set phy-connection-type " - "%s.\n", fdt_strerror(err)); - break; - } - - index = fdt_getprop(blob, nodeoff, "cell-index", 0); - if (index == NULL) { - printf("WARNING: could not get cell-index of ucc\n"); - break; - } - - ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); - if (ph == NULL) { - printf("WARNING: could not get phy-handle of ucc\n"); - break; - } - - off = fdt_node_offset_by_phandle(blob, *ph); - if (off < 0) { - printf("WARNING: could not get phy node %s.\n", - fdt_strerror(err)); - break; - } - - val = 0x7 + *index; /* RMII phy address starts from 0x8 */ - - err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); - if (err < 0) { - printf("WARNING: could not set reg for phy-handle " - "%s.\n", fdt_strerror(err)); - break; - } - } -#endif - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - fdt_board_fixup_esdhc(blob, bd); - fdt_board_fixup_qe_uart(blob, bd); - fdt_board_fixup_qe_usb(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c deleted file mode 100644 index 1328a58..0000000 --- a/board/freescale/mpc8569mds/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 Initializations */ - /* - * TLBe 0: 64M write-through, guarded - * Out of reset this entry is only 4K. - * 0xfc000000 32MB NAND FLASH (CS3) - * 0xfe000000 32MB NOR FLASH (CS0) - */ -#ifdef CONFIG_NAND_SPL - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), -#endif - /* - * TLBe 1: 256KB Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256K, 1), - - /* - * TLBe 2: 256M Non-cacheable, guarded - * 0xa00000000 256M PCIe MEM (lower half) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLBe 3: 256M Non-cacheable, guarded - * 0xb00000000 256M PCIe MEM (higher half) - */ - SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000), - (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLBe 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe280_0000 8M PCIe IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig deleted file mode 100644 index 326983d..0000000 --- a/configs/MPC8569MDS_ATM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8569MDS=y -CONFIG_SYS_EXTRA_OPTIONS="ATM" diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig deleted file mode 100644 index 81fb82a..0000000 --- a/configs/MPC8569MDS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8569MDS=y diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h deleted file mode 100644 index 78019b9..0000000 --- a/include/configs/MPC8569MDS.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8569mds board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8569 1 /* MPC8569 specific */ -#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ - -#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI 1 /* Disable PCI/PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controller */ -#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_QE /* Enable QE */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -/* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#ifdef CONFIG_ATM -#define CONFIG_PQ_MDS_PIB -#define CONFIG_PQ_MDS_PIB_ATM -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 - /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 -#define CONFIG_SYS_DDR_TIMING_2 0x002888D0 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 -#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 -#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 -#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 -#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 -#define CONFIG_SYS_DDR_CDR_1 0x80040000 -#define CONFIG_SYS_DDR_CDR_2 0x00000000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_BCSR_BASE 0xf8000000 -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE - -/*Chip select 0 - Flash*/ -#define CONFIG_FLASH_BR_PRELIM 0xfe000801 -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 - -/*Chip select 1 - BCSR*/ -#define CONFIG_SYS_BR1_PRELIM 0xf8000801 -#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 - -/*Chip select 4 - PIB*/ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 - -/*Chip select 5 - PIB*/ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 -#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Chip select 3 - NAND */ -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFC000000 -#else -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#endif - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_NAND_SPL -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser*/ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * I2C2 EEPROM - */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -#define PLPPAR1_I2C_BIT_MASK 0x0000000F -#define PLPPAR1_I2C2_VAL 0x00000000 -#define PLPPAR1_ESDHC_VAL 0x0000000A -#define PLPDIR1_I2C_BIT_MASK 0x0000000F -#define PLPDIR1_I2C2_VAL 0x0000000F -#define PLPDIR1_ESDHC_VAL 0x00000006 -#define PLPPAR1_UART0_BIT_MASK 0x00000fc0 -#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 -#define PLPDIR1_UART0_BIT_MASK 0x00000fc0 -#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 - -/* - * General PCI - * Memory Addresses are mapped 1-1. I/O is mapped from 0 - */ -#define CONFIG_SYS_PCIE1_NAME "Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ - -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -#ifdef CONFIG_QE -/* - * QE UEC ethernet configuration - */ -#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ -#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ - -#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define CONFIG_HAS_ETH0 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#if defined(CONFIG_SYS_UCC_RGMII_MODE) -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#elif defined(CONFIG_SYS_UCC_RMII_MODE) -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_SYS_UCC_RGMII_MODE */ -#endif /* CONFIG_UEC_ETH1 */ - -#define CONFIG_UEC_ETH2 /* GETH2 */ -#define CONFIG_HAS_ETH1 - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#if defined(CONFIG_SYS_UCC_RGMII_MODE) -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#elif defined(CONFIG_SYS_UCC_RMII_MODE) -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 -#endif /* CONFIG_SYS_UCC_RGMII_MODE */ -#endif /* CONFIG_UEC_ETH2 */ - -#define CONFIG_UEC_ETH3 /* GETH3 */ -#define CONFIG_HAS_ETH2 - -#ifdef CONFIG_UEC_ETH3 -#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE -#if defined(CONFIG_SYS_UCC_RGMII_MODE) -#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC3_PHY_ADDR 2 -#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 -#elif defined(CONFIG_SYS_UCC_RMII_MODE) -#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ -#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ -#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 -#endif /* CONFIG_SYS_UCC_RGMII_MODE */ -#endif /* CONFIG_UEC_ETH3 */ - -#define CONFIG_UEC_ETH4 /* GETH4 */ -#define CONFIG_HAS_ETH3 - -#ifdef CONFIG_UEC_ETH4 -#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE -#if defined(CONFIG_SYS_UCC_RGMII_MODE) -#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC4_PHY_ADDR 3 -#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 -#elif defined(CONFIG_SYS_UCC_RMII_MODE) -#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ -#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ -#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 -#endif /* CONFIG_SYS_UCC_RGMII_MODE */ -#endif /* CONFIG_UEC_ETH4 */ - -#undef CONFIG_UEC_ETH6 /* GETH6 */ -#define CONFIG_HAS_ETH5 - -#ifdef CONFIG_UEC_ETH6 -#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ -#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC6_PHY_ADDR 4 -#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII -#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 -#endif /* CONFIG_UEC_ETH6 */ - -#undef CONFIG_UEC_ETH8 /* GETH8 */ -#define CONFIG_HAS_ETH7 - -#ifdef CONFIG_UEC_ETH8 -#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ -#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC8_PHY_ADDR 6 -#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII -#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 -#endif /* CONFIG_UEC_ETH8 */ - -#endif /* CONFIG_QE */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#if defined(CONFIG_SYS_RAMBOOT) -#else -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_MMC 1 - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_HOSTNAME mpc8569mds -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/powerpc/cpu/mpc86xx/Kconfig | 4 - board/sbc8641d/Kconfig | 9 - board/sbc8641d/MAINTAINERS | 6 - board/sbc8641d/Makefile | 10 - board/sbc8641d/README | 28 -- board/sbc8641d/ddr.c | 56 ---- board/sbc8641d/law.c | 40 --- board/sbc8641d/sbc8641d.c | 261 ----------------- configs/sbc8641d_defconfig | 4 - include/configs/sbc8641d.h | 590 --------------------------------------- 10 files changed, 1008 deletions(-) delete mode 100644 board/sbc8641d/Kconfig delete mode 100644 board/sbc8641d/MAINTAINERS delete mode 100644 board/sbc8641d/Makefile delete mode 100644 board/sbc8641d/README delete mode 100644 board/sbc8641d/ddr.c delete mode 100644 board/sbc8641d/law.c delete mode 100644 board/sbc8641d/sbc8641d.c delete mode 100644 configs/sbc8641d_defconfig delete mode 100644 include/configs/sbc8641d.h

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 46d15e2..0dcee70 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -8,9 +8,6 @@ choice prompt "Target select" optional

-config TARGET_SBC8641D - bool "Support sbc8641d" - config TARGET_MPC8641HPCN bool "Support MPC8641HPCN"

@@ -20,7 +17,6 @@ config TARGET_XPEDITE517X endchoice

source "board/freescale/mpc8641hpcn/Kconfig" -source "board/sbc8641d/Kconfig" source "board/xes/xpedite517x/Kconfig"

endmenu diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig deleted file mode 100644 index 8dfc90c..0000000 --- a/board/sbc8641d/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SBC8641D - -config SYS_BOARD - default "sbc8641d" - -config SYS_CONFIG_NAME - default "sbc8641d" - -endif diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS deleted file mode 100644 index a50b541..0000000 --- a/board/sbc8641d/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SBC8641D BOARD -M: Paul Gortmaker paul.gortmaker@windriver.com -S: Maintained -F: board/sbc8641d/ -F: include/configs/sbc8641d.h -F: configs/sbc8641d_defconfig diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile deleted file mode 100644 index a9b2026..0000000 --- a/board/sbc8641d/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sbc8641d.o -obj-y += law.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8641d/README b/board/sbc8641d/README deleted file mode 100644 index a051466..0000000 --- a/board/sbc8641d/README +++ /dev/null @@ -1,28 +0,0 @@ -Wind River SBC8641D reference board -=========================== - -Created 06/14/2007 Joe Hamman -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. ------------------------------ - -1. Building U-Boot ------------------- -The SBC8641D code is known to build using ELDK 4.1. - - $ make sbc8641d_config - Configuring for sbc8641d board... - - $ make - - -2. Switch and Jumper Settings ------------------------------ -All Jumpers & Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. - -3. Known limitations --------------------- -PCI: - The PCI command may hang if no boards are present in either slot. diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c deleted file mode 100644 index b31ea34..0000000 --- a/board/sbc8641d/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c deleted file mode 100644 index c4e736b..0000000 --- a/board/sbc8641d/law.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW (Local Access Window) configuration: - * - * 0x0000_0000 DDR 256M - * 0x1000_0000 DDR2 256M - * 0x8000_0000 PCIE1 MEM 512M - * 0xa000_0000 PCIE2 MEM 512M - * 0xc000_0000 RapidIO 512M - * 0xe200_0000 PCIE1 IO 16M - * 0xe300_0000 PCIE2 IO 16M - * 0xf800_0000 CCSRBAR 2M - * 0xfe00_0000 FLASH (boot bank) 32M - * - */ - - -struct law_entry law_table[] = { -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), -#endif - SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c deleted file mode 100644 index 6bdf1a2..0000000 --- a/board/sbc8641d/sbc8641d.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> - * Copyright 2007 Embedded Specialties, Inc. - * Joe Hamman joe.hamman@embeddedspecialties.com - * - * Copyright 2004 Freescale Semiconductor. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_86xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <libfdt.h> -#include <fdt_support.h> - -long int fixed_sdram (void); - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("Board: Wind River SBC8641D\n"); - - return 0; -} - -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram (); -#endif - - debug (" DDR: "); - return dram_size; -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - puts ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts ("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -long int fixed_sdram (void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile struct ccsr_ddr *ddr = &immap->im_ddr1; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; - ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; - ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; - ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; - ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - - asm ("sync;isync"); - - udelay (500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; - asm ("sync; isync"); - - udelay (500); - ddr = &immap->im_ddr2; - - ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; - ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; - ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; - ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; - ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; - ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; - ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; - ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; - ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; - ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; - ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL; - ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; - - asm ("sync;isync"); - - udelay (500); - - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; - asm ("sync; isync"); - - udelay (500); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif - -void sbc8641d_reset_board (void) -{ - puts ("Resetting board....\n"); -} - -/* - * get_board_sys_clk - * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ - */ - -unsigned long get_board_sys_clk (ulong dummy) -{ - int i; - ulong val = 0; - - i = 5; - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -void board_reset(void) -{ -#ifdef CONFIG_SYS_RESET_ADDRESS - ulong addr = CONFIG_SYS_RESET_ADDRESS; - - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - - /* - * SRR0 has system reset vector, SRR1 has default MSR value - * rfi restores MSR from SRR1 and sets the PC to the SRR0 value - */ - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); -#endif -} diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig deleted file mode 100644 index b67c7c0..0000000 --- a/configs/sbc8641d_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC86xx=y -CONFIG_TARGET_SBC8641D=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h deleted file mode 100644 index 00aab6b..0000000 --- a/include/configs/sbc8641d.h +++ /dev/null @@ -1,590 +0,0 @@ -/* - * Copyright 2007 Wind River Systems <www.windriver.com> - * Copyright 2007 Embedded Specialties, Inc. - * Joe Hamman joe.hamman@embeddedspecialties.com - * - * Copyright 2006 Freescale Semiconductor. - * - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * SBC8641D board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ -#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ -#define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#ifdef RUN_DIAG -#define CONFIG_SYS_DIAG_ADDR 0xff800000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -/* - * virtual address to be used for temporary mappings. There - * should be 128k free at this VA. - */ -#define CONFIG_SYS_SCRATCH_VA 0xe8000000 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI 1 /* Enable PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#define CACHE_LINE_INTERLEAVING 0x20000000 -#define PAGE_INTERLEAVING 0x21000000 -#define BANK_INTERLEAVING 0x22000000 -#define SUPER_BANK_INTERLEAVING 0x23000000 - - -#define CONFIG_ALTIVEC 1 - -/* - * L2CR setup -- make sure this is right for your board! - */ -#define CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ - -#else - /* - * Manually set up DDR1 & DDR2 parameters - */ - - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F - #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 - #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_TIMING_3 0x00000000 - #define CONFIG_SYS_DDR_TIMING_0 0x00220802 - #define CONFIG_SYS_DDR_TIMING_1 0x38377322 - #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 - #define CONFIG_SYS_DDR_CFG_1A 0x43008008 - #define CONFIG_SYS_DDR_CFG_2 0x24401000 - #define CONFIG_SYS_DDR_MODE_1 0x23c00542 - #define CONFIG_SYS_DDR_MODE_2 0x00000000 - #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 - #define CONFIG_SYS_DDR_INTERVAL 0x05080100 - #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 - #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 - #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 - - #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F - #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 - #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 - #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 - #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 - #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 - #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 - #define CONFIG_SYS_DDR2_CFG_2 0x24401000 - #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 - #define CONFIG_SYS_DDR2_MODE_2 0x00000000 - #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 - #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 - #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 - #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 - #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 - - -#endif - -/* #define CONFIG_ID_EEPROM 1 -#define ID_EEPROM_ADDR 0x57 */ - -/* - * The SBC8641D contains 16MB flash space at ff000000. - */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ - -/* Flash */ -#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ - -/* 64KB EEPROM */ -#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ - -/* EPLD - User switches, board id, LEDs */ -#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ - -/* Local bus SDRAM 128MB */ -#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ -#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ - -/* Disk on Chip (DOC) 128MB */ -#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ -#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ - -/* LCD */ -#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ -#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ - -/* Control logic & misc peripherals */ -#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ -#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_PROTECTION - -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#ifndef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* - * Pass open firmware flat tree to kernel - */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * RapidIO MMU - */ -#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS -#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ - -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 -#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS -#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CONFIG_DOS_PARTITION -#undef CONFIG_SCSI_AHCI - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE -#endif - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -/* #define CONFIG_MII 1 */ /* MII PHY management */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" - -#define TSEC1_PHY_ADDR 0x1F -#define TSEC2_PHY_ADDR 0x00 -#define TSEC3_PHY_ADDR 0x01 -#define TSEC4_PHY_ADDR 0x02 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT -#define TSEC4_FLAGS TSEC_GIGABIT - -#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR - */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U - -/* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 512M PCI-Express 1 Memory - * 0xa000_0000 512M PCI-Express 2 Memory - * Changed it for operating from 0xd0000000 - */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M RapidIO Memory - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - -/* - * BAT3 4M Cache-inhibited, guarded - * 0xf800_0000 4M CCSR - */ -#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU -#endif - -/* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 - * Note that this is at 0xe0000000 - */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U - -/* - * BAT5 128K Cacheable, non-guarded - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U - -/* - * BAT6 32M Cache-inhibited, guarded - * 0xfe00_0000 32M FLASH - */ -#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U - -/* Map the last 1M of flash where we're running from reset */ -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY - -#define CONFIG_SYS_DBAT7L 0x00000000 -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 -#define CONFIG_SYS_IBAT7U 0x00000000 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_HAS_ETH0 1 -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 - -#define CONFIG_IPADDR 192.168.0.50 - -#define CONFIG_HOSTNAME sbc8641d -#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=uRamdisk\0" \ - "dtbaddr=400000\0" \ - "dtbfile=sbc8641d.dtb\0" \ - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ - "maxcpus=1" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" - -#define CONFIG_FLASHBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "bootm ffd00000 ffb00000 ffa00000" - -#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND - -#endif /* __CONFIG_H */