[PATCH v6 00/14] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Changes since v6: - Took some patches from Pratyush's series - Removed USE_CLSR flag from S25HL02GT and S25HS02GT - Defined SPINOR_OP_EX4B_CYPRESS and use it - Removed mtd.writesize fixup - Added uniform sector check for multi-die package parts - Remove spansion_quad_enable_volatile() from tiny - Fixed some other minor issues
Changes since v5: - Removed 256Mb and 4Gb parts support - Fixed register offset issue in spansion_quad_enable_volatile() - Added spi_nor_default_ready() and moved existing code into it - Separated spansion_sr_read() to new patch - Renamed spansion_overlaid_erase() to spansion_non_uniform_erase() and changed the implementation to issue the proper erase command based on the address - Added s25hx_t_erase_non_uniform() - Changed mtd.writesize and mtd.flags in s25hx_t_setup() - Fixed page size and erase size issues in s25hx_t_post_bfpt_fixup()
Changes since v4: - Added Read/Write Any Register support - Added the ->ready() hook to support multi-die package parts - Added S25HL02GT/S25HL04GT/S25HS02GT/S25HS04GT support
Changes since v3: - Split into multiple patches
Changes since v2: - Fixed typo in comment for spansion_overlaid_erase() - Fixed expressions for addr and len check in spansion_overlaid_erase() - Added device ID check to make the changes effective for S25 only - Added nor->setup() and fixup hooks based on the following patches https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-7-p.yad... https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-8-p.yad... https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-9-p.yad...
Pratyush Yadav (4): mtd: spi-nor-core: Add a ->setup() hook mtd: spi-nor-core: Move SFDP related declarations to top mtd: spi-nor-core: Introduce flash-specific fixup hooks mtd: spi-nor-core: allow truncated erases
Takahiro Kuwano (10): mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress mtd: spi-nor: Add Cypress manufacturer ID mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t mtd: spi-nor-core: Add support for Read/Write Any Register mtd: spi-nor-core: Add support for volatile QE bit mtd: spi-nor-core: Add the ->ready() hook mtd: spi-nor-core: Read status by Read Any Register mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t
drivers/mtd/spi/spi-nor-core.c | 723 ++++++++++++++++++++++++--------- drivers/mtd/spi/spi-nor-ids.c | 16 + drivers/mtd/spi/spi-nor-tiny.c | 28 +- include/linux/mtd/spi-nor.h | 205 +++++++--- 4 files changed, 700 insertions(+), 272 deletions(-)
From: Pratyush Yadav p.yadav@ti.com
nor->setup() can be used by flashes to configure settings in case they have any peculiarities that can't be easily expressed by the generic spi-nor framework. This includes things like different opcodes, dummy cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav p.yadav@ti.com ---
Taken from Pratyush's series: https://patchwork.ozlabs.org/project/uboot/list/?series=237040&state=*
drivers/mtd/spi/spi-nor-core.c | 84 +++------------ drivers/mtd/spi/spi-nor-tiny.c | 22 ---- include/linux/mtd/spi-nor.h | 192 ++++++++++++++++++++++----------- 3 files changed, 147 insertions(+), 151 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e0efebc355..bda00fa76e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1451,71 +1451,6 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ #endif /* CONFIG_SPI_FLASH_SPANSION */
-struct spi_nor_read_command { - u8 num_mode_clocks; - u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; -}; - -struct spi_nor_pp_command { - u8 opcode; - enum spi_nor_protocol proto; -}; - -enum spi_nor_read_command_index { - SNOR_CMD_READ, - SNOR_CMD_READ_FAST, - SNOR_CMD_READ_1_1_1_DTR, - - /* Dual SPI */ - SNOR_CMD_READ_1_1_2, - SNOR_CMD_READ_1_2_2, - SNOR_CMD_READ_2_2_2, - SNOR_CMD_READ_1_2_2_DTR, - - /* Quad SPI */ - SNOR_CMD_READ_1_1_4, - SNOR_CMD_READ_1_4_4, - SNOR_CMD_READ_4_4_4, - SNOR_CMD_READ_1_4_4_DTR, - - /* Octo SPI */ - SNOR_CMD_READ_1_1_8, - SNOR_CMD_READ_1_8_8, - SNOR_CMD_READ_8_8_8, - SNOR_CMD_READ_1_8_8_DTR, - - SNOR_CMD_READ_MAX -}; - -enum spi_nor_pp_command_index { - SNOR_CMD_PP, - - /* Quad SPI */ - SNOR_CMD_PP_1_1_4, - SNOR_CMD_PP_1_4_4, - SNOR_CMD_PP_4_4_4, - - /* Octo SPI */ - SNOR_CMD_PP_1_1_8, - SNOR_CMD_PP_1_8_8, - SNOR_CMD_PP_8_8_8, - - SNOR_CMD_PP_MAX -}; - -struct spi_nor_flash_parameter { - u64 size; - u32 page_size; - - struct spi_nor_hwcaps hwcaps; - struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; - struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; - - int (*quad_enable)(struct spi_nor *nor); -}; - static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, @@ -2377,9 +2312,10 @@ static int spi_nor_select_erase(struct spi_nor *nor, return 0; }
-static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps) +static int spi_nor_default_setup(struct spi_nor *nor, + const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) { u32 ignored_mask, shared_mask; bool enable_quad_io; @@ -2438,6 +2374,16 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return 0; }
+static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) +{ + if (!nor->setup) + return 0; + + return nor->setup(nor, info, params, hwcaps); +} + static int spi_nor_init(struct spi_nor *nor) { int err; @@ -2504,6 +2450,8 @@ int spi_nor_scan(struct spi_nor *nor) nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg;
+ nor->setup = spi_nor_default_setup; + if (spi->mode & SPI_RX_OCTAL) { hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 07c8c7b82b..5cc2b7d996 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -555,28 +555,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) } #endif /* CONFIG_SPI_FLASH_SPANSION */
-struct spi_nor_read_command { - u8 num_mode_clocks; - u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; -}; - -enum spi_nor_read_command_index { - SNOR_CMD_READ, - SNOR_CMD_READ_FAST, - - /* Quad SPI */ - SNOR_CMD_READ_1_1_4, - - SNOR_CMD_READ_MAX -}; - -struct spi_nor_flash_parameter { - struct spi_nor_hwcaps hwcaps; - struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; -}; - static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c3e38e499e..47a2eced69 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -249,6 +249,134 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), };
+struct spi_nor; + +/** + * struct spi_nor_hwcaps - Structure for describing the hardware capabilies + * supported by the SPI controller (bus master). + * @mask: the bitmask listing all the supported hw capabilies + */ +struct spi_nor_hwcaps { + u32 mask; +}; + +/* + *(Fast) Read capabilities. + * MUST be ordered by priority: the higher bit position, the higher priority. + * As a matter of performances, it is relevant to use Octo SPI protocols first, + * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly + * (Slow) Read. + */ +#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) +#define SNOR_HWCAPS_READ BIT(0) +#define SNOR_HWCAPS_READ_FAST BIT(1) +#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) + +#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) +#define SNOR_HWCAPS_READ_1_1_2 BIT(3) +#define SNOR_HWCAPS_READ_1_2_2 BIT(4) +#define SNOR_HWCAPS_READ_2_2_2 BIT(5) +#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) + +#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) +#define SNOR_HWCAPS_READ_1_1_4 BIT(7) +#define SNOR_HWCAPS_READ_1_4_4 BIT(8) +#define SNOR_HWCAPS_READ_4_4_4 BIT(9) +#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) + +#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) +#define SNOR_HWCAPS_READ_1_1_8 BIT(11) +#define SNOR_HWCAPS_READ_1_8_8 BIT(12) +#define SNOR_HWCAPS_READ_8_8_8 BIT(13) +#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) + +/* + * Page Program capabilities. + * MUST be ordered by priority: the higher bit position, the higher priority. + * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the + * legacy SPI 1-1-1 protocol. + * Note that Dual Page Programs are not supported because there is no existing + * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory + * implements such commands. + */ +#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) +#define SNOR_HWCAPS_PP BIT(16) + +#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) +#define SNOR_HWCAPS_PP_1_1_4 BIT(17) +#define SNOR_HWCAPS_PP_1_4_4 BIT(18) +#define SNOR_HWCAPS_PP_4_4_4 BIT(19) + +#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) +#define SNOR_HWCAPS_PP_1_1_8 BIT(20) +#define SNOR_HWCAPS_PP_1_8_8 BIT(21) +#define SNOR_HWCAPS_PP_8_8_8 BIT(22) + +struct spi_nor_read_command { + u8 num_mode_clocks; + u8 num_wait_states; + u8 opcode; + enum spi_nor_protocol proto; +}; + +struct spi_nor_pp_command { + u8 opcode; + enum spi_nor_protocol proto; +}; + +enum spi_nor_read_command_index { + SNOR_CMD_READ, + SNOR_CMD_READ_FAST, + SNOR_CMD_READ_1_1_1_DTR, + + /* Dual SPI */ + SNOR_CMD_READ_1_1_2, + SNOR_CMD_READ_1_2_2, + SNOR_CMD_READ_2_2_2, + SNOR_CMD_READ_1_2_2_DTR, + + /* Quad SPI */ + SNOR_CMD_READ_1_1_4, + SNOR_CMD_READ_1_4_4, + SNOR_CMD_READ_4_4_4, + SNOR_CMD_READ_1_4_4_DTR, + + /* Octo SPI */ + SNOR_CMD_READ_1_1_8, + SNOR_CMD_READ_1_8_8, + SNOR_CMD_READ_8_8_8, + SNOR_CMD_READ_1_8_8_DTR, + + SNOR_CMD_READ_MAX +}; + +enum spi_nor_pp_command_index { + SNOR_CMD_PP, + + /* Quad SPI */ + SNOR_CMD_PP_1_1_4, + SNOR_CMD_PP_1_4_4, + SNOR_CMD_PP_4_4_4, + + /* Octo SPI */ + SNOR_CMD_PP_1_1_8, + SNOR_CMD_PP_1_8_8, + SNOR_CMD_PP_8_8_8, + + SNOR_CMD_PP_MAX +}; + +struct spi_nor_flash_parameter { + u64 size; + u32 page_size; + + struct spi_nor_hwcaps hwcaps; + struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; + struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; + + int (*quad_enable)(struct spi_nor *nor); +}; + /** * struct flash_info - Forward declaration of a structure used internally by * spi_nor_scan() @@ -330,6 +458,9 @@ struct spi_nor { u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+ int (*setup)(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps); int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); @@ -368,67 +499,6 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor) } #endif /* __UBOOT__ */
-/** - * struct spi_nor_hwcaps - Structure for describing the hardware capabilies - * supported by the SPI controller (bus master). - * @mask: the bitmask listing all the supported hw capabilies - */ -struct spi_nor_hwcaps { - u32 mask; -}; - -/* - *(Fast) Read capabilities. - * MUST be ordered by priority: the higher bit position, the higher priority. - * As a matter of performances, it is relevant to use Octo SPI protocols first, - * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly - * (Slow) Read. - */ -#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) -#define SNOR_HWCAPS_READ BIT(0) -#define SNOR_HWCAPS_READ_FAST BIT(1) -#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) - -#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) -#define SNOR_HWCAPS_READ_1_1_2 BIT(3) -#define SNOR_HWCAPS_READ_1_2_2 BIT(4) -#define SNOR_HWCAPS_READ_2_2_2 BIT(5) -#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) - -#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) -#define SNOR_HWCAPS_READ_1_1_4 BIT(7) -#define SNOR_HWCAPS_READ_1_4_4 BIT(8) -#define SNOR_HWCAPS_READ_4_4_4 BIT(9) -#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) - -#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) -#define SNOR_HWCAPS_READ_1_1_8 BIT(11) -#define SNOR_HWCAPS_READ_1_8_8 BIT(12) -#define SNOR_HWCAPS_READ_8_8_8 BIT(13) -#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) - -/* - * Page Program capabilities. - * MUST be ordered by priority: the higher bit position, the higher priority. - * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the - * legacy SPI 1-1-1 protocol. - * Note that Dual Page Programs are not supported because there is no existing - * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory - * implements such commands. - */ -#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) -#define SNOR_HWCAPS_PP BIT(16) - -#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) -#define SNOR_HWCAPS_PP_1_1_4 BIT(17) -#define SNOR_HWCAPS_PP_1_4_4 BIT(18) -#define SNOR_HWCAPS_PP_4_4_4 BIT(19) - -#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) -#define SNOR_HWCAPS_PP_1_1_8 BIT(20) -#define SNOR_HWCAPS_PP_1_8_8 BIT(21) -#define SNOR_HWCAPS_PP_8_8_8 BIT(22) - /** * spi_nor_scan() - scan the SPI NOR * @nor: the spi_nor structure
From: Pratyush Yadav p.yadav@ti.com
These structures will be used in a later commit inside another structure definition. Also take the declarations out of the ifdef since they won't affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav p.yadav@ti.com ---
Taken from Pratyush's series: https://patchwork.ozlabs.org/project/uboot/list/?series=237040&state=*
drivers/mtd/spi/spi-nor-core.c | 224 ++++++++++++++++----------------- 1 file changed, 112 insertions(+), 112 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index bda00fa76e..eb58e9ea09 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -40,6 +40,118 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+struct sfdp_parameter_header { + u8 id_lsb; + u8 minor; + u8 major; + u8 length; /* in double words */ + u8 parameter_table_pointer[3]; /* byte address */ + u8 id_msb; +}; + +#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) +#define SFDP_PARAM_HEADER_PTP(p) \ + (((p)->parameter_table_pointer[2] << 16) | \ + ((p)->parameter_table_pointer[1] << 8) | \ + ((p)->parameter_table_pointer[0] << 0)) + +#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ +#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ +#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ + +#define SFDP_SIGNATURE 0x50444653U +#define SFDP_JESD216_MAJOR 1 +#define SFDP_JESD216_MINOR 0 +#define SFDP_JESD216A_MINOR 5 +#define SFDP_JESD216B_MINOR 6 + +struct sfdp_header { + u32 signature; /* Ox50444653U <=> "SFDP" */ + u8 minor; + u8 major; + u8 nph; /* 0-base number of parameter headers */ + u8 unused; + + /* Basic Flash Parameter Table. */ + struct sfdp_parameter_header bfpt_header; +}; + +/* Basic Flash Parameter Table */ + +/* + * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. + * They are indexed from 1 but C arrays are indexed from 0. + */ +#define BFPT_DWORD(i) ((i) - 1) +#define BFPT_DWORD_MAX 16 + +/* The first version of JESB216 defined only 9 DWORDs. */ +#define BFPT_DWORD_MAX_JESD216 9 + +/* 1st DWORD. */ +#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) +#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) +#define BFPT_DWORD1_DTR BIT(19) +#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) +#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) +#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) + +/* 5th DWORD. */ +#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) +#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) + +/* 11th DWORD. */ +#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 +#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) + +/* 15th DWORD. */ + +/* + * (from JESD216 rev B) + * Quad Enable Requirements (QER): + * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 + * reads based on instruction. DQ3/HOLD# functions are hold during + * instruction phase. + * - 001b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * Writing only one byte to the status register has the side-effect of + * clearing status register 2, including the QE bit. The 100b code is + * used if writing one byte to the status register does not modify + * status register 2. + * - 010b: QE is bit 6 of status register 1. It is set via Write Status with + * one data byte where bit 6 is one. + * [...] + * - 011b: QE is bit 7 of status register 2. It is set via Write status + * register 2 instruction 3Eh with one data byte where bit 7 is one. + * [...] + * The status register 2 is read using instruction 3Fh. + * - 100b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * In contrast to the 001b code, writing one byte to the status + * register does not modify status register 2. + * - 101b: QE is bit 1 of status register 2. Status register 1 is read using + * Read Status instruction 05h. Status register2 is read using + * instruction 35h. QE is set via Writ Status instruction 01h with + * two data bytes where bit 1 of the second byte is one. + * [...] + */ +#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) +#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ +#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) +#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ +#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ + +struct sfdp_bfpt { + u32 dwords[BFPT_DWORD_MAX]; +}; + static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { @@ -1528,118 +1640,6 @@ read_err: return ret; }
-struct sfdp_parameter_header { - u8 id_lsb; - u8 minor; - u8 major; - u8 length; /* in double words */ - u8 parameter_table_pointer[3]; /* byte address */ - u8 id_msb; -}; - -#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) -#define SFDP_PARAM_HEADER_PTP(p) \ - (((p)->parameter_table_pointer[2] << 16) | \ - ((p)->parameter_table_pointer[1] << 8) | \ - ((p)->parameter_table_pointer[0] << 0)) - -#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ -#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ -#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ - -#define SFDP_SIGNATURE 0x50444653U -#define SFDP_JESD216_MAJOR 1 -#define SFDP_JESD216_MINOR 0 -#define SFDP_JESD216A_MINOR 5 -#define SFDP_JESD216B_MINOR 6 - -struct sfdp_header { - u32 signature; /* Ox50444653U <=> "SFDP" */ - u8 minor; - u8 major; - u8 nph; /* 0-base number of parameter headers */ - u8 unused; - - /* Basic Flash Parameter Table. */ - struct sfdp_parameter_header bfpt_header; -}; - -/* Basic Flash Parameter Table */ - -/* - * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. - * They are indexed from 1 but C arrays are indexed from 0. - */ -#define BFPT_DWORD(i) ((i) - 1) -#define BFPT_DWORD_MAX 16 - -/* The first version of JESB216 defined only 9 DWORDs. */ -#define BFPT_DWORD_MAX_JESD216 9 - -/* 1st DWORD. */ -#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) -#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) -#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) -#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) -#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) -#define BFPT_DWORD1_DTR BIT(19) -#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) -#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) -#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) - -/* 5th DWORD. */ -#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) -#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) - -/* 11th DWORD. */ -#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 -#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) - -/* 15th DWORD. */ - -/* - * (from JESD216 rev B) - * Quad Enable Requirements (QER): - * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 - * reads based on instruction. DQ3/HOLD# functions are hold during - * instruction phase. - * - 001b: QE is bit 1 of status register 2. It is set via Write Status with - * two data bytes where bit 1 of the second byte is one. - * [...] - * Writing only one byte to the status register has the side-effect of - * clearing status register 2, including the QE bit. The 100b code is - * used if writing one byte to the status register does not modify - * status register 2. - * - 010b: QE is bit 6 of status register 1. It is set via Write Status with - * one data byte where bit 6 is one. - * [...] - * - 011b: QE is bit 7 of status register 2. It is set via Write status - * register 2 instruction 3Eh with one data byte where bit 7 is one. - * [...] - * The status register 2 is read using instruction 3Fh. - * - 100b: QE is bit 1 of status register 2. It is set via Write Status with - * two data bytes where bit 1 of the second byte is one. - * [...] - * In contrast to the 001b code, writing one byte to the status - * register does not modify status register 2. - * - 101b: QE is bit 1 of status register 2. Status register 1 is read using - * Read Status instruction 05h. Status register2 is read using - * instruction 35h. QE is set via Writ Status instruction 01h with - * two data bytes where bit 1 of the second byte is one. - * [...] - */ -#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) -#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ -#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) -#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ -#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) -#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) -#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ - -struct sfdp_bfpt { - u32 dwords[BFPT_DWORD_MAX]; -}; - /* Fast Read settings. */
static void
From: Pratyush Yadav p.yadav@ti.com
Sometimes the information in a flash's SFDP tables is wrong. Sometimes some information just can't be expressed in the SFDP table. So, introduce the fixup hooks to allow tailoring settings for a specific flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These allow tweaking the flash settings at different point in the probe sequence. Since the hooks reside in nor->info, set that value just before the call to spi_nor_init_params().
The hooks and at what points they are executed mimics Linux's spi-nor framework. One major difference is that Linux puts the struct spi_nor_fixups in nor->info. This is not possible in U-Boot because the spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c. Since spi-nor-tiny shouldn't have those fixup hooks populated, add a separate function that lets flashes populate their fixup hooks.
Signed-off-by: Pratyush Yadav p.yadav@ti.com ---
Taken from Pratyush's series: https://patchwork.ozlabs.org/project/uboot/list/?series=237040&state=*
drivers/mtd/spi/spi-nor-core.c | 78 ++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 2 + 2 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index eb58e9ea09..9f31e6b92a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -152,6 +152,31 @@ struct sfdp_bfpt { u32 dwords[BFPT_DWORD_MAX]; };
+/** + * struct spi_nor_fixups - SPI NOR fixup hooks + * @default_init: called after default flash parameters init. Used to tweak + * flash parameters when information provided by the flash_info + * table is incomplete or wrong. + * @post_bfpt: called after the BFPT table has been parsed + * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs + * that do not support RDSFDP). Typically used to tweak various + * parameters that could not be extracted by other means (i.e. + * when information provided by the SFDP/flash_info tables are + * incomplete or wrong). + * + * Those hooks can be used to tweak the SPI NOR configuration when the SFDP + * table is broken or not available. + */ +struct spi_nor_fixups { + void (*default_init)(struct spi_nor *nor); + int (*post_bfpt)(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params); + void (*post_sfdp)(struct spi_nor *nor, + struct spi_nor_flash_parameter *params); +}; + static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { @@ -1751,6 +1776,18 @@ static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
+static int +spi_nor_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + if (nor->fixups && nor->fixups->post_bfpt) + return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params); + + return 0; +} + /** * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. * @nor: pointer to a 'struct spi_nor' @@ -1889,7 +1926,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
/* Stop here if not JESD216 rev A or later. */ if (bfpt_header->length < BFPT_DWORD_MAX) - return 0; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, + params);
/* Page size: this field specifies 'N' so the page size = 2^N bytes. */ params->page_size = bfpt.dwords[BFPT_DWORD(11)]; @@ -1922,7 +1960,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EINVAL; }
- return 0; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); }
/** @@ -2085,6 +2123,29 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, } #endif /* SPI_FLASH_SFDP_SUPPORT */
+/** + * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings + * after SFDP has been parsed (is also called for SPI NORs that do not + * support RDSFDP). + * @nor: pointer to a 'struct spi_nor' + * + * Typically used to tweak various parameters that could not be extracted by + * other means (i.e. when information provided by the SFDP/flash_info tables + * are incomplete or wrong). + */ +static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + if (nor->fixups && nor->fixups->post_sfdp) + nor->fixups->post_sfdp(nor, params); +} + +static void spi_nor_default_init_fixups(struct spi_nor *nor) +{ + if (nor->fixups && nor->fixups->default_init) + nor->fixups->default_init(nor); +} + static int spi_nor_init_params(struct spi_nor *nor, const struct flash_info *info, struct spi_nor_flash_parameter *params) @@ -2164,6 +2225,8 @@ static int spi_nor_init_params(struct spi_nor *nor, } }
+ spi_nor_default_init_fixups(nor); + /* Override the parameters with data read from SFDP tables. */ nor->addr_width = 0; nor->mtd.erasesize = 0; @@ -2180,6 +2243,8 @@ static int spi_nor_init_params(struct spi_nor *nor, } }
+ spi_nor_post_sfdp_fixups(nor, params); + return 0; }
@@ -2428,6 +2493,10 @@ static int spi_nor_init(struct spi_nor *nor) return 0; }
+void spi_nor_set_fixups(struct spi_nor *nor) +{ +} + int spi_nor_scan(struct spi_nor *nor) { struct spi_nor_flash_parameter params; @@ -2476,6 +2545,10 @@ int spi_nor_scan(struct spi_nor *nor) info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) return -ENOENT; + nor->info = info; + + spi_nor_set_fixups(nor); + /* Parse the Serial Flash Discoverable Parameters table. */ ret = spi_nor_init_params(nor, info, ¶ms); if (ret) @@ -2575,7 +2648,6 @@ int spi_nor_scan(struct spi_nor *nor) }
/* Send all the required SPI flash commands to initialize device */ - nor->info = info; ret = spi_nor_init(nor); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 47a2eced69..b2e9e0895b 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -416,6 +416,7 @@ struct spi_flash { * @write_proto: the SPI protocol for write operations * @reg_proto the SPI protocol for read_reg/write_reg/erase operations * @cmd_buf: used by the write_reg + * @fixups: flash-specific fixup hooks. * @prepare: [OPTIONAL] do some preparations for the * read/write/erase/lock/unlock operations * @unprepare: [OPTIONAL] do some post work after the @@ -457,6 +458,7 @@ struct spi_nor { bool sst_write_second; u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + struct spi_nor_fixups *fixups;
int (*setup)(struct spi_nor *nor, const struct flash_info *info, const struct spi_nor_flash_parameter *params,
From: Pratyush Yadav p.yadav@ti.com
On devices with non-uniform sector sizes like Spansion S25 or S28 family of flashes the sector under erase does not necessarily have to be mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then 256 KiB sectors till the end.
Let the flash-specific erase functions erase less than the requested length in case of the 4 or 128 KiB sectors and report the number of bytes erased back to the calling function.
Signed-off-by: Pratyush Yadav p.yadav@ti.com [Takahiro.Kuwano@infineon.com: base on master to exclude Octal/DTR related changes] Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com ---
Pratyush's original patch [0] depends on the other changes in his series. Once his patch is accepted, I will rebase this series.
[0] https://patchwork.ozlabs.org/project/uboot/patch/20210401193133.18129-26-p.y...
drivers/mtd/spi/spi-nor-core.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9f31e6b92a..829ad36903 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -660,7 +660,8 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) #endif
/* - * Initiate the erasure of a single sector + * Initiate the erasure of a single sector. Returns the number of bytes erased + * on success, a negative error code on error. */ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) { @@ -669,6 +670,7 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + int ret;
if (nor->erase) return nor->erase(nor, addr); @@ -677,7 +679,11 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) * Default implementation, if driver doesn't have a specialized HW * control */ - return spi_mem_exec_op(nor->spi, &op); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return nor->mtd.erasesize; }
/* @@ -713,11 +719,11 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) write_enable(nor);
ret = spi_nor_erase_sector(nor, addr); - if (ret) + if (ret < 0) goto erase_err;
- addr += mtd->erasesize; - len -= mtd->erasesize; + addr += ret; + len -= ret;
ret = spi_nor_wait_till_ready(nor); if (ret)
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or bottom, depending on the device configuration, while U-Boot supports uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors, non-overlaid portion of normal sector, and remaining normal sectors, by selecting correct erase command and size based on the address to erase and size of overlaid portion in parameters. Since different Spansion flashes can use different opcode for erasing the 4K sectors, the opcode must be passed in as a parameter based on the flash being used.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Signed-off-by: Pratyush Yadav p.yadav@ti.com [p.yadav@ti.com: Refactor the function to be compatible with nor->erase, make 4K opcode customizable, call spi_nor_setup_op() before executing the op.] [Takahiro.Kuwano@infineon.com: Remove spi_nor_setup_op() and initialize op.cmd.buswidth and op.addr.buswidth by 1] ---
Once Pratyush's patch [0] is accepted, I will rebase this series.
[0] https://patchwork.ozlabs.org/project/uboot/patch/20210401193133.18129-27-p.y...
drivers/mtd/spi/spi-nor-core.c | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 829ad36903..1b84e389ad 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -739,6 +739,65 @@ erase_err: return ret; }
+#ifdef CONFIG_SPI_FLASH_SPANSION +/** + * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress + * chips + * @nor: pointer to a 'struct spi_nor' + * @addr: address of the sector to erase + * @opcode_4k: opcode for 4K sector erase + * @ovlsz_top: size of overlaid portion at the top address + * @ovlsz_btm: size of overlaid portion at the bottom address + * + * Erase an address range on the nor chip that can contain 4KB sectors overlaid + * on top and/or bottom. The appropriate erase opcode and size are chosen by + * address to erase and size of overlaid portion. + * + * Return: number of bytes erased on success, -errno otherwise. + */ +static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr, + u8 opcode_4k, u32 ovlsz_top, + u32 ovlsz_btm) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + struct mtd_info *mtd = &nor->mtd; + u32 erasesize; + int ret; + + /* 4KB sectors */ + if (op.addr.val < ovlsz_btm || + op.addr.val >= mtd->size - ovlsz_top) { + op.cmd.opcode = opcode_4k; + erasesize = SZ_4K; + + /* Non-overlaid portion in the normal sector at the bottom */ + } else if (op.addr.val == ovlsz_btm) { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize - ovlsz_btm; + + /* Non-overlaid portion in the normal sector at the top */ + } else if (op.addr.val == mtd->size - mtd->erasesize) { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize - ovlsz_top; + + /* Normal sectors */ + } else { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize; + } + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return erasesize; +} +#endif + #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* Write status register and ensure bits in mask match written values */ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
This patch adds Cypress manufacturer ID (34h) definition.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- include/linux/mtd/spi-nor.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b2e9e0895b..47ce8f5f25 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -27,6 +27,7 @@ #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ +#define SNOR_MFR_CYPRESS 0x34
/* * Note on opcode nomenclature: some opcodes have a format like
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable sector architecture. By default, the 512Mb and 1Gb, single-die package parts are configured to non-uniform that 4KB sectors overlaid on bottom address. To support this, an erase hook makes overlaid sectors appear as uniform sectors. The 2Gb, dual-die package parts are configured to uniform by default.
Tested on Xilinx Zynq-7000 FPGA board.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v6: - Remove USE_CLSR flag from S25HL02GT and S25HS02GT - Remove comment block and update commit description
Changes in v5: - Remove 256Mb and 4Gb parts
drivers/mtd/spi/spi-nor-ids.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954..d6f1b7d8a3 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -222,6 +222,22 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
Some of Spansion/Cypress chips support Read/Write Any Register commands. These commands are mainly used to write volatile registers and access to the registers in second and subsequent die for multi-die package parts.
The Read Any Register instruction (65h) is followed by register address and dummy cycles, then the selected register byte is returned.
The Write Any Register instruction (71h) is followed by register address and register byte to write.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v6: - No change
Changes in v5: - Remove unused defines from spi-nor.h
drivers/mtd/spi/spi-nor-core.c | 25 +++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 27 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1b84e389ad..36c1756576 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -212,6 +212,31 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) return spi_nor_read_write_reg(nor, &op, buf); }
+#ifdef CONFIG_SPI_FLASH_SPANSION +static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, + u8 *val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_DUMMY(dummy / 8, 1), + SPI_MEM_OP_DATA_IN(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, val); +} + +static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, &val); +} +#endif + static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 47ce8f5f25..a9b389f2af 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -121,6 +121,8 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_RDAR 0x65 /* Read any register */ +#define SPINOR_OP_WRAR 0x71 /* Write any register */
/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v6: - No change
Changes in v5: - Fix register address calculation, 'base | offset' -> 'base + offset'
drivers/mtd/spi/spi-nor-core.c | 53 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 54 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 36c1756576..d731df30a7 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1644,6 +1644,59 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) return 0; }
+/** + * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register. + * @nor: pointer to a 'struct spi_nor' + * @addr_base: base address of register (can be >0 in multi-die parts) + * @dummy: number of dummy cycles for register read + * + * It is recommended to update volatile registers in the field application due + * to a risk of the non-volatile registers corruption by power interrupt. This + * function sets Quad Enable bit in CFR1 volatile. + * + * Return: 0 on success, -errno otherwise. + */ +static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base, + u8 dummy) +{ + u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V; + + u8 cr; + int ret; + + /* Check current Quad Enable bit value. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret < 0) { + dev_dbg(nor->dev, + "error while reading configuration register\n"); + return -EINVAL; + } + + if (cr & CR_QUAD_EN_SPAN) + return 0; + + cr |= CR_QUAD_EN_SPAN; + + write_enable(nor); + + ret = spansion_write_any_reg(nor, addr, cr); + + if (ret < 0) { + dev_dbg(nor->dev, + "error while writing configuration register\n"); + return -EINVAL; + } + + /* Read back and check it. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret || !(cr & CR_QUAD_EN_SPAN)) { + dev_dbg(nor->dev, "Spansion Quad bit not set\n"); + return -EINVAL; + } + + return 0; +} + #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) /** * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index a9b389f2af..de4472da5c 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_CFR1V 0x00800002
/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
For dual/quad die package devices from Spansion/Cypress, the device's status needs to be checked by reading status registers in all dies, by using Read Any Register command. To support this, a Flash specific hook that can overwrite the legacy status check is needed.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v6: - Rebase and fix commit description
Changes in v5: - Move spansion_sr_ready() to different patch - Move original code in spi_nor_ready() to newly created spi_nor_default_ready()
drivers/mtd/spi/spi-nor-core.c | 10 +++++++++- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d731df30a7..55e17aace3 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -567,7 +567,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) return fsr & FSR_READY; }
-static int spi_nor_ready(struct spi_nor *nor) +static int spi_nor_default_ready(struct spi_nor *nor) { int sr, fsr;
@@ -580,6 +580,14 @@ static int spi_nor_ready(struct spi_nor *nor) return sr && fsr; }
+static int spi_nor_ready(struct spi_nor *nor) +{ + if (nor->ready) + return nor->ready(nor); + + return spi_nor_default_ready(nor); +} + /* * Service routine to read status register until ready, or timeout occurs. * Returns non-zero if error. diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index de4472da5c..2236e36e28 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -437,6 +437,7 @@ struct spi_flash { * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode + * @ready: [FLASH-SPECIFIC] check if the flash is ready * @priv: the private data */ struct spi_nor { @@ -482,6 +483,7 @@ struct spi_nor { int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*quad_enable)(struct spi_nor *nor); + int (*ready)(struct spi_nor *nor);
void *priv; /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The spansion_sr_ready() reads status register 1 by Read Any Register commnad. This function is called from Flash specific hook with die address and dummy cycles to support multi-die package parts from Spansion/Cypress.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v6: - No change
Changes in v5: - New in v5, separated from another patch --- drivers/mtd/spi/spi-nor-core.c | 29 +++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 30 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 55e17aace3..296310eb25 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -523,6 +523,35 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, } }
+#ifdef CONFIG_SPI_FLASH_SPANSION +/* + * Read status register 1 by using Read Any Register command to support multi + * die package parts. + */ +static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy) +{ + u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V; + u8 sr; + int ret; + + ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr); + if (ret < 0) + return ret; + + if (sr & (SR_E_ERR | SR_P_ERR)) { + if (sr & SR_E_ERR) + dev_dbg(nor->dev, "Erase Error occurred\n"); + else + dev_dbg(nor->dev, "Programming Error occurred\n"); + + nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); + return -EIO; + } + + return !(sr & SR_WIP); +} +#endif + static int spi_nor_sr_ready(struct spi_nor *nor) { int sr = read_sr(nor); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2236e36e28..8a187eaf26 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002
/* Used for Micron flashes only. */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.
Cypress chips support B8h to disable 4-byte addressing mode instead of SPINOR_OP_EX4B(E9h).
This patch defines new opcode and updates set_4byte() to support enable/disable 4-byte addressing mode for Cypress chips.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v6: - Define SPINOR_OP_EX4B_CYPRESS and use it
drivers/mtd/spi/spi-nor-core.c | 3 +++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 4 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 296310eb25..5e91338ced 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -516,6 +516,9 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, }
return status; + case SNOR_MFR_CYPRESS: + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS; + return nor->write_reg(nor, cmd, NULL, 0); default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 8a187eaf26..0b295c3eec 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -121,6 +121,7 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts.
The nor->quad_enable() sets the volatile QE bit on each die.
The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed.
The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v6: - Remove mtd.writesize fixup - Check if uniform sector is selected in multi-die package parts - Fix some other minor issues
Changes in v5: - Add s25hx_t_erase_non_uniform() - Change mtd.writesize and mtd.flags in s25hx_t_setup() - Fix page size and erase size issues in s25hx_t_post_bfpt_fixup() --- drivers/mtd/spi/spi-nor-core.c | 142 +++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 3 + 2 files changed, 145 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5e91338ced..2ee1201f6b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2676,8 +2676,150 @@ static int spi_nor_init(struct spi_nor *nor) return 0; }
+#ifdef CONFIG_SPI_FLASH_SPANSION +static int s25hx_t_mdp_ready(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_sr_ready(nor, addr, 0); + if (!ret) + return ret; + } + + return 1; +} + +static int s25hx_t_quad_enable(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_quad_enable_volatile(nor, addr, 0); + if (ret) + return ret; + } + + return 0; +} + +static ssize_t s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 32 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, + SZ_128K); +} + +static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) +{ + int ret; + u8 cfr3v; + +#ifdef CONFIG_SPI_FLASH_BAR + return -ENOTSUPP; /* Bank Address Register is not supported */ +#endif + /* + * Read CFR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25hx_t_erase_non_uniform; + + /* + * For the multi-die package parts, the ready() hook is needed to check + * all dies' status via read any register. + */ + if (nor->mtd.size > SZ_128M) + nor->ready = s25hx_t_mdp_ready; + + return spi_nor_default_setup(nor, info, params, hwcaps); +} + +static void s25hx_t_default_init(struct spi_nor *nor) +{ + nor->setup = s25hx_t_setup; +} + +static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + int ret; + u32 addr; + u8 cfr3v; + + /* erase size in case it is set to 4K from BFPT */ + nor->erase_opcode = SPINOR_OP_SE_4B; + nor->mtd.erasesize = nor->info->sector_size; + + ret = set_4byte(nor, nor->info, 1); + if (ret) + return ret; + nor->addr_width = 4; + + /* + * The page_size is set to 512B from BFPT, but it actually depends on + * the configuration register. Look up the CFR3V and determine the + * page_size. For multi-die package parts, use 512B only when the all + * dies are configured to 512B buffer. + */ + for (addr = 0; addr < params->size; addr += SZ_128M) { + ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V, + 0, &cfr3v); + if (ret) + return ret; + + if (!(cfr3v & CFR3V_PGMBUF)) { + params->page_size = 256; + return 0; + } + } + params->page_size = 512; + + return 0; +} + +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_FAST_4B (0Ch) requires mode cycles*/ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25hx_t_quad_enable; +} + +static struct spi_nor_fixups s25hx_t_fixups = { + .default_init = s25hx_t_default_init, + .post_bfpt = s25hx_t_post_bfpt_fixup, + .post_sfdp = s25hx_t_post_sfdp_fixup, +}; +#endif + void spi_nor_set_fixups(struct spi_nor *nor) { +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) { + switch (nor->info->id[1]) { + case 0x2a: /* S25HL (QSPI, 3.3V) */ + case 0x2b: /* S25HS (QSPI, 1.8V) */ + nor->fixups = &s25hx_t_fixups; + break; + + default: + break; + } + } +#endif }
int spi_nor_scan(struct spi_nor *nor) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 0b295c3eec..7bc946064a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -126,6 +126,9 @@ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002 +#define SPINOR_REG_ADDR_CFR3V 0x00800004 +#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ +#define CFR3V_PGMBUF BIT(4) /* Program buffer size */
/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.
Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v6: - Remove spansion_quad_enable_volatile() per comment in https://patchwork.ozlabs.org/project/uboot/patch/a5c3cf1353d9a621379e2fcfefc...
Changes in v5: - Add a comment about Flash models and respective IDs
drivers/mtd/spi/spi-nor-tiny.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 5cc2b7d996..aa2df75c60 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -583,6 +583,12 @@ static int spi_nor_init_params(struct spi_nor *nor, spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1); +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(info) == SNOR_MFR_CYPRESS && + (info->id[1] == 0x2a || info->id[1] == 0x2b)) + /* 0x2a: S25HL (QSPI, 3.3V), 0x2b: S25HS (QSPI, 1.8V) */ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; +#endif }
if (info->flags & SPI_NOR_QUAD_READ) {
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Jagan.
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Best Regards, Takahiro
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
Jagan.
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
[0] https://patchwork.ozlabs.org/project/uboot/list/?series=237040&state=*
Best Regards, Takahiro
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano tkuw584924@gmail.com wrote:
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
nor->erase seems improper, please have a look at the issue here. https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
Jagan.
On 26/04/21 06:04PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano tkuw584924@gmail.com wrote:
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote:
From: Takahiro Kuwano Takahiro.Kuwano@infineon.com
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...
Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
nor->erase seems improper, please have a look at the issue here. https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
I get a 404 on this link. Can you elaborate on what is wrong with nor->erase?
On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav p.yadav@ti.com wrote:
On 26/04/21 06:04PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano tkuw584924@gmail.com wrote:
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote:
On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote: > > From: Takahiro Kuwano Takahiro.Kuwano@infineon.com > > The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. > > The summary datasheets can be found in the following links. > https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) > https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) > > The full version can be found in the following links (registration > required). > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M... > > Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
nor->erase seems improper, please have a look at the issue here. https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
I get a 404 on this link. Can you elaborate on what is wrong with nor->erase?
Building current source for 1 boards (0 threads, 40 jobs per thread) sandbox: w+ sandbox_spl + nor->erase = s25hx_t_erase_non_uniform; + ^ w+drivers/mtd/spi/spi-nor-core.c: In function 's25hx_t_setup': w+drivers/mtd/spi/spi-nor-core.c:2733:14: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] 0 1 0 /1 sandbox_spl
Can you able to open this link at least?
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/7306
Jagan.
On 26/04/21 06:25PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav p.yadav@ti.com wrote:
On 26/04/21 06:04PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano tkuw584924@gmail.com wrote:
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote:
On 4/19/2021 4:13 PM, Jagan Teki wrote: > On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote: >> >> From: Takahiro Kuwano Takahiro.Kuwano@infineon.com >> >> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >> >> The summary datasheets can be found in the following links. >> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) >> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) >> >> The full version can be found in the following links (registration >> required). >> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... >> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M... >> >> Tested on Xilinx Zynq-7000 FPGA board. > > Any details about footprint statistics? > Please see arm-none-eabi-size output below.
BEFORE patching: text data bss dec hex filename 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o
AFTER patching: text data bss dec hex filename 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o
arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
nor->erase seems improper, please have a look at the issue here. https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
I get a 404 on this link. Can you elaborate on what is wrong with nor->erase?
Building current source for 1 boards (0 threads, 40 jobs per thread) sandbox: w+ sandbox_spl
- nor->erase = s25hx_t_erase_non_uniform;
- ^
w+drivers/mtd/spi/spi-nor-core.c: In function 's25hx_t_setup': w+drivers/mtd/spi/spi-nor-core.c:2733:14: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] 0 1 0 /1 sandbox_spl
Sandbox defines ssize_t as long and ARM defines it as int and so on. nor->erase() returns int, so this would build fine on 32-bit platforms but not on 64-bit ones. Changing the return type of s25hx_t_setup() to int should fix this problem.
Can you able to open this link at least?
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/7306
Yes.
On 4/26/2021 10:19 PM, Pratyush Yadav wrote:
On 26/04/21 06:25PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav p.yadav@ti.com wrote:
On 26/04/21 06:04PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano tkuw584924@gmail.com wrote:
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano tkuw584924@gmail.com wrote: > > On 4/19/2021 4:13 PM, Jagan Teki wrote: >> On Wed, Apr 7, 2021 at 9:01 AM tkuw584924@gmail.com wrote: >>> >>> From: Takahiro Kuwano Takahiro.Kuwano@infineon.com >>> >>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >>> >>> The summary datasheets can be found in the following links. >>> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) >>> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) >>> >>> The full version can be found in the following links (registration >>> required). >>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... >>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M... >>> >>> Tested on Xilinx Zynq-7000 FPGA board. >> >> Any details about footprint statistics? >> > Please see arm-none-eabi-size output below. > > BEFORE patching: > text data bss dec hex filename > 6353 0 0 6353 18d1 drivers/mtd/spi/spi-nor-core.o > 922 0 0 922 39a drivers/mtd/spi/spi-nor-ids.o > 1879 0 0 1879 757 spl/drivers/mtd/spi/spi-nor-tiny.o > > AFTER patching: > text data bss dec hex filename > 7705 12 0 7717 1e25 drivers/mtd/spi/spi-nor-core.o > 1150 0 0 1150 47e drivers/mtd/spi/spi-nor-ids.o > 1919 0 0 1919 77f spl/drivers/mtd/spi/spi-nor-tiny.o > > arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
Does this series depend on any other patches or Octal DTR?
No. This series is for Quad SPI parts and independent from any other patches. The #1, #2, and #3 patches in this series come from Pratyush's series [0] that adds Octal DTR support. However, those three patches introduce generic hooks and do not contain any specific changes for Octal DTR.
nor->erase seems improper, please have a look at the issue here. https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
I get a 404 on this link. Can you elaborate on what is wrong with nor->erase?
Building current source for 1 boards (0 threads, 40 jobs per thread) sandbox: w+ sandbox_spl
- nor->erase = s25hx_t_erase_non_uniform;
- ^
w+drivers/mtd/spi/spi-nor-core.c: In function 's25hx_t_setup': w+drivers/mtd/spi/spi-nor-core.c:2733:14: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] 0 1 0 /1 sandbox_spl
Sandbox defines ssize_t as long and ARM defines it as int and so on. nor->erase() returns int, so this would build fine on 32-bit platforms but not on 64-bit ones. Changing the return type of s25hx_t_setup() to int should fix this problem.
I will fix it. Thank you for working on this.
Can you able to open this link at least?
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/7306
Yes.
Best Regards, Takahiro
participants (4)
-
Jagan Teki -
Pratyush Yadav -
Takahiro Kuwano -
tkuw584924＠gmail.com