[U-Boot] powerpc/mpc85xx: Increase image size
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
Please comment.
Regards,
York
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
-Scott
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
York
On 10/11/2013 11:56 AM, York Sun wrote:
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
Scott,
Are SPL and TPL boot methods immune from the size issue here?
York
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
On 10/11/2013 11:56 AM, York Sun wrote:
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
Scott,
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
-Scott
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
On 10/11/2013 11:56 AM, York Sun wrote:
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
Scott,
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
York
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
On 10/11/2013 11:56 AM, York Sun wrote:
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote:
Scott, et al.
I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well.
It is per board configuration. But it may be better if we keep them consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
Scott,
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
-Scott
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
On 10/11/2013 11:56 AM, York Sun wrote:
On 10/11/2013 11:39 AM, Scott Wood wrote:
On Fri, 2013-10-11 at 11:29 -0700, York Sun wrote: > Scott, et al. > > I'd like to start the discussion to increase u-boot image size for some > mpc85xx targets. As we all know the reset vector is at the very end and > linking process start from the top. This gives us no good choice but to > use fixed image size. While we have more and more features, the size > increases inevitably. It's time to adjust the arbitrary size. We are now > using 512KB. Shall we go with 768KB, or even 1MB?
768K would affect fewer existing partition maps (many of which leave 1M for U-Boot and environment combined), but 1M might be better for new boards. And of course it would be nice if someone could spare some time to try to slim things down (finer-grained compile-time config, speed/size tradeoffs, etc).
> For the first step, I think we don't have to increase size for all > targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those > are the most recent used. There are other targets which don't use NOR > flash boot method. They should be considered as well. > > It is per board configuration. But it may be better if we keep them > consistent.
I don't think it's worth trying to keep them consistent. Leave alone old boards that are not pushing the limit, and where testing and user education would be a hassle, and let newer boards where more features are wanted not be constrained by the past.
I did a quick search for eff80000. Only these boards have it
include/configs/B4860QDS.h include/configs/C29XPCIE.h include/configs/corenet_ds.h include/configs/HWW1U1A.h include/configs/MPC8536DS.h include/configs/MPC8572DS.h include/configs/P1010RDB.h include/configs/P1022DS.h include/configs/P1023RDB.h include/configs/P1023RDS.h include/configs/P1_P2_RDB.h include/configs/p1_p2_rdb_pc.h include/configs/p1_twr.h include/configs/P2020DS.h include/configs/P2041RDB.h include/configs/T1040QDS.h include/configs/t4qds.h
Scott,
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
York
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
-Scott
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
York
On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote: > Are SPL and TPL boot methods immune from the size issue here?
Sort of. We still need to fit inside existing partition tables.
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
There's no reason to change them all at once. It doesn't make anything easier; it just means you have to do a bunch of testing all at once, and force a change in procedure for users on boards where it otherwise would not have been required.
Plus, the 512K limit is for e500v2-based chips. Newer chips have CPC for SRAM which is larger than 512K.
-Scott
On 10/16/2013 01:41 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
On 10/16/2013 12:37 PM, Scott Wood wrote: > On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote: >> Are SPL and TPL boot methods immune from the size issue here? > > Sort of. We still need to fit inside existing partition tables. >
PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
There's no reason to change them all at once. It doesn't make anything easier; it just means you have to do a bunch of testing all at once, and force a change in procedure for users on boards where it otherwise would not have been required.
You are right here.
Plus, the 512K limit is for e500v2-based chips. Newer chips have CPC for SRAM which is larger than 512K.
Hmm? T4240 has 512KB CPC.
York
On Wed, 2013-10-16 at 13:44 -0700, York Sun wrote:
On 10/16/2013 01:41 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote: > On 10/16/2013 12:37 PM, Scott Wood wrote: >> On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote: >>> Are SPL and TPL boot methods immune from the size issue here? >> >> Sort of. We still need to fit inside existing partition tables. >> > > PBL boot will be broken if the image size is bigger than 512KB, right?
It has to be even smaller than that, to make room for early data.
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
There's no reason to change them all at once. It doesn't make anything easier; it just means you have to do a bunch of testing all at once, and force a change in procedure for users on boards where it otherwise would not have been required.
You are right here.
Plus, the 512K limit is for e500v2-based chips. Newer chips have CPC for SRAM which is larger than 512K.
Hmm? T4240 has 512KB CPC.
Each CPC is 512K, but there are three of them. Is it possible to use more than one for SRAM, contiguously?
Still, I find it curious that T4240 has less CPC than P4080, and less CPC than L2 cache.
-Scott
On 10/16/2013 02:23 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:44 -0700, York Sun wrote:
On 10/16/2013 01:41 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
On 10/16/2013 01:29 PM, Scott Wood wrote: > On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote: >> On 10/16/2013 12:37 PM, Scott Wood wrote: >>> On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote: >>>> Are SPL and TPL boot methods immune from the size issue here? >>> >>> Sort of. We still need to fit inside existing partition tables. >>> >> >> PBL boot will be broken if the image size is bigger than 512KB, right? > > It has to be even smaller than that, to make room for early data. >
So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
There's no reason to change them all at once. It doesn't make anything easier; it just means you have to do a bunch of testing all at once, and force a change in procedure for users on boards where it otherwise would not have been required.
You are right here.
Plus, the 512K limit is for e500v2-based chips. Newer chips have CPC for SRAM which is larger than 512K.
Hmm? T4240 has 512KB CPC.
Each CPC is 512K, but there are three of them. Is it possible to use more than one for SRAM, contiguously?
I think it is possible to use two CPC. The PBL boot method is hard-coded to take 512KB u-boot.bin and generate u-boot.pbl. It surely can be improved. My point is making a move for all concerned platforms may be easier for maintenance.
York
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of York Sun Sent: Thursday, October 17, 2013 4:14 AM To: Wood Scott-B07421 Cc: Tom Rini; u-boot@lists.denx.de Subject: Re: [U-Boot] powerpc/mpc85xx: Increase image size
On 10/16/2013 02:23 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:44 -0700, York Sun wrote:
On 10/16/2013 01:41 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
On 10/16/2013 01:33 PM, Scott Wood wrote:
On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote: > On 10/16/2013 01:29 PM, Scott Wood wrote: >> On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote: >>> On 10/16/2013 12:37 PM, Scott Wood wrote: >>>> On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote: >>>>> Are SPL and TPL boot methods immune from the size issue here? >>>> >>>> Sort of. We still need to fit inside existing partition
tables.
>>>> >>> >>> PBL boot will be broken if the image size is bigger than 512KB,
right?
>> >> It has to be even smaller than that, to make room for early data. >> > > So if we go with 768KB, do we have to convert all PBL boot to SPL
boot?
Only the targets that need the extra space.
We have T4, B4 and corenet_ds using PBL boot. They most likely will exceed the 512KB soon, if not yet. It maybe easier to change all of them togther, than one by one.
There's no reason to change them all at once. It doesn't make anything easier; it just means you have to do a bunch of testing all at once, and force a change in procedure for users on boards where it otherwise would not have been required.
You are right here.
Plus, the 512K limit is for e500v2-based chips. Newer chips have CPC for SRAM which is larger than 512K.
Hmm? T4240 has 512KB CPC.
Each CPC is 512K, but there are three of them. Is it possible to use more than one for SRAM, contiguously?
I think it is possible to use two CPC. The PBL boot method is hard-coded to take 512KB u-boot.bin and generate u-boot.pbl. It surely can be improved. My point is making a move for all concerned platforms may be easier for maintenance.
We can go ahead with 2 stage boot loaders for SoC having < 1MB CPC. We have already sent patch for T1040 which has 256K CPC. This same patch can be used for T4 and B4.
FYI, I have also sent one RFC for B4 with 2stage boot loader. It can be taken as full patch.
Regards, Prabhakar
participants (3)
-
Kushwaha Prabhakar-B32579 -
Scott Wood -
York Sun