[U-Boot] [PATCH V2 00/10] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html
Patch 6 is TEST_ONLY since Simon will be sending it as a part of device model changes.
Patch 10 is TEST_ONLY and it adds support for cros-ec on peach_pit. Simon will be sending a proper patchset for the same.
Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY
Ajay Kumar (9): [PATCH V2 1/10] exynos_fb: Remove usage of static defines [PATCH V2 2/10] arm: exynos: Add RPLL for Exynos5420 [PATCH V2 3/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V2 4/10] video: exynos_fimd: Add framework to disable FIMD sysmmu [TEST_ONLY V2 6/10] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V2 7/10] exynos5420: add callbacks needed for exynos_fb driver [PATCH V2 8/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V2 9/10] CONFIGS: peach_pit: Enable display for peach_pit board [TEST_ONLY V2 10/10] Pit WIP
Vadim Bendebury (1): [PATCH V2 5/10] video: Add driver for Parade PS8625 dP to LVDS bridge
arch/arm/cpu/armv7/exynos/clock.c | 83 +++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 ++++ arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h | 1 + arch/arm/include/asm/arch-exynos/system.h | 4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 ++++++--------- doc/device-tree-bindings/video/exynos-fb.txt | 6 + drivers/misc/cros_ec_spi.c | 4 +- drivers/power/pmic/Makefile | 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++ drivers/spi/exynos_spi.c | 9 +- drivers/spi/spi.c | 2 + drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c | 43 +++++ drivers/video/parade.c | 220 +++++++++++++++++++++++++ include/configs/exynos5-dt.h | 2 +- include/configs/exynos5250-dt.h | 2 - include/configs/peach-pit.h | 12 ++ include/configs/s5pc210_universal.h | 3 - include/configs/trats.h | 3 - include/configs/trats2.h | 3 - include/fdtdec.h | 2 + include/power/tps65090_pmic.h | 6 + lib/fdtdec.c | 2 + 30 files changed, 724 insertions(+), 119 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c create mode 100644 drivers/video/parade.c
Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/include/asm/arch-exynos/system.h | 1 + board/samsung/common/board.c | 15 +++++++++++++++ drivers/video/exynos_fb.c | 17 +++++------------ include/configs/exynos5250-dt.h | 2 -- include/configs/s5pc210_universal.h | 3 --- include/configs/trats.h | 3 --- include/configs/trats2.h | 3 --- 7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 7e2057c..4968d3d 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); +int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..1f6f0a0 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -20,6 +20,7 @@ #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> +#include <asm/arch/system.h> #include <power/pmic.h> #include <asm/arch/sromc.h> #include <lcd.h> @@ -148,6 +149,20 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB) +/* + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve + * FB memory at a very early stage. So, we need to fill panel_info.vl_col, + * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called. + */ + err = exynos_lcd_early_init(gd->fdt_blob); + if (err) { + debug("LCD early init failed\n"); + return err; + } +#endif + return exynos_early_init_f(); } #endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index e1e0d80..bc478a9 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/* - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve - * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt() - * is called. So, we are forced to statically assign it. - */ #ifdef CONFIG_OF_CONTROL vidinfo_t panel_info = { - .vl_col = LCD_XRES, - .vl_row = LCD_YRES, - .vl_bpix = LCD_COLOR16, + /* Insert a value here so that we don't end up in the BSS + * Reference: drivers/video/tegra.c + */ + .vl_col = -1, }; #endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid) }
#ifdef CONFIG_OF_CONTROL -int exynos_fimd_parse_dt(const void *blob) +int exynos_lcd_early_init(const void *blob) { unsigned int node; node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); @@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase) set_lcd_clk();
#ifdef CONFIG_OF_CONTROL - if (exynos_fimd_parse_dt(gd->fdt_blob)) - debug("Can't get proper panel info\n"); #ifdef CONFIG_EXYNOS_MIPI_DSIM exynos_init_dsim_platform_data(&panel_info); #endif diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 74e72a5..c24984b 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -61,8 +61,6 @@ #ifdef CONFIG_LCD #define CONFIG_EXYNOS_FB #define CONFIG_EXYNOS_DP -#define LCD_XRES 2560 -#define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index eb046cd..20985da 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -247,7 +247,4 @@ int universal_spi_read(void); #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480 -#define LCD_YRES 800 - #endif /* __CONFIG_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 90f1962..35c1feb 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -261,7 +261,4 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720 -#define LCD_YRES 1280 - #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 206975b..94c8a9f 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -241,7 +241,4 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720 -#define LCD_YRES 1280 - #endif /* __CONFIG_H */
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++ arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++++++++++++ 2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index a875d0b..fce502f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -75,6 +75,9 @@ struct mem_timings { unsigned spll_mdiv; unsigned spll_pdiv; unsigned spll_sdiv; + unsigned rpll_mdiv; + unsigned rpll_pdiv; + unsigned rpll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 1d6977f..b6a9bc1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, + /* RPLL @70.5Mhz */ + .rpll_mdiv = 0x5E, + .rpll_pdiv = 0x2, + .rpll_sdiv = 0x4,
.direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, @@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void) writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void) while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ;
+ /* Set RPLL */ + writel(RPLL_CON2_VAL, &clk->rpll_con2); + writel(RPLL_CON1_VAL, &clk->rpll_con1); + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); + writel(val, &clk->rpll_con0); + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) + ; + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/cpu/armv7/exynos/clock.c | 83 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 400d134..7558eff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || + pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void) clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); }
+void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else { + if (proid_is_exynos5420()) + return exynos5420_get_lcd_clk(); + else + return exynos5_get_lcd_clk(); + } }
void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); - else - exynos5_set_lcd_clk(); + else { + if (proid_is_exynos5250()) + exynos5_set_lcd_clk(); + if (proid_is_exynos5420()) + exynos5420_set_lcd_clk(); + } }
void set_mipi_clk(void) diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 3242093..2eea48a 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -783,7 +783,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ffbc07e..db24dc0 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4))
On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/dts/exynos54xx.dtsi | 10 +++++++ doc/device-tree-bindings/video/exynos-fb.txt | 6 ++++ drivers/video/exynos_fimd.c | 43 ++++++++++++++++++++++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index b9f8e0b..c21d798 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -113,6 +113,16 @@ status = "disabled"; };
+ fimdm0_sysmmu@0x14640000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14640000 0x100>; + }; + + fimdm1_sysmmu@0x14680000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14680000 0x100>; + }; + fimd@14400000 { /* sysmmu is not used in U-Boot */ samsung,disable-sysmmu; diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index bb7441c..dc4e44f 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -55,6 +55,12 @@ Board(panel specific): samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL) samsung,sclk-div: parent_clock/source_clock ratio samsung,dual-lcd-enabled: 1 if you support two LCD, else 0 + samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu. + (needed for Exynos5420 and newer versions) + Add the required FIMD sysmmu nodes to be + disabled with compatible string + "samsung,sysmmu-v3.3", with a "reg" property + holding the register address of FIMD sysmmu.
Example: SOC specific part: diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index cebbba7..f67fa81 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id) writel(cfg, &fimd_ctrl->winshmap); }
+#ifdef CONFIG_OF_CONTROL +/* +* The reset value for FIMD SYSMMU register MMU_CTRL is 3 +* on Exynos5420 and newer versions. +* This means FIMD SYSMMU is on by default on Exynos5420 +* and newer versions. +* Since in u-boot we don't use SYSMMU, we should disable +* those FIMD SYSMMU. +* Note that there are 2 SYSMMU for FIMD: m0 and m1. +* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3. +* We disable both of them here. +*/ +void exynos_fimd_disable_sysmmu(void) +{ + u32 *sysmmufimd; + unsigned int node; + int node_list[2]; + int count; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd", + COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2); + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) { + debug("Can't get device node for fimd sysmmu\n"); + return; + } + + sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (!sysmmufimd) { + debug("Can't get base address for sysmmu fimdm0"); + return; + } + + writel(0x0, sysmmufimd); + } +} +#endif
void exynos_fimd_lcd_init(vidinfo_t *vid) { @@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) node, "reg"); if (fimd_ctrl == NULL) debug("Can't get the FIMD base address\n"); + + if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) + exynos_fimd_disable_sysmmu(); + #else fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); #endif diff --git a/include/fdtdec.h b/include/fdtdec.h index a7e6ee7..a583d68 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -94,6 +94,7 @@ enum fdt_compat_id { COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ + COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 13d3d2f..1ccfb39 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -68,6 +68,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), COMPAT(TI_TPS65090, "ti,tps65090"), COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), + COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
From: Vadim Bendebury vbendeb@chromium.org
The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury vbendeb@chromium.org Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- drivers/video/Makefile | 1 + drivers/video/parade.c | 220 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 4 files changed, 223 insertions(+) create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 945f35d..8618590 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_FORMIKE) += formike.o +obj-$(CONFIG_VIDEO_PARADE) += parade.o diff --git a/drivers/video/parade.c b/drivers/video/parade.c new file mode 100644 index 0000000..36e5d80 --- /dev/null +++ b/drivers/video/parade.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * This file is a driver for Parade dP<->LVDS bridges. The original submission + * is for the ps8625 chip. + */ +#include <config.h> +#include <common.h> +#include <i2c.h> +#include <fdtdec.h> + +/* + * Initialization of the chip is a process of writing certaing values into + * certain registers over i2c bus. The chip in fact responds to a range of + * addresses on the i2c bus, so for each written value three parameters are + * required: i2c address, register address and the actual value. + * + * The base address is derived from the device tree, only address offset is + * stored in the table below. + */ +/** + * struct reg_data() - data for a parade register write + * + * @addr_off offset from the i2c base address for parade + * @reg_addr register address to write + * @value value to be written + */ +struct reg_data { + uint8_t addr_off; + uint8_t reg; + uint8_t value; +} _packed; + +#define END_OF_TABLE 0xff /* Ficticious offset */ + +static const struct reg_data parade_values[] = { + {0x02, 0xa1, 0x01}, /* HPD low */ + /* + * SW setting + * [1:0] SW output 1.2V voltage is lower to 96% + */ + {0x04, 0x14, 0x01}, + /* + * RCO SS setting + * [5:4] = b01 0.5%, b10 1%, b11 1.5% + */ + {0x04, 0xe3, 0x20}, + {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */ + /* + * RPHY Setting + * [3:2] CDR tune wait cycle before + * measure for fine tune b00: 1us, + * 01: 0.5us, 10:2us, 11:4us. + */ + {0x04, 0x8a, 0x0c}, + {0x04, 0x89, 0x08}, /* [3] RFD always on */ + /* + * CTN lock in/out: + * 20000ppm/80000ppm. Lock out 2 + * times. + */ + {0x04, 0x71, 0x2d}, + /* + * 2.7G CDR settings + * NOF=40LSB for HBR CDR setting + */ + {0x04, 0x7d, 0x07}, + {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */ + {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */ + /* + * 1.62G CDR settings + * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + */ + {0x04, 0xc0, 0x12}, + {0x04, 0xc1, 0x92}, /* Gitune=-37% */ + {0x04, 0xc2, 0x1c}, /* Fbstep=100% */ + {0x04, 0x32, 0x80}, /* [7] LOS signal disable */ + /* + * RPIO Setting + * [7:4] LVDS driver bias current : + * 75% (250mV swing) + */ + {0x04, 0x00, 0xb0}, + /* + * [7:6] Right-bar GPIO output strength is 8mA + */ + {0x04, 0x15, 0x40}, + /* EQ Training State Machine Setting */ + {0x04, 0x54, 0x10}, /* RCO calibration start */ + /* [4:0] MAX_LANE_COUNT set to one lane */ + {0x01, 0x02, 0x81}, + /* [4:0] LANE_COUNT_SET set to one lane */ + {0x01, 0x21, 0x81}, + {0x00, 0x52, 0x20}, + {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */ + {0x00, 0x62, 0x41}, + /* Counter number, add 1ms counter delay */ + {0x00, 0xf6, 0x01}, + /* + * [6]PWM function control by + * DPCD0040f[7], default is PWM + * block always works. + */ + {0x00, 0x77, 0x06}, + /* + * 04h Adjust VTotal tolerance to + * fix the 30Hz no display issue + */ + {0x00, 0x4c, 0x04}, + /* DPCD00400='h00, Parade OUI = 'h001cf8 */ + {0x01, 0xc0, 0x00}, + {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */ + {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */ + /* + * DPCD403~408 = ASCII code + * D2SLV5='h4432534c5635 + */ + {0x01, 0xc3, 0x44}, + {0x01, 0xc4, 0x32}, /* DPCD404 */ + {0x01, 0xc5, 0x53}, /* DPCD405 */ + {0x01, 0xc6, 0x4c}, /* DPCD406 */ + {0x01, 0xc7, 0x56}, /* DPCD407 */ + {0x01, 0xc8, 0x35}, /* DPCD408 */ + /* + * DPCD40A, Initial Code major revision + * '01' + */ + {0x01, 0xca, 0x01}, + /* DPCD40B, Initial Code minor revision '05' */ + {0x01, 0xcb, 0x05}, + /* DPCD720, Select internal PWM */ + {0x01, 0xa5, 0xa0}, + /* + * FFh for 100% PWM of brightness, 0h for 0% + * brightness + */ + {0x01, 0xa7, 0xff}, + /* + * Set LVDS output as 6bit-VESA mapping, + * single LVDS channel + */ + {0x01, 0xcc, 0x13}, + /* Enable SSC set by register */ + {0x02, 0xb1, 0x20}, + /* + * Set SSC enabled and +/-1% central + * spreading + */ + {0x04, 0x10, 0x16}, + /* MPU Clock source: LC => RCO */ + {0x04, 0x59, 0x60}, + {0x04, 0x54, 0x14}, /* LC -> RCO */ + {0x02, 0xa1, 0x91}, /* HPD high */ + {END_OF_TABLE} +}; + +/** + * Write values table into the Parade eDP bridge + * + * @return 0 on success, non-0 on failure + */ + +static int parade_write_regs(int base_addr, const struct reg_data *table) +{ + int ret = 0; + + while (!ret && (table->addr_off != END_OF_TABLE)) { + ret = i2c_write(base_addr + table->addr_off, + table->reg, 1, + (uint8_t *)&table->value, + sizeof(table->value)); + table++; + } + return ret; +} + +int parade_init(const void *blob) +{ + int bus, old_bus; + int parent; + int node; + int addr; + int ret; + + node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625); + if (node < 0) + return 0; + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Could not find parent i2c node\n", __func__); + return -1; + } + addr = fdtdec_get_int(blob, node, "reg", -1); + if (addr < 0) { + debug("%s: Could not find i2c address\n", __func__); + return -1; + } + + bus = i2c_get_bus_num_fdt(parent); + old_bus = i2c_get_bus_num(); + + debug("%s: Using i2c bus %d\n", __func__, bus); + + /* + * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay + * here. + */ + mdelay(40); + i2c_set_bus_num(bus); + ret = parade_write_regs(addr, parade_values); + + i2c_set_bus_num(old_bus); + + return ret; +} diff --git a/include/fdtdec.h b/include/fdtdec.h index a583d68..d4284bb 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -95,6 +95,7 @@ enum fdt_compat_id { COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ + COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 1ccfb39..c7c4854 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -69,6 +69,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(TI_TPS65090, "ti,tps65090"), COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), + COMPAT(PARADE_PS8625, "parade,ps8625"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
Dear Ajay Kumar,
In message 1403769668-2026-6-git-send-email-ajaykumar.rs@samsung.com you wrote: ...
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
NAK. We need precise licnese terms; just mentioning some "LICENSE file" without even telling us where to find it is definitely insufficient.
Please also make sure to use SPDX tags instead.
Best regards,
Wolfgang Denk
This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/include/asm/arch-exynos/gpio.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index be5113f..8fb5c23 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = { void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); +int gpio_direction_input(unsigned gpio); int gpio_direction_output(unsigned gpio, int value); int gpio_set_value(unsigned gpio, int value); int gpio_get_value(unsigned gpio);
Add initialization code for peach_pit panel, parade bridge chip, and backlight.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/include/asm/arch-exynos/system.h | 3 + board/samsung/smdk5420/smdk5420.c | 129 +++++++++++------------------- 2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 4968d3d..320763f 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */ +int parade_init(const void *blob); + #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 183c522..270ee83 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -10,11 +10,14 @@ #include <i2c.h> #include <lcd.h> #include <spi.h> +#include <errno.h> #include <asm/arch/board.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch/system.h> #include <asm/arch/dp_info.h> +#include <power/tps65090_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void) }
#ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +static int has_edp_bridge(void) { - /* For Backlight */ - gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5420_GPIO_B20, 1); + int node; + + node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */ - gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5420_GPIO_X15, 1); + /* No node for bridge in device tree. */ + if (node <= 0) + return 0;
- /* Set Hotplug detect for DP */ - gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3)); + /* Default is with bridge ic */ + return 1; }
-vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_power_on(void) { - vid->rgb_mode = MODE_RGB_P; + int ret; + +#ifdef CONFIG_POWER_TPS65090 + ret = tps65090_init(); + if (ret < 0) { + printf("%s: tps65090_init() failed\n", __func__); + return; + } + + tps65090_fet_enable(6); +#endif + + mdelay(5); + + /* TODO(ajaykumar.rs@samsung.com): Use device tree */ + gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ + mdelay(10); + gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data); + if (has_edp_bridge()) + if (parade_init(gd->fdt_blob)) + printf("%s: ps8625_init() failed\n", __func__); +} + +void exynos_backlight_on(unsigned int onoff) +{ + /* For PWM */ + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1)); + gpio_set_value(EXYNOS5420_GPIO_B20, 1); + +#ifdef CONFIG_POWER_TPS65090 + tps65090_fet_enable(1); +#endif } #endif
This patch adds DT properties for fimd and the parade bridge chip present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/dts/exynos5420-peach-pit.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 8d148af..3ed70a8 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -63,6 +63,11 @@ reg = <0x20>; compatible = "maxim,max98090-codec"; }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; };
sound@3830000 { @@ -124,4 +129,29 @@ xhci@12400000 { samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1366>; + samsung,vl-row = <768>; + samsung,vl-width = <1366>; + samsung,vl-height = <768>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <40>; + samsung,vl-hfpd = <40>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <10>; + samsung,vl-vfpd = <12>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; };
Enable drivers for FIMD, DP and parade bridge chip.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- include/configs/peach-pit.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING " for Peach"
+#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */
WIP patch to enable cros-ec on peach_pit.
Signed-off-by: Simon Glass sjg@chromium.org --- drivers/misc/cros_ec_spi.c | 4 +- drivers/power/pmic/Makefile | 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++++++++++++ drivers/spi/exynos_spi.c | 9 +- drivers/spi/spi.c | 2 + include/configs/exynos5-dt.h | 2 +- include/configs/peach-pit.h | 2 + include/power/tps65090_pmic.h | 6 + 8 files changed, 232 insertions(+), 8 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 7df709c..015333f 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -98,7 +98,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, }
out = dev->dout; - out[0] = cmd_version; + out[0] = EC_CMD_VERSION0 + cmd_version; out[1] = cmd; out[2] = (uint8_t)dout_len; memcpy(out + 3, dout, dout_len); @@ -165,7 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob) */ int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob) { - dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node); + dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node); if (!dev->spi) { debug("%s: Could not setup SPI slave\n", __func__); return -1; diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61..e7b07eb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -11,7 +11,8 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000..93b7923 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + */ + +#include <common.h> +#include <cros_ec.h> +#include <errno.h> +#include <power/tps65090_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -1 if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -1; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return FET_ERR_COMMS if we got a comms error, FET_ERR_NOT_READY if the + * FET failed to change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, int set) +{ + int retry; + u8 reg = 0, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return FET_ERR_COMMS; + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return FET_ERR_COMMS; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return FET_ERR_NOT_READY; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + int loops; + ulong start; + int ret = 0; + + if (tps65090_check_fet(fet_id)) + return -1; + + start = get_timer(0); + for (loops = 0; ; loops++) { + ret = tps65090_fet_set(fet_id, 1); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, 0); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == FET_ERR_NOT_READY) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + if (tps65090_check_fet(fet_id)) + return -1; + + ret = tps65090_fet_set(fet_id, 0); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + if (tps65090_check_fet(fet_id)) + return -1; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -2; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -1; + } + + return 0; +} diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index c92276f..2969184 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave) clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); debug("Activate CS, bus %d\n", spi_slave->slave.bus); spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE; - - /* Remember time of this transaction so we can honour the bus delay */ - if (spi_slave->bus->deactivate_delay_us) - spi_slave->last_transaction_us = timer_get_us(); }
/** @@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave) struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); + + /* Remember time of this transaction so we can honour the bus delay */ + if (spi_slave->bus->deactivate_delay_us) + spi_slave->last_transaction_us = timer_get_us(); + debug("Deactivate CS, bus %d\n", spi_slave->slave.bus); }
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 7ddea9b..7d81fbd 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, mode |= SPI_CPHA; if (fdtdec_get_bool(blob, node, "spi-cs-high")) mode |= SPI_CS_HIGH; + if (fdtdec_get_bool(blob, node, "spi-half-duplex")) + mode |= SPI_PREAMBLE; return spi_setup_slave(busnum, cs, max_hz, mode); } #endif diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index e36a031..4e316b9 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -37,8 +37,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000
/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE
/* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 88c093f..01be8a6 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,6 +22,8 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING " for Peach"
+#define CONFIG_POWER_TPS65090_EC + #define CONFIG_VIDEO_PARADE
/* Display */ diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h index dcf99c9..531751d 100644 --- a/include/power/tps65090_pmic.h +++ b/include/power/tps65090_pmic.h @@ -18,6 +18,12 @@ enum { TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, };
+/* FET errors */ +enum { + FET_ERR_COMMS = -1, /* FET comms error */ + FET_ERR_NOT_READY = -2, /* FET is not yet ready - retry */ +}; + /** * Enable FET *
Dear Ajay Kumar,
In message 1403769668-2026-11-git-send-email-ajaykumar.rs@samsung.com you wrote:
WIP patch to enable cros-ec on peach_pit.
Do you think anybody would be able to figure out what this is supposed to mean? I can't...
@@ -0,0 +1,212 @@ +/*
- Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
- Alternatively, this software may be distributed under the terms of the
- GNU General Public License ("GPL") version 2 as published by the Free
- Software Foundation.
- */
Please use SPDX license tags, and make sure to use GPL-2.0+ rather than GPL-2.0
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index c92276f..2969184 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave) clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); debug("Activate CS, bus %d\n", spi_slave->slave.bus); spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
- /* Remember time of this transaction so we can honour the bus delay */
- if (spi_slave->bus->deactivate_delay_us)
spi_slave->last_transaction_us = timer_get_us();}
/** @@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave) struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
- /* Remember time of this transaction so we can honour the bus delay */
- if (spi_slave->bus->deactivate_delay_us)
spi_slave->last_transaction_us = timer_get_us();- debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
}
Is this really a related change, or shoudl that go into a separate commit?
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 7ddea9b..7d81fbd 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, mode |= SPI_CPHA; if (fdtdec_get_bool(blob, node, "spi-cs-high")) mode |= SPI_CS_HIGH;
- if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
Ditto?
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index e36a031..4e316b9 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -37,8 +37,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000
/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE
Ditto?
Best regards,
Wolfgang Denk
Hi Denk,
On Thu, Jun 26, 2014 at 2:16 PM, Wolfgang Denk wd@denx.de wrote:
Dear Ajay Kumar,
In message 1403769668-2026-11-git-send-email-ajaykumar.rs@samsung.com you wrote:
WIP patch to enable cros-ec on peach_pit.
This Entire patch is a TEST_ONLY since it is still WIP(Work In Progress). That would mean somebody else is already working on it, but he/she hasn't sent that patchset yet, and till that comes up in the mailing list, this WIP patch can be used for testing the dependent patches. So, this would not be merged into the tree, but I thought its better to send it with a TEST_ONLY tag, so that maintainers can test this patchset.
Regards, Ajay Kumar
Do you think anybody would be able to figure out what this is supposed to mean? I can't...
@@ -0,0 +1,212 @@ +/*
- Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
- Alternatively, this software may be distributed under the terms of the
- GNU General Public License ("GPL") version 2 as published by the Free
- Software Foundation.
- */
Please use SPDX license tags, and make sure to use GPL-2.0+ rather than GPL-2.0
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index c92276f..2969184 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave) clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); debug("Activate CS, bus %d\n", spi_slave->slave.bus); spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
/* Remember time of this transaction so we can honour the bus delay */if (spi_slave->bus->deactivate_delay_us)spi_slave->last_transaction_us = timer_get_us();}
/** @@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave) struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
/* Remember time of this transaction so we can honour the bus delay */if (spi_slave->bus->deactivate_delay_us)spi_slave->last_transaction_us = timer_get_us();debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);}
Is this really a related change, or shoudl that go into a separate commit?
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 7ddea9b..7d81fbd 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, mode |= SPI_CPHA; if (fdtdec_get_bool(blob, node, "spi-cs-high")) mode |= SPI_CS_HIGH;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))mode |= SPI_PREAMBLE; return spi_setup_slave(busnum, cs, max_hz, mode);Ditto?
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index e36a031..4e316b9 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -37,8 +37,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000
/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE
Ditto?
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Politics: A strife of interests masquerading as a contest of principles. The conduct of public affairs for private advantage.
- Ambrose Bierce
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Dear Ajay kumar,
In message CAEC9eQNA9DkKhg9cgObaWTPrkmsn32jOrq9Uw2wgrDkedpRXAA@mail.gmail.com you wrote:
In message 1403769668-2026-11-git-send-email-ajaykumar.rs@samsung.com you wrote:
WIP patch to enable cros-ec on peach_pit.
This Entire patch is a TEST_ONLY since it is still WIP(Work In Progress). That would mean somebody else is already working on it, but he/she hasn't sent that patchset yet, and till that comes up in the mailing list, this WIP patch can be used for testing the dependent patches. So, this would not be merged into the tree, but I thought its better to send it with a TEST_ONLY tag, so that maintainers can test this patchset.
I don't think this is an excuse for cryptic or missing description of what this is about.
If you post something on the mailing list, then please make sure everybody can understand it. If the message is not intended to public audience, then don't post it here and use some other, more private form of communication.
Thanks.
Wolfgang Denk
On Thu, Jun 26, 2014 at 4:19 PM, Wolfgang Denk wd@denx.de wrote:
Dear Ajay kumar,
In message CAEC9eQNA9DkKhg9cgObaWTPrkmsn32jOrq9Uw2wgrDkedpRXAA@mail.gmail.com you wrote:
In message 1403769668-2026-11-git-send-email-ajaykumar.rs@samsung.com you wrote:
WIP patch to enable cros-ec on peach_pit.
This Entire patch is a TEST_ONLY since it is still WIP(Work In Progress). That would mean somebody else is already working on it, but he/she hasn't sent that patchset yet, and till that comes up in the mailing list, this WIP patch can be used for testing the dependent patches. So, this would not be merged into the tree, but I thought its better to send it with a TEST_ONLY tag, so that maintainers can test this patchset.
I don't think this is an excuse for cryptic or missing description of what this is about.
If you post something on the mailing list, then please make sure everybody can understand it. If the message is not intended to public audience, then don't post it here and use some other, more private form of communication.
I did mention about this in the cover letter. Still, I will make sure I elaborate more from the next time.
Thanks and regards, Ajay Kumar
participants (3)
-
Ajay Kumar -
Ajay kumar -
Wolfgang Denk