[U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/system.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 868ea54b4fef..c2d3718eb90c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -17,6 +17,7 @@ #define PGTABLE_SIZE (0x10000) /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 +#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
#ifndef __ASSEMBLY__
@@ -278,11 +279,6 @@ enum { */ void mmu_page_table_flush(unsigned long start, unsigned long stop);
-#ifdef CONFIG_SYS_NONCACHED_MEMORY -void noncached_init(void); -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x) @@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align); void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init(void); +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + #endif /* __ASSEMBLY__ */
#endif
From: Stephen Warren swarren@nvidia.com
In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/cpu/armv8/cache_v8.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf6a00e..f4b19272e17b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) }
/* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +__weak void mmu_setup(void) { bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
From: Stephen Warren swarren@nvidia.com
This sets up a fine-grained page table, which is a requirement for noncached_init() to operate correctly.
MMU setup code currently exists in a number of places: - A version in the core ARMv8 support code that sets up page tables that use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't support. - Enhanced versions for fsl-lsch3 and zynmq that set up finer grained page tables.
Ideally, rather than duplicating the MMU setup code yet again this patch would instead consolidate all the different routines into the core ARMv8 code so that it supported all use-cases. However, this will require significant effort since there appear to be a number of discrepancies[1] between different versions of the code, and between the defines/values by some copies of the MMU setup code use and the architectural MMU documentation. Some reverse engineering will be required to determine the intent of the current code.
[1] For example, in the core ARMv8 MMU setup code, three defines named TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and the others set a different field (T1SZ) in the page tables. As far as I can tell so far, there should be no need to set different values per exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't be enabled anyway. Another example is inconsistent values for *_VA_BITS between the current core ARMv8 MMU setup code and the various SoC- specific MMU setup code. Another example is that asm/armv8/mmu.h's value for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT; research is needed to determine which code relies on which of those values and why, and whether fixing the incorrect value will cause any regression.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/arm64-mmu.c | 131 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm/mach-tegra/arm64-mmu.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 75924ad84800..98431a91f875 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o obj-$(CONFIG_PWM_TEGRA) += pwm.o endif
+obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c new file mode 100644 index 000000000000..c2276523cb34 --- /dev/null +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) + +#define TCR_TG1_4K (1 << 31) +#define TCR_EPD1_DISABLE (1 << 23) +#define TEGRA_VA_BITS 40 +#define TEGRA_TCR TCR_TG1_4K | \ + TCR_EPD1_DISABLE | \ + TCR_SHARED_OUTER | \ + TCR_SHARED_INNER | \ + TCR_IRGN_WBWA | \ + TCR_ORGN_WBWA | \ + TCR_T0SZ(TEGRA_VA_BITS) + +#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ + PMD_ATTRINDX(MT_NORMAL) | \ + PMD_TYPE_SECT +#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ + PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ + PMD_TYPE_SECT + +/* 4K size is required to place 512 entries in each level */ +#define TLB_TABLE_SIZE 0x1000 + +/* + * This mmu table looks as below + * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 + * and other Level1 Table1. + * Level1 Table0 contains entries for each 1GB from 0 to 511GB. + * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. + * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains + * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. + */ +void mmu_setup(void) +{ + int el; + u64 i, section_l1t0, section_l1t1; + u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); + u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); + u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0, covering 0 to 512GB + * set level 1 table 1, covering 512GB to 1TB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + + for (i = 0; i < 512; i++) { + level1_table_0[i] = section_l1t0; + if (i >= 4) + level1_table_0[i] |= MEMORY_ATTR; + level1_table_1[i] = section_l1t1; + level1_table_1[i] |= MEMORY_ATTR; + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + level1_table_0[2] = + (u64)level2_table_2 | PMD_TYPE_TABLE; + level1_table_0[3] = + (u64)level2_table_3 | PMD_TYPE_TABLE; + + section_l2t0 = 0; + section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ + section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ + section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ + + for (i = 0; i < 512; i++) { + level2_table_0[i] = section_l2t0 | DEVICE_ATTR; + level2_table_1[i] = section_l2t1 | DEVICE_ATTR; + level2_table_2[i] = section_l2t2 | MEMORY_ATTR; + level2_table_3[i] = section_l2t3 | MEMORY_ATTR; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; + section_l2t2 += BLOCK_SIZE_L2; + section_l2t3 += BLOCK_SIZE_L2; + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TEGRA_TCR, MEMORY_ATTRIBUTES); + + set_sctlr(get_sctlr() | CR_M); +} + +u64 *arch_get_page_table(void) +{ + return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); +}
From: Stephen Warren swarren@nvidia.com
Now that we have solved the problems that prevented this feature from being enabled, enable it everywhere.
Signed-off-by: Stephen Warren swarren@nvidia.com --- include/configs/tegra-common-post.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 651c4c493536..68da23e8b70c 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif
-#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif
#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply this.
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply this.
I'll have a look at it in the coming days.
Amicalement,
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block
size.
The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply
this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
Tom -- nvpublic
Amicalement,
Albert.
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define
MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block
size.
The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply
this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom -- nvpublic
Tom
nvpublic
Amicalement,
Albert.
Albert,
Ping!
-----Original Message----- From: Tom Warren Sent: Tuesday, November 03, 2015 12:19 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal Simek' michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define
MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block
size.
The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply
this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom
nvpublic
Tom
-- nvpublic
Amicalement,
Albert.
TomR,
Any chance of you taking a look at these ARM MMU patches and either taking them in to u-boot/master or ACKing them so I can take them in via the Tegra repo?
Thanks,
TomW
-----Original Message----- From: Tom Warren Sent: Friday, November 06, 2015 9:32 AM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal Simek' michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
Ping!
-----Original Message----- From: Tom Warren Sent: Tuesday, November 03, 2015 12:19 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal
Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren
Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The implementation of noncached_init() uses define
MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block
size.
The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply
this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom
nvpublic
Tom
-- nvpublic
Amicalement,
Albert.
On Mon, Nov 09, 2015 at 11:28:27PM +0000, Tom Warren wrote:
TomR,
Any chance of you taking a look at these ARM MMU patches and either taking them in to u-boot/master or ACKing them so I can take them in via the Tegra repo?
So I know Albert was tacking a PR today and then ran into a bug with his Thumb-1 patchset. If they aren't in that PR then yes, I'll review/ack them but I suspect / hope Albert is taking a look and got side-tracked by the bug he found.
Thanks,
TomW
-----Original Message----- From: Tom Warren Sent: Friday, November 06, 2015 9:32 AM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal Simek' michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
Ping!
-----Original Message----- From: Tom Warren Sent: Tuesday, November 03, 2015 12:19 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal
Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren
Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote:
On 10/05/2015 12:08 PM, Stephen Warren wrote: > From: Stephen Warren swarren@nvidia.com > > The implementation of noncached_init() uses define
MMU_SECTION_SIZE.
> Define this on ARM64. > > Move the prototype of noncached_{init,alloc}() to a location > that doesn't depend on !defined(CONFIG_ARM64). > > Note that noncached_init() calls > mmu_set_region_dcache_behaviour() which relies on something > having set up translation tables with 2MB block
size.
> The core ARMv8 MMU setup code does not do this by default, but > currently relies on SoC specific MMU setup code. Be aware of > this before enabling this feature on your platform!
Albert, it looks like I forgot to add you to the CC on this email. Sorry! Could you please take a look at this series and tell me what you think? If you need a resend just let me know.
Also note that this series is a dependency for PCIe support on 64-bit Tegra systems; I guess either Tom Warren would be looking for an ack so he can apply the series to the Tegra tree, or perhaps if you just apply the whole series, he can base his branch on the branch where you apply
this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom
nvpublic
Tom
-- nvpublic
Amicalement,
Albert.
Thanks, Tom.
-----Original Message----- From: Tom Rini [mailto:trini@konsulko.com] Sent: Monday, November 09, 2015 4:36 PM To: Tom Warren TWarren@nvidia.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net; swarren@wwwdotorg.org; u- boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
- PGP Signed by an unknown key
On Mon, Nov 09, 2015 at 11:28:27PM +0000, Tom Warren wrote:
TomR,
Any chance of you taking a look at these ARM MMU patches and either taking them in to u-boot/master or ACKing them so I can take them in via the Tegra repo?
So I know Albert was tacking a PR today and then ran into a bug with his Thumb-1 patchset. If they aren't in that PR then yes, I'll review/ack them but I suspect / hope Albert is taking a look and got side-tracked by the bug he found.
Thanks,
TomW
-----Original Message----- From: Tom Warren Sent: Friday, November 06, 2015 9:32 AM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com;
'Michal Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
Ping!
-----Original Message----- From: Tom Warren Sent: Tuesday, November 03, 2015 12:19 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal
Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, October 21, 2015 11:26 PM To: Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom Warren TWarren@nvidia.com; Stephen Warren
Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren swarren@wwwdotorg.org wrote: > On 10/05/2015 12:08 PM, Stephen Warren wrote: > > From: Stephen Warren swarren@nvidia.com > > > > The implementation of noncached_init() uses define
MMU_SECTION_SIZE.
> > Define this on ARM64. > > > > Move the prototype of noncached_{init,alloc}() to a > > location that doesn't depend on !defined(CONFIG_ARM64). > > > > Note that noncached_init() calls > > mmu_set_region_dcache_behaviour() which relies on > > something having set up translation tables with 2MB block size. > > The core ARMv8 MMU setup code does not do this by default, > > but currently relies on SoC specific MMU setup code. Be > > aware of this before enabling this feature on your platform! > > Albert, it looks like I forgot to add you to the CC on this email. > Sorry! Could you please take a look at this series and tell > me what you think? If you need a resend just let me know. > > Also note that this series is a dependency for PCIe support > on 64-bit Tegra systems; I guess either Tom Warren would be > looking for an ack so he can apply the series to the Tegra > tree, or perhaps if you just apply the whole series, he can > base his branch on the branch where you apply this.
I'll have a look at it in the coming days.
Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom
nvpublic
Tom
-- nvpublic
Amicalement,
Albert.
-- Tom
- Unknown Key
- 0x56D6FECD
Hello Tom,
Switching to these ASAP. :)
On Tue, 10 Nov 2015 15:54:58 +0000, Tom Warren TWarren@nvidia.com wrote:
Thanks, Tom.
-----Original Message----- From: Tom Rini [mailto:trini@konsulko.com] Sent: Monday, November 09, 2015 4:36 PM To: Tom Warren TWarren@nvidia.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net; swarren@wwwdotorg.org; u- boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
- PGP Signed by an unknown key
On Mon, Nov 09, 2015 at 11:28:27PM +0000, Tom Warren wrote:
TomR,
Any chance of you taking a look at these ARM MMU patches and either taking them in to u-boot/master or ACKing them so I can take them in via the Tegra repo?
So I know Albert was tacking a PR today and then ran into a bug with his Thumb-1 patchset. If they aren't in that PR then yes, I'll review/ack them but I suspect / hope Albert is taking a look and got side-tracked by the bug he found.
Thanks,
TomW
-----Original Message----- From: Tom Warren Sent: Friday, November 06, 2015 9:32 AM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com;
'Michal Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
Ping!
-----Original Message----- From: Tom Warren Sent: Tuesday, November 03, 2015 12:19 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; 'Stephen Warren' swarren@wwwdotorg.org; Tom Rini (trini@konsulko.com) trini@konsulko.com Cc: 'u-boot@lists.denx.de' u-boot@lists.denx.de; 'Simon Glass' sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; 'York Sun' yorksun@freescale.com; 'Michal
Simek'
michal.simek@xilinx.com; 'tomcwarren3959@gmail.com' tomcwarren3959@gmail.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
-----Original Message----- From: Tom Warren Sent: Tuesday, October 27, 2015 1:39 PM To: 'Albert ARIBAUD' albert.u.boot@aribaud.net; Stephen Warren swarren@wwwdotorg.org Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Stephen Warren swarren@nvidia.com; Thierry Reding treding@nvidia.com; York Sun yorksun@freescale.com; Michal Simek michal.simek@xilinx.com Subject: RE: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
Albert,
> -----Original Message----- > From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] > Sent: Wednesday, October 21, 2015 11:26 PM > To: Stephen Warren swarren@wwwdotorg.org > Cc: u-boot@lists.denx.de; Simon Glass sjg@chromium.org; Tom > Warren TWarren@nvidia.com; Stephen Warren
> Thierry Reding treding@nvidia.com; York Sun > yorksun@freescale.com; Michal Simek > michal.simek@xilinx.com > Subject: Re: [U-Boot] [PATCH 1/4] armv8: enable compilation > with CONFIG_SYS_NONCACHED_MEMORY > > Hello Stephen, > > On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren > swarren@wwwdotorg.org wrote: > > On 10/05/2015 12:08 PM, Stephen Warren wrote: > > > From: Stephen Warren swarren@nvidia.com > > > > > > The implementation of noncached_init() uses define MMU_SECTION_SIZE. > > > Define this on ARM64. > > > > > > Move the prototype of noncached_{init,alloc}() to a > > > location that doesn't depend on !defined(CONFIG_ARM64). > > > > > > Note that noncached_init() calls > > > mmu_set_region_dcache_behaviour() which relies on > > > something having set up translation tables with 2MB block > size. > > > The core ARMv8 MMU setup code does not do this by default, > > > but currently relies on SoC specific MMU setup code. Be > > > aware of this before enabling this feature on your platform! > > > > Albert, it looks like I forgot to add you to the CC on this email. > > Sorry! Could you please take a look at this series and tell > > me what you think? If you need a resend just let me know. > > > > Also note that this series is a dependency for PCIe support > > on 64-bit Tegra systems; I guess either Tom Warren would be > > looking for an ack so he can apply the series to the Tegra > > tree, or perhaps if you just apply the whole series, he can > > base his branch on the branch where you apply > this. > > I'll have a look at it in the coming days. Please let me know when this series is in arm/master (or u-boot/master), as I need it to base Stephen's PCI/PCIe/XUSB patches on before I can send a PR for u-boot-tegra/master. Thanks!
I need this patchset in before I can add Stephen's PCIe/XUSB patchsets to Tegra U-Boot.
If you can Ack them, I can take them in via the Tegra repo, and send them upstream to TomR on my next PR. Or if you can let me know an ETA for getting them in to the ARM/master repo, I can base my schedule off of that. But I'm blocked until the ARMv8 MMU changes are in somewhere, and I'd like to clear this from my plate.
Thanks,
Tom
nvpublic
Tom
-- nvpublic
> > Amicalement, > -- > Albert.
-- Tom
- Unknown Key
- 0x56D6FECD
Amicalement,
participants (4)
-
Albert ARIBAUD -
Stephen Warren -
Tom Rini -
Tom Warren