[U-Boot] [PATCH 1/3] 85xx: Add support to populate addr map based on TLB settings
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/tlb.c | 34 ++++++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 3 +++ lib_ppc/board.c | 8 ++++++++ 3 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index a2d16ae..5b5f791 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -26,6 +26,11 @@ #include <common.h> #include <asm/processor.h> #include <asm/mmu.h> +#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + +DECLARE_GLOBAL_DATA_PTR;
void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, @@ -47,6 +52,11 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, mtspr(MAS7, _mas7); #endif asm volatile("isync;msync;tlbwe;isync"); + +#ifdef CONFIG_ADDR_MAP + if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) + addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); +#endif }
void disable_tlb(u8 esel) @@ -67,6 +77,11 @@ void disable_tlb(u8 esel) mtspr(MAS7, _mas7); #endif asm volatile("isync;msync;tlbwe;isync"); + +#ifdef CONFIG_ADDR_MAP + if (gd->flags & GD_FLG_RELOC) + addrmap_set_entry(0, 0, 0, esel); +#endif }
void invalidate_tlb(u8 tlb) @@ -91,6 +106,25 @@ void init_tlbs(void) return ; }
+#ifdef CONFIG_ADDR_MAP +void init_addr_map(void) +{ + int i; + + for (i = 0; i < num_tlb_entries; i++) { + if (tlb_table[i].tlb == 0) + continue; + + addrmap_set_entry(tlb_table[i].epn, + tlb_table[i].rpn, + (1UL << ((tlb_table[i].tsize * 2) + 10)), + tlb_table[i].esel); + } + + return ; +} +#endif + unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8975e6c..6d942d0 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -431,6 +431,9 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 289a32a..61c29b5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -75,6 +75,10 @@ #include <keyboard.h> #endif
+#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif + #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE extern int update_flash_size (int flash_size); #endif @@ -694,6 +698,10 @@ void board_init_r (gd_t *id, ulong dest_addr) */ trap_init (dest_addr);
+#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500) + init_addr_map(); +#endif + #if defined(CONFIG_BOARD_EARLY_INIT_R) board_early_init_r (); #endif
If we have addr map support enabled use the mapping functions to implement virt_to_phys() and map_physmem().
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- include/asm-ppc/io.h | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 64cb746..4ddad26 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -10,6 +10,10 @@ #include <linux/config.h> #include <asm/byteorder.h>
+#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399
@@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { +#ifdef CONFIG_ADDR_MAP + return (void *)(addrmap_phys_to_virt(paddr)); +#else return (void *)((unsigned long)paddr); +#endif }
/* @@ -300,7 +308,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
static inline phys_addr_t virt_to_phys(void * vaddr) { +#ifdef CONFIG_ADDR_MAP + return addrmap_virt_to_phys(vaddr); +#else return (phys_addr_t)((unsigned long)vaddr); +#endif }
#endif
The current code that determines which bank/chipselect is used for a given NAND instance only worked for 32-bit addresses and assumed a 1:1 mapping. This breaks in 36-bit physical configs.
The proper way to handle this is to use the virt_to_phys() and BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address with the the virtual address the NAND code uses.
Signed-off-by: Kumar Gala galak@kernel.crashing.org Acked-by: Scott Wood scottwood@freescale.com --- drivers/mtd/nand/fsl_elbc_nand.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 367c7d7..3f318e0 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -718,7 +718,7 @@ static void fsl_elbc_ctrl_init(void) int board_nand_init(struct nand_chip *nand) { struct fsl_elbc_mtd *priv; - uint32_t br, or; + uint32_t br = 0, or = 0;
if (!elbc_ctrl) { fsl_elbc_ctrl_init(); @@ -737,11 +737,13 @@ int board_nand_init(struct nand_chip *nand) * if we could pass more than one datum to the NAND driver... */ for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); + br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && - (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R) + (br & or & BR_BA) == BR_PHYS_ADDR(base_addr)) break; }
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Kumar Gala