[U-Boot] [PATCH v12 0/8] Add Intel Arria 10 SoC FPGA driver
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socfpga.git
[v11]: https://www.mail-archive.com/u-boot@lists.denx.de/msg255643.html
v11 -> v12 changes: ----------------- - Changed the commit messages of patch 5. - Separate patch for defconfig, header changes and minor code clean up.
Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg247788.html [v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg248541.html [v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg249160.html [v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250149.html [v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250517.html [v6]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250687.html [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg251213.html [v8]: https://www.mail-archive.com/u-boot@lists.denx.de/msg252196.html [v9]: https://www.mail-archive.com/u-boot@lists.denx.de/msg252422.html [v10]: https://www.mail-archive.com/u-boot@lists.denx.de/msg252583.html
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org
Tien Fong Chee (8): arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset arm: socfpga: Restructure FPGA driver in the preparation to support A10 kconfig: Convert FPGA and FPGA_ALTERA configuration to Kconfig kconfig: Convert FPGA_SOCFPGA configuration to Kconfig drivers: Enable FPGA driver build on SPL configs: Add FPGA driver config for Arria 10 arm: socfpga: Add FPGA driver support for Arria 10 arm: socfpga: Enable all FPGA config support for Arria 10
arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +-- .../include/mach/fpga_manager_arria10.h | 100 +++++ .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++- .../include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 4 +- configs/astro_mcf5373l_defconfig | 1 + configs/socfpga_arria10_defconfig | 2 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/theadorable_debug_defconfig | 1 + configs/theadorable_defconfig | 1 + drivers/Makefile | 1 + drivers/fpga/Kconfig | 8 + drivers/fpga/Makefile | 2 + drivers/fpga/socfpga.c | 235 +--------- drivers/fpga/socfpga_arria10.c | 479 +++++++++++++++++++++ drivers/fpga/{socfpga.c => socfpga_gen5.c} | 54 +-- include/configs/astro_mcf5373l.h | 2 - include/configs/socfpga_common.h | 6 +- include/configs/theadorable.h | 2 - 30 files changed, 658 insertions(+), 394 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%) create mode 100644 drivers/fpga/socfpga_arria10.c copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)
From: Tien Fong Chee tien.fong.chee@intel.com
Remove parameter from socfpga_bridges_reset(), and keeping this function for single purpose which is just triggering reset on bridges. socfpga_reset_deassert_bridges_handoff() can be called for releasing reset on any bridges based on the bridge setting defined in fdt.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 7922db8..b6d7f4f 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_assert_fpga_connected_peripherals(void); void socfpga_reset_deassert_osc1wd0(void); void socfpga_reset_uart(int assert); -int socfpga_bridges_reset(int enable); +int socfpga_bridges_reset(void);
struct socfpga_reset_manager { u32 stat; diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index d8c858c..66f1ec2 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void) }
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { /* For SoCFPGA-VT, this is NOP. */ return 0; } #else -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { int ret;
From: Tien Fong Chee tien.fong.chee@intel.com
Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 68 ++---- .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++--- drivers/fpga/Makefile | 1 + drivers/fpga/socfpga.c | 235 +-------------------- drivers/fpga/{socfpga.c => socfpga_gen5.c} | 54 +---- 6 files changed, 47 insertions(+), 382 deletions(-) copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%) copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 41b779c..286bfef 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@
obj-y += board.o obj-y += clock_manager.o -obj-y += fpga_manager.o obj-y += misc.o obj-y += reset_manager.o obj-y += timer.o @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o obj-y += scan_manager.o obj-y += system_manager_gen5.o obj-y += wrap_pll_config.o +obj-y += fpga_manager.o endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index a077e22..b046c2c 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -10,58 +10,9 @@
#include <altera.h>
-struct socfpga_fpga_manager { - /* FPGA Manager Module */ - u32 stat; /* 0x00 */ - u32 ctrl; - u32 dclkcnt; - u32 dclkstat; - u32 gpo; /* 0x10 */ - u32 gpi; - u32 misci; /* 0x18 */ - u32 _pad_0x1c_0x82c[517]; - - /* Configuration Monitor (MON) Registers */ - u32 gpio_inten; /* 0x830 */ - u32 gpio_intmask; - u32 gpio_inttype_level; - u32 gpio_int_polarity; - u32 gpio_intstatus; /* 0x840 */ - u32 gpio_raw_intstatus; - u32 _pad_0x848; - u32 gpio_porta_eoi; - u32 gpio_ext_porta; /* 0x850 */ - u32 _pad_0x854_0x85c[3]; - u32 gpio_1s_sync; /* 0x860 */ - u32 _pad_0x864_0x868[2]; - u32 gpio_ver_id_code; - u32 gpio_config_reg2; /* 0x870 */ - u32 gpio_config_reg1; -}; - -#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3 - -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 - -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 - -/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/fpga_manager_gen5.h> +#endif
/* FPGA CD Ratio Value */ #define CDRATIO_x1 0x0 @@ -69,9 +20,14 @@ struct socfpga_fpga_manager { #define CDRATIO_x4 0x2 #define CDRATIO_x8 0x3
-/* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void); +#ifndef __ASSEMBLY__ + +/* Common prototypes */ int fpgamgr_get_mode(void); +int fpgamgr_poll_fpga_ready(void); +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); +int fpgamgr_test_fpga_ready(void); +int fpgamgr_dclkcnt_set(unsigned long cnt);
+#endif /* __ASSEMBLY__ */ #endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h similarity index 57% copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h index a077e22..2de7a11 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h @@ -1,14 +1,38 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
-#ifndef _FPGA_MANAGER_H_ -#define _FPGA_MANAGER_H_ +#ifndef _FPGA_MANAGER_GEN5_H_ +#define _FPGA_MANAGER_GEN5_H_
-#include <altera.h> +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +#ifndef __ASSEMBLY__
struct socfpga_fpga_manager { /* FPGA Manager Module */ @@ -39,39 +63,6 @@ struct socfpga_fpga_manager { u32 gpio_config_reg1; };
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3 - -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 - -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 - -/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 - -/* FPGA CD Ratio Value */ -#define CDRATIO_x1 0x0 -#define CDRATIO_x2 0x1 -#define CDRATIO_x4 0x2 -#define CDRATIO_x8 0x3 - -/* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void); -int fpgamgr_get_mode(void); +#endif /* __ASSEMBLY__ */
-#endif /* _FPGA_MANAGER_H_ */ +#endif /* _FPGA_MANAGER_GEN5_H_ */ diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 777706f..b65e5ba 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o endif diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..28fa16b 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -19,18 +19,8 @@ DECLARE_GLOBAL_DATA_PTR;
static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Set CD ratio */ -static void fpgamgr_set_cd_ratio(unsigned long ratio) -{ - clrsetbits_le32(&fpgamgr_regs->ctrl, - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, - (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); -} - -static int fpgamgr_dclkcnt_set(unsigned long cnt) +int fpgamgr_dclkcnt_set(unsigned long cnt) { unsigned long i;
@@ -53,98 +43,8 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt) return -ETIMEDOUT; }
-/* Start the FPGA programming by initialize the FPGA Manager */ -static int fpgamgr_program_init(void) -{ - unsigned long msel, i; - - /* Get the MSEL value */ - msel = readl(&fpgamgr_regs->stat); - msel &= FPGAMGRREGS_STAT_MSEL_MASK; - msel >>= FPGAMGRREGS_STAT_MSEL_LSB; - - /* - * Set the cfg width - * If MSEL[3] = 1, cfg width = 32 bit - */ - if (msel & 0x8) { - setbits_le32(&fpgamgr_regs->ctrl, - FPGAMGRREGS_CTRL_CFGWDTH_MASK); - - /* To determine the CD ratio */ - /* MSEL[1:0] = 0, CD Ratio = 1 */ - if ((msel & 0x3) == 0x0) - fpgamgr_set_cd_ratio(CDRATIO_x1); - /* MSEL[1:0] = 1, CD Ratio = 4 */ - else if ((msel & 0x3) == 0x1) - fpgamgr_set_cd_ratio(CDRATIO_x4); - /* MSEL[1:0] = 2, CD Ratio = 8 */ - else if ((msel & 0x3) == 0x2) - fpgamgr_set_cd_ratio(CDRATIO_x8); - - } else { /* MSEL[3] = 0 */ - clrbits_le32(&fpgamgr_regs->ctrl, - FPGAMGRREGS_CTRL_CFGWDTH_MASK); - - /* To determine the CD ratio */ - /* MSEL[1:0] = 0, CD Ratio = 1 */ - if ((msel & 0x3) == 0x0) - fpgamgr_set_cd_ratio(CDRATIO_x1); - /* MSEL[1:0] = 1, CD Ratio = 2 */ - else if ((msel & 0x3) == 0x1) - fpgamgr_set_cd_ratio(CDRATIO_x2); - /* MSEL[1:0] = 2, CD Ratio = 4 */ - else if ((msel & 0x3) == 0x2) - fpgamgr_set_cd_ratio(CDRATIO_x4); - } - - /* To enable FPGA Manager configuration */ - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); - - /* To enable FPGA Manager drive over configuration line */ - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); - - /* Put FPGA into reset phase */ - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); - - /* (1) wait until FPGA enter reset phase */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) - break; - } - - /* If not in reset state, return error */ - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { - puts("FPGA: Could not reset\n"); - return -1; - } - - /* Release FPGA from reset phase */ - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); - - /* (2) wait until FPGA enter configuration phase */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) - break; - } - - /* If not in configuration state, return error */ - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { - puts("FPGA: Could not configure\n"); - return -2; - } - - /* Clear all interrupts in CB Monitor */ - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); - - /* Enable AXI configuration */ - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); - - return 0; -} - /* Write the RBF data to FPGA Manager */ -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) { uint32_t src = (uint32_t)rbf_data; uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; @@ -171,134 +71,3 @@ static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); }
-/* Ensure the FPGA entering config done */ -static int fpgamgr_program_poll_cd(void) -{ - const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | - FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; - unsigned long reg, i; - - /* (3) wait until full config done */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - reg = readl(&fpgamgr_regs->gpio_ext_porta); - - /* Config error */ - if (!(reg & mask)) { - printf("FPGA: Configuration error.\n"); - return -3; - } - - /* Config done without error */ - if (reg & mask) - break; - } - - /* Timeout happened, return error */ - if (i == FPGA_TIMEOUT_CNT) { - printf("FPGA: Timeout waiting for program.\n"); - return -4; - } - - /* Disable AXI configuration */ - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); - - return 0; -} - -/* Ensure the FPGA entering init phase */ -static int fpgamgr_program_poll_initphase(void) -{ - unsigned long i; - - /* Additional clocks for the CB to enter initialization phase */ - if (fpgamgr_dclkcnt_set(0x4)) - return -5; - - /* (4) wait until FPGA enter init phase or user mode */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) - break; - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) - break; - } - - /* If not in configuration state, return error */ - if (i == FPGA_TIMEOUT_CNT) - return -6; - - return 0; -} - -/* Ensure the FPGA entering user mode */ -static int fpgamgr_program_poll_usermode(void) -{ - unsigned long i; - - /* Additional clocks for the CB to exit initialization phase */ - if (fpgamgr_dclkcnt_set(0x5000)) - return -7; - - /* (5) wait until FPGA enter user mode */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) - break; - } - /* If not in configuration state, return error */ - if (i == FPGA_TIMEOUT_CNT) - return -8; - - /* To release FPGA Manager drive over configuration line */ - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); - - return 0; -} - -/* - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. - * Return 0 for sucess, non-zero for error. - */ -int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) -{ - unsigned long status; - - if ((uint32_t)rbf_data & 0x3) { - puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); - return -EINVAL; - } - - /* Prior programming the FPGA, all bridges need to be shut off */ - - /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); - - /* Disable all signals from FPGA to HPS SDRAM */ -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 - writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); - - /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ - socfpga_bridges_reset(1); - - /* Unmap the bridges from NIC-301 */ - writel(0x1, SOCFPGA_L3REGS_ADDRESS); - - /* Initialize the FPGA Manager */ - status = fpgamgr_program_init(); - if (status) - return status; - - /* Write the RBF data to FPGA Manager */ - fpgamgr_program_write(rbf_data, rbf_size); - - /* Ensure the FPGA entering config done */ - status = fpgamgr_program_poll_cd(); - if (status) - return status; - - /* Ensure the FPGA entering init phase */ - status = fpgamgr_program_poll_initphase(); - if (status) - return status; - - /* Ensure the FPGA entering user mode */ - return fpgamgr_program_poll_usermode(); -} diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c similarity index 83% copy from drivers/fpga/socfpga.c copy to drivers/fpga/socfpga_gen5.c index f1b2f2c..3dfb030 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga_gen5.c @@ -14,8 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */ -#define FPGA_TIMEOUT_CNT 0x1000000 +#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; @@ -30,29 +29,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio) (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); }
-static int fpgamgr_dclkcnt_set(unsigned long cnt) -{ - unsigned long i; - - /* Clear any existing done status */ - if (readl(&fpgamgr_regs->dclkstat)) - writel(0x1, &fpgamgr_regs->dclkstat); - - /* Write the dclkcnt */ - writel(cnt, &fpgamgr_regs->dclkcnt); - - /* Wait till the dclkcnt done */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - if (!readl(&fpgamgr_regs->dclkstat)) - continue; - - writel(0x1, &fpgamgr_regs->dclkstat); - return 0; - } - - return -ETIMEDOUT; -} - /* Start the FPGA programming by initialize the FPGA Manager */ static int fpgamgr_program_init(void) { @@ -143,34 +119,6 @@ static int fpgamgr_program_init(void) return 0; }
-/* Write the RBF data to FPGA Manager */ -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) -{ - uint32_t src = (uint32_t)rbf_data; - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; - - /* Number of loops for 32-byte long copying. */ - uint32_t loops32 = rbf_size / 32; - /* Number of loops for 4-byte long copying + trailing bytes */ - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); - - asm volatile( - "1: ldmia %0!, {r0-r7}\n" - " stmia %1!, {r0-r7}\n" - " sub %1, #32\n" - " subs %2, #1\n" - " bne 1b\n" - " cmp %3, #0\n" - " beq 3f\n" - "2: ldr %2, [%0], #4\n" - " str %2, [%1]\n" - " subs %3, #1\n" - " bne 2b\n" - "3: nop\n" - : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); -} - /* Ensure the FPGA entering config done */ static int fpgamgr_program_poll_cd(void) {
From: Tien Fong Chee tien.fong.chee@intel.com
This converts the following to Kconfig: CONFIG_FPGA CONFIG_FPGA_ALTERA
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- configs/astro_mcf5373l_defconfig | 1 + configs/theadorable_debug_defconfig | 1 + configs/theadorable_defconfig | 1 + include/configs/astro_mcf5373l.h | 2 -- include/configs/theadorable.h | 2 -- 5 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index d5e8430..80fb1fa 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y +CONFIG_FPGA_ALTERA=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 2164237..e07b7b6 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_FPGA_ALTERA=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig index d5eef70..3d2977c 100644 --- a/configs/theadorable_defconfig +++ b/configs/theadorable_defconfig @@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SPL_OF_TRANSLATE=y +CONFIG_FPGA_ALTERA=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 8899579..f4acea1 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -201,10 +201,8 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 -#define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_CYCLON2 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 2a671e8..5459f4f 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -89,8 +89,6 @@ #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
/* FPGA programming support */ -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_STRATIX_V
/*
From: Tien Fong Chee tien.fong.chee@intel.com
This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/fpga/Kconfig | 8 ++++++++ include/configs/socfpga_common.h | 3 --- 13 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a565384..6f2a06f 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 06fc82c..1047657 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 0697e2e..72a9e5d 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index cd64fb9..67864cf 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_DM=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index bba90be..35c4484 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_DM=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 058791e..ae688f8 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 627b90f..c5e3b7b 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index bf5d63d..3ff7bb7 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 5915faf..fb9c13f 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 4468d3b..d90d6a1 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index fb9bae4..c3fbe40 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_LED_STATUS=y diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index a760944..6b2c866 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -13,6 +13,14 @@ config FPGA_ALTERA Enable Altera FPGA specific functions which includes bitstream (in BIT format), fpga and device validation.
+config FPGA_SOCFPGA + bool "Enable Gen5 and Arria10 common FPGA drivers" + select FPGA_ALTERA + help + Say Y here to enable the Gen5 and Arria10 common FPGA driver + + This provides common functionality for Gen5 and Arria10 devices. + config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index da7e4ad..1b79c03 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -107,9 +107,6 @@ */ #ifdef CONFIG_TARGET_SOCFPGA_GEN5 #ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_SOCFPGA #define CONFIG_FPGA_COUNT 1 #endif #endif
From: Tien Fong Chee tien.fong.chee@intel.com
Enable FPGA driver build for Arria 10 SPL because FPGA driver is needed by Arria 10 SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- drivers/Makefile | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/Makefile b/drivers/Makefile index 64c39d3..4478212 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ +obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ endif
ifdef CONFIG_TPL_BUILD
From: Tien Fong Chee tien.fong.chee@intel.com
Add FPGA driver config for Arria 10.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- configs/socfpga_arria10_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 46bda47..53ab66f 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10" CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_SPL=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y @@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y
From: Tien Fong Chee tien.fong.chee@intel.com
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 + .../include/mach/fpga_manager_arria10.h | 100 +++++ drivers/fpga/Makefile | 1 + drivers/fpga/socfpga_arria10.c | 479 +++++++++++++++++++++ 4 files changed, 582 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h create mode 100644 drivers/fpga/socfpga_arria10.c
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index b046c2c..a21c716 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -12,6 +12,8 @@
#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <asm/arch/fpga_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/fpga_manager_arria10.h> #endif
/* FPGA CD Ratio Value */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h new file mode 100644 index 0000000..9cbf696 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _FPGA_MANAGER_ARRIA10_H_ +#define _FPGA_MANAGER_ARRIA10_H_ + +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 + +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 + +#ifndef __ASSEMBLY__ + +struct socfpga_fpga_manager { + u32 _pad_0x0_0x7[2]; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; + u32 gpi; + u32 misci; + u32 _pad_0x1c_0x2f[5]; + u32 emr_data0; + u32 emr_data1; + u32 emr_data2; + u32 emr_data3; + u32 emr_data4; + u32 emr_data5; + u32 emr_valid; + u32 emr_en; + u32 jtag_config; + u32 jtag_status; + u32 jtag_kick; + u32 _pad_0x5c_0x5f; + u32 jtag_data_w; + u32 jtag_data_r; + u32 _pad_0x68_0x6f[2]; + u32 imgcfg_ctrl_00; + u32 imgcfg_ctrl_01; + u32 imgcfg_ctrl_02; + u32 _pad_0x7c_0x7f; + u32 imgcfg_stat; + u32 intr_masked_status; + u32 intr_mask; + u32 intr_polarity; + u32 dma_config; + u32 imgcfg_fifo_status; +}; + +/* Functions */ +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); +int fpgamgr_program_finish(void); +int is_fpgamgr_user_mode(void); +int fpgamgr_wait_early_user_mode(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _FPGA_MANAGER_ARRIA10_H_ */ diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index b65e5ba..08c9ff8 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c new file mode 100644 index 0000000..5c1a68a --- /dev/null +++ b/drivers/fpga/socfpga_arria10.c @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/io.h> +#include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/misc.h> +#include <altera.h> +#include <common.h> +#include <errno.h> +#include <wait_bit.h> +#include <watchdog.h> + +#define CFGWDTH_32 1 +#define MIN_BITSTREAM_SIZECHECK 230 +#define ENCRYPTION_OFFSET 69 +#define COMPRESSION_OFFSET 229 +#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_fpga_manager *fpga_manager_base = + (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; + +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +static void fpgamgr_set_cd_ratio(unsigned long ratio); + +static uint32_t fpgamgr_get_msel(void) +{ + u32 reg; + + reg = readl(&fpga_manager_base->imgcfg_stat); + reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB; + + return reg; +} + +static void fpgamgr_set_cfgwdth(int width) +{ + if (width) + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); + else + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); +} + +int is_fpgamgr_user_mode(void) +{ + return (readl(&fpga_manager_base->imgcfg_stat) & + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0; +} + +static int wait_for_user_mode(void) +{ + return wait_for_bit(__func__, + &fpga_manager_base->imgcfg_stat, + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK, + 1, FPGA_TIMEOUT_MSEC, false); +} + +static int is_fpgamgr_early_user_mode(void) +{ + return (readl(&fpga_manager_base->imgcfg_stat) & + ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; +} + +int fpgamgr_wait_early_user_mode(void) +{ + u32 sync_data = 0xffffffff; + u32 i = 0; + unsigned start = get_timer(0); + unsigned long cd_ratio; + + /* Getting existing CDRATIO */ + cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB; + + /* Using CDRATIO_X1 for better compatibility */ + fpgamgr_set_cd_ratio(CDRATIO_x1); + + while (!is_fpgamgr_early_user_mode()) { + if (get_timer(start) > FPGA_TIMEOUT_MSEC) + return -ETIMEDOUT; + fpgamgr_program_write((const long unsigned int *)&sync_data, + sizeof(sync_data)); + udelay(FPGA_TIMEOUT_MSEC); + i++; + } + + debug("Additional %i sync word needed\n", i); + + /* restoring original CDRATIO */ + fpgamgr_set_cd_ratio(cd_ratio); + + return 0; +} + +/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */ +static int wait_for_nconfig_pin_and_nstatus_pin(void) +{ + unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK | + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK; + + /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted, + * timeout at 1000ms + */ + return wait_for_bit(__func__, + &fpga_manager_base->imgcfg_stat, + mask, + false, FPGA_TIMEOUT_MSEC, false); +} + +static int wait_for_f2s_nstatus_pin(unsigned long value) +{ + /* Poll until f2s to specific value, timeout at 1000ms */ + return wait_for_bit(__func__, + &fpga_manager_base->imgcfg_stat, + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK, + value, FPGA_TIMEOUT_MSEC, false); +} + +/* set CD ratio */ +static void fpgamgr_set_cd_ratio(unsigned long ratio) +{ + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); + + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); +} + +/* get the MSEL value, verify we are set for FPP configuration mode */ +static int fpgamgr_verify_msel(void) +{ + u32 msel = fpgamgr_get_msel(); + + if (msel & ~BIT(0)) { + printf("Fail: read msel=%d\n", msel); + return -EPERM; + } + + return 0; +} + +/* + * Write cdratio and cdwidth based on whether the bitstream is compressed + * and/or encoded + */ +static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data, + size_t rbf_size) +{ + unsigned int cd_ratio; + bool encrypt, compress; + + /* + * According to the bitstream specification, + * both encryption and compression status are + * in location before offset 230 of the buffer. + */ + if (rbf_size < MIN_BITSTREAM_SIZECHECK) + return -EINVAL; + + encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3; + encrypt = encrypt != 0; + + compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1; + compress = !compress; + + debug("header word %d = %08x\n", 69, rbf_data[69]); + debug("header word %d = %08x\n", 229, rbf_data[229]); + debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress); + + /* + * from the register map description of cdratio in imgcfg_ctrl_02: + * Normal Configuration : 32bit Passive Parallel + * Partial Reconfiguration : 16bit Passive Parallel + */ + + /* + * cd ratio is dependent on cfg width and whether the bitstream + * is encrypted and/or compressed. + * + * | width | encr. | compr. | cd ratio | + * | 16 | 0 | 0 | 1 | + * | 16 | 0 | 1 | 4 | + * | 16 | 1 | 0 | 2 | + * | 16 | 1 | 1 | 4 | + * | 32 | 0 | 0 | 1 | + * | 32 | 0 | 1 | 8 | + * | 32 | 1 | 0 | 4 | + * | 32 | 1 | 1 | 8 | + */ + if (!compress && !encrypt) { + cd_ratio = CDRATIO_x1; + } else { + if (compress) + cd_ratio = CDRATIO_x4; + else + cd_ratio = CDRATIO_x2; + + /* if 32 bit, double the cd ratio (so register + field setting is incremented) */ + if (cfg_width == CFGWDTH_32) + cd_ratio += 1; + } + + fpgamgr_set_cfgwdth(cfg_width); + fpgamgr_set_cd_ratio(cd_ratio); + + return 0; +} + +static int fpgamgr_reset(void) +{ + unsigned long reg; + + /* S2F_NCONFIG = 0 */ + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); + + /* Wait for f2s_nstatus == 0 */ + if (wait_for_f2s_nstatus_pin(0)) + return -ETIME; + + /* S2F_NCONFIG = 1 */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); + + /* Wait for f2s_nstatus == 1 */ + if (wait_for_f2s_nstatus_pin(1)) + return -ETIME; + + /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */ + reg = readl(&fpga_manager_base->imgcfg_stat); + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0) + return -EPERM; + + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0) + return -EPERM; + + return 0; +} + +/* Start the FPGA programming by initialize the FPGA Manager */ +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size) +{ + int ret; + + /* Step 1 */ + if (fpgamgr_verify_msel()) + return -EPERM; + + /* Step 2 */ + if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size)) + return -EPERM; + + /* + * Step 3: + * Make sure no other external devices are trying to interfere with + * programming: + */ + if (wait_for_nconfig_pin_and_nstatus_pin()) + return -ETIME; + + /* + * Step 4: + * Deassert the signal drives from HPS + * + * S2F_NCE = 1 + * S2F_PR_REQUEST = 0 + * EN_CFG_CTRL = 0 + * EN_CFG_DATA = 0 + * S2F_NCONFIG = 1 + * S2F_NSTATUS_OE = 0 + * S2F_CONDONE_OE = 0 + */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); + + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK); + + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); + + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); + + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK | + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK); + + /* + * Step 5: + * Enable overrides + * S2F_NENABLE_CONFIG = 0 + * S2F_NENABLE_NCONFIG = 0 + */ + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); + + /* + * Disable driving signals that HPS doesn't need to drive. + * S2F_NENABLE_NSTATUS = 1 + * S2F_NENABLE_CONDONE = 1 + */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK | + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK); + + /* + * Step 6: + * Drive chip select S2F_NCE = 0 + */ + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); + + /* Step 7 */ + if (wait_for_nconfig_pin_and_nstatus_pin()) + return -ETIME; + + /* Step 8 */ + ret = fpgamgr_reset(); + + if (ret) + return ret; + + /* + * Step 9: + * EN_CFG_CTRL and EN_CFG_DATA = 1 + */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); + + return 0; +} + +/* Ensure the FPGA entering config done */ +static int fpgamgr_program_poll_cd(void) +{ + unsigned long reg, i; + + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + reg = readl(&fpga_manager_base->imgcfg_stat); + if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) + return 0; + + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) { + printf("nstatus == 0 while waiting for condone\n"); + return -EPERM; + } + } + + if (i == FPGA_TIMEOUT_CNT) + return -ETIME; + + return 0; +} + +/* Ensure the FPGA entering user mode */ +static int fpgamgr_program_poll_usermode(void) +{ + unsigned long reg; + int ret = 0; + + if (fpgamgr_dclkcnt_set(0xf)) + return -ETIME; + + ret = wait_for_user_mode(); + if (ret < 0) { + printf("%s: Failed to enter user mode with ", __func__); + printf("error code %d\n", ret); + return ret; + } + + /* + * Step 14: + * Stop DATA path and Dclk + * EN_CFG_CTRL and EN_CFG_DATA = 0 + */ + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); + + /* + * Step 15: + * Disable overrides + * S2F_NENABLE_CONFIG = 1 + * S2F_NENABLE_NCONFIG = 1 + */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); + + /* Disable chip select S2F_NCE = 1 */ + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); + + /* + * Step 16: + * Final check + */ + reg = readl(&fpga_manager_base->imgcfg_stat); + if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) || + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != + ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) || + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) != + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK)) + return -EPERM; + + return 0; +} + +int fpgamgr_program_finish(void) +{ + /* Ensure the FPGA entering config done */ + int status = fpgamgr_program_poll_cd(); + + if (status) { + printf("FPGA: Poll CD failed with error code %d\n", status); + return -EPERM; + } + WATCHDOG_RESET(); + + /* Ensure the FPGA entering user mode */ + status = fpgamgr_program_poll_usermode(); + if (status) { + printf("FPGA: Poll usermode failed with error code %d\n", + status); + return -EPERM; + } + + printf("Full Configuration Succeeded.\n"); + + return 0; +} + +/* + * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. + * Return 0 for sucess, non-zero for error. + */ +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + unsigned long status; + + /* disable all signals from hps peripheral controller to fpga */ + writel(0, &system_manager_base->fpgaintf_en_global); + + /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ + socfpga_bridges_reset(); + + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); + if (status) + return status; + + /* Write the RBF data to FPGA Manager */ + fpgamgr_program_write(rbf_data, rbf_size); + + return fpgamgr_program_finish(); +}
From: Tien Fong Chee tien.fong.chee@intel.com
Enable all FPGA config support for Arria 10.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Dinh Nguyen dinguyen@kernel.org --- include/configs/socfpga_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 1b79c03..edd973a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -105,11 +105,10 @@ /* * FPGA Driver */ -#ifdef CONFIG_TARGET_SOCFPGA_GEN5 #ifdef CONFIG_CMD_FPGA #define CONFIG_FPGA_COUNT 1 #endif -#endif + /* * L4 OSC1 Timer 0 */
On 07/21/2017 10:22 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socfpga.git
Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.
On Jum, 2017-07-21 at 11:06 +0200, Marek Vasut wrote:
On 07/21/2017 10:22 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-so cfpga.git
Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.
Sure. So repost with same version 12?
Thanks.
On 07/24/2017 07:49 AM, Chee, Tien Fong wrote:
On Jum, 2017-07-21 at 11:06 +0200, Marek Vasut wrote:
On 07/21/2017 10:22 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-so cfpga.git
Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.
Sure. So repost with same version 12?
That'd be v13 ...
On Jul 24, 2017 8:41 PM, "Marek Vasut" marex@denx.de wrote:
On 07/24/2017 07:49 AM, Chee, Tien Fong wrote:
On Jum, 2017-07-21 at 11:06 +0200, Marek Vasut wrote:
On 07/21/2017 10:22 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-so cfpga.git
Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.
Sure. So repost with same version 12?
That'd be v13 ...
-- Best regards, Marek Vasut
On Isn, 2017-07-24 at 14:09 +0200, Marek Vasut wrote:
On 07/24/2017 07:49 AM, Chee, Tien Fong wrote:
On Jum, 2017-07-21 at 11:06 +0200, Marek Vasut wrote:
On 07/21/2017 10:22 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boo t-so cfpga.git
Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.
Sure. So repost with same version 12?
That'd be v13 ...
Okay, i repost again.
participants (4)
-
chee skywind -
Chee, Tien Fong -
Marek Vasut -
tien.fong.chee＠intel.com