[U-Boot] Export redesign
Hello, while trying to eliminate the XF_xxx enums, i came to a point in examples/standalone/stubs.c In the definition of EXPORT_FUNC for CONFIG_AVR32 the XF_ ##x is not multiplied with sizeof(void*) . Is this a bug or a avr feature ?
Regards Martin
+avr32 maintainer
Hi,
On 26 November 2014 at 01:07, Martin Dorwig dorwig@tetronik.com wrote:
Hello, while trying to eliminate the XF_xxx enums, i came to a point in examples/standalone/stubs.c In the definition of EXPORT_FUNC for CONFIG_AVR32 the XF_ ##x is not multiplied with sizeof(void*) . Is this a bug or a avr feature ?
I know nothing about this arch, but I found this link which suggests that the shift is implicit for the ld.w instruction:
http://www.avrfreaks.net/forum/ldw-instruction-syntax
So probably it is correct as is.
Regards, Simon
Hello,
for CONFIG_AVR32 the macro looks like this: #define EXPORT_FUNC(x) \ asm volatile( \ " .globl\t" #x "\n" \ #x ":\n" \ " ld.w r8, r6[%0]\n" \ " ld.w pc, r8[%1]\n" \ : \ : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ : "r8"); if there is an implicit shift in the ld.w instructuions, then the ld.w r8,r6[%0] is wrong, because offsetof(gd_t, jt) is the offset in bytes. if there is no shift, then the ld.w pc,r8[%1] is wrong, because the XF_ ## is not multiplied by sizeof(void*)
the syntax from the avr32 manual shows
Operation: III. Rd ← *(Rp + (ZE(disp5) << 2)); IV. Rd ← *(Rp + (SE(disp16)));
Syntax: III. ld.w Rd, Rp[disp] IV. ld.w Rd, Rp[disp]
my interpretation is : the assembler checks if (disp % 4 == 0) && disp <= 124 then is uses variant III and places disp >> 2 as disp5 into the instruction. else it uses variant IV and places disp as disp16 into the extension word of the instruction.
Regards Martin
participants (2)
-
Martin Dorwig -
Simon Glass