[U-Boot] [PATCH 00/60] ARM: tegra: cleanup part 1
From: Stephen Warren swarren@nvidia.com
This series cleans up Tegra code: - Removes unused definitions. - Unifies duplicate definitions and code. - Moves Tegra headers from arch/arm/include to arch/arm/mach-tegra so all Tegra files are located together. Headers for Tegra-specific APIs (intended e.g. for public/driver use) are placed into <mach/>, whereas headers intended only for use by code in arch/arm/mach-tegra are placed into <soc/>. - Hides as much internal Tegra information as possible, to reduce the size of the "API" provided to Tegra boards. This will help refactoring that "API" later; the next chip is quite different and various parts of this API (e.g. clock, reset, GPIO, ...) will need alternative implementations. This will hopefully be a bit easier after this series. - Cleans up the set of functions the core Tegra "board" support calls and which are implemented by Tegra board files. - Replaces funcmux with pinmux functions so that pinmux is set up in as much the same way across all Tegra SoCs as possible. - Various other cleanup. - Removes almost 3000 lines!
Future changes/series will likely/hopefully: - Refactor C files in arch/arm/mach-tegra to allow Makefiles to easily decide which parts to pull in for each chip, and avoid a mess of ifdefs in the C files when adding support for the next chip. - Convert Tegra to standard clock/reset APIs, since the next chipd will use a different implementation, yet we need them to share the same API so that drivers don't need conditional code. - Add some new drivers for the next chip.
Stephen Warren (60): ARM: tegra: remove unused definitions in headers mmc: tegra: move pad init into MMC driver mmc: tegra: move header file to driver directory mmc: tegra: move public header to arch/arm/mach-tegra/include pwm: tegra: move header file to driver directory i2c: tegra: move header file to driver directory usb: tegra: move header file to driver directory video: tegra: move header file to driver directory ARM: tegra: correct 64-bit DT unit addresses ARM: tegra: sort DT /aliases entries ARM: tegra: add DT alias for GPIO controller gpio: tegra: remove duplicate define ARM: tegra: sort some board file include directives ARM: tegra: use DT bindings for GPIO naming gpio: tegra: header file split ARM: tegra: migrate TEGRA_GPIO to Kconfig ARM: tegra: move apb_misc.h ARM: tegra: move fuse.h ARM: tegra: move gpu.h ARM: tegra: move pmc.h ARM: tegra: move scu.h ARM: tegra: move warmboot.h ARM: tegra: move xusb-padctl.h to <mach/> ARM: tegra: unify+move {board,sys_proto}.h to <mach/> ARM: tegra: use consistently named include guards ARM: tegra: delete unused headers ARM: tegra: move emc.h ARM: tegra: move sdram_param.h ARM: tegra: move sysctr.h ARM: tegra: remove pmu.h ARM: tegra: move powergate.h to <mach/> ARM: tegra: add SoC-specific include directory ARM: tegra: fix bug in Tegra20 flow.h ARM: tegra: move flow.h nyan-big: remove direct MC register access ARM: tegra: move mc.h ARM: tegra: move SDIOCFG_DRV* to pinmux.h ARM: tegra: remove tegra_get_chip() ARM: tegra: remove get_num_cpus() ARM: tegra: remove gp_padctrl.h ARM: tegra: remove tegra_get_sku_info() ARM: tegra: move EMC code to tegra20/ directory ARM: tegra: move PLLX configuration into SoC directories ARM: tegra: remove tegra_get_chip_sku() ARM: tegra: move custom pinmux.h to <mach/> ARM: tegra: add pinmux APIs to replace funcmux ARM: tegra: provide API for SPL code to init UART ARM: tegra: lay groundwork for board hook cleanup ARM: tegra: convert boards to new hooks ARM: tegra: remove unused includes ARM: tegra: move SPL-specific GPIO device to spl.c ARM: tegra: convert pin_mux_*() to new hooks tegra: keyboard: move pinmux setup to board files video: tegra: move pinmux setup to board files i2c: tegra: move pinmux setup to board files ARM: tegra: remove funcmux API ARM: tegra: don't access Boot Info Table from board code ARM: tegra: clean up board include statements ARM: tegra: unify+move tegra.h to mach-tegra/ ARM: tegra: move clock headers
arch/arm/dts/tegra114.dtsi | 4 + arch/arm/dts/tegra124-nyan-big.dts | 10 +- arch/arm/dts/tegra124-nyan.dtsi | 4 +- arch/arm/dts/tegra20-colibri.dts | 2 +- arch/arm/dts/tegra20-harmony.dts | 4 +- arch/arm/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/dts/tegra20-paz00.dts | 2 +- arch/arm/dts/tegra20-plutux.dts | 2 +- arch/arm/dts/tegra20-seaboard.dts | 4 +- arch/arm/dts/tegra20-tec.dts | 2 +- arch/arm/dts/tegra20-trimslice.dts | 4 +- arch/arm/dts/tegra20-ventana.dts | 2 +- arch/arm/dts/tegra20-whistler.dts | 2 +- arch/arm/dts/tegra20.dtsi | 4 + arch/arm/dts/tegra210-e2220-1170.dts | 16 +- arch/arm/dts/tegra210-p2371-0000.dts | 16 +- arch/arm/dts/tegra210-p2371-2180.dts | 20 +- arch/arm/dts/tegra210-p2571.dts | 48 ++-- arch/arm/dts/tegra210.dtsi | 56 ++-- arch/arm/dts/tegra30.dtsi | 4 + arch/arm/include/asm/arch-tegra/ap.h | 69 ----- arch/arm/include/asm/arch-tegra/board.h | 34 --- arch/arm/include/asm/arch-tegra/funcmux.h | 29 -- arch/arm/include/asm/arch-tegra/gp_padctrl.h | 26 -- arch/arm/include/asm/arch-tegra/tegra.h | 104 ------- arch/arm/include/asm/arch-tegra/timer.h | 15 - arch/arm/include/asm/arch-tegra/uart.h | 31 --- arch/arm/include/asm/arch-tegra114/funcmux.h | 21 -- arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 73 ----- arch/arm/include/asm/arch-tegra114/gpio.h | 20 -- arch/arm/include/asm/arch-tegra114/pmu.h | 13 - arch/arm/include/asm/arch-tegra114/powergate.h | 6 - arch/arm/include/asm/arch-tegra114/tegra.h | 25 -- arch/arm/include/asm/arch-tegra124/ahb.h | 91 ------- arch/arm/include/asm/arch-tegra124/display.h | 58 ---- arch/arm/include/asm/arch-tegra124/funcmux.h | 23 -- arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 74 ----- arch/arm/include/asm/arch-tegra124/gpio.h | 303 --------------------- arch/arm/include/asm/arch-tegra124/pmu.h | 14 - arch/arm/include/asm/arch-tegra124/powergate.h | 6 - arch/arm/include/asm/arch-tegra124/pwm.h | 14 - arch/arm/include/asm/arch-tegra124/sysctr.h | 26 -- arch/arm/include/asm/arch-tegra124/tegra.h | 30 -- arch/arm/include/asm/arch-tegra20/display.h | 29 -- arch/arm/include/asm/arch-tegra20/funcmux.h | 52 ---- arch/arm/include/asm/arch-tegra20/gpio.h | 263 ------------------ arch/arm/include/asm/arch-tegra20/pmu.h | 14 - arch/arm/include/asm/arch-tegra20/powergate.h | 6 - arch/arm/include/asm/arch-tegra20/pwm.h | 14 - arch/arm/include/asm/arch-tegra20/tegra.h | 22 -- arch/arm/include/asm/arch-tegra210/ahb.h | 91 ------- arch/arm/include/asm/arch-tegra210/funcmux.h | 23 -- arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ----- arch/arm/include/asm/arch-tegra210/gpio.h | 303 --------------------- arch/arm/include/asm/arch-tegra210/pmu.h | 14 - arch/arm/include/asm/arch-tegra210/powergate.h | 12 - arch/arm/include/asm/arch-tegra210/sysctr.h | 26 -- arch/arm/include/asm/arch-tegra210/tegra.h | 32 --- arch/arm/include/asm/arch-tegra30/funcmux.h | 21 -- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 55 ---- arch/arm/include/asm/arch-tegra30/gpio.h | 294 -------------------- arch/arm/include/asm/arch-tegra30/pmu.h | 13 - arch/arm/include/asm/arch-tegra30/powergate.h | 6 - arch/arm/include/asm/arch-tegra30/tegra.h | 21 -- arch/arm/include/asm/gpio.h | 2 +- arch/arm/mach-tegra/Kconfig | 5 + arch/arm/mach-tegra/Makefile | 5 +- arch/arm/mach-tegra/ap.c | 117 +------- .../asm/arch-tegra => mach-tegra}/apb_misc.h | 5 +- arch/arm/mach-tegra/board.c | 138 +--------- arch/arm/mach-tegra/board2.c | 155 +++-------- arch/arm/mach-tegra/cache.c | 24 +- arch/arm/mach-tegra/clock.c | 12 +- arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- arch/arm/mach-tegra/config.mk | 13 + arch/arm/mach-tegra/cpu.c | 185 ++----------- arch/arm/mach-tegra/cpu.h | 37 +-- arch/arm/mach-tegra/emc.c | 38 --- arch/arm/mach-tegra/gpu.c | 11 +- .../{include/asm/arch-tegra => mach-tegra}/gpu.h | 8 +- arch/arm/mach-tegra/i2c_early.c | 29 ++ .../include/mach/board.h} | 21 +- arch/arm/mach-tegra/include/mach/board_init.h | 15 + .../include/mach}/clk_rst.h | 89 +----- .../include/mach/clock_common.h} | 10 +- .../include/mach/pinmux_common.h} | 11 +- .../include/mach}/powergate.h | 12 +- arch/arm/mach-tegra/include/mach/spl_uart.h | 20 ++ .../include/mach/tegra_gpio.h} | 18 +- arch/arm/mach-tegra/include/mach/tegra_i2c.h | 25 ++ .../mmc.h => mach-tegra/include/mach/tegra_mmc.h} | 7 +- .../include/mach}/xusb-padctl.h | 4 +- arch/arm/mach-tegra/lowlevel_init.S | 3 +- arch/arm/mach-tegra/pinmux-common.c | 5 +- arch/arm/mach-tegra/pllx.h | 20 ++ .../{include/asm/arch-tegra => mach-tegra}/pmc.h | 25 +- arch/arm/mach-tegra/powergate.c | 8 +- .../{include/asm/arch-tegra => mach-tegra}/scu.h | 8 +- arch/arm/mach-tegra/spl.c | 26 +- arch/arm/mach-tegra/spl_uart.c | 40 +++ .../asm/arch-tegra114 => mach-tegra}/sysctr.h | 8 +- arch/arm/mach-tegra/tegra.h | 76 ++++++ arch/arm/mach-tegra/tegra114/Makefile | 5 +- arch/arm/mach-tegra/tegra114/clock.c | 11 +- arch/arm/mach-tegra/tegra114/cpu.c | 14 +- arch/arm/mach-tegra/tegra114/funcmux.c | 57 ---- .../tegra114/include/mach}/clock-tables.h | 8 +- .../tegra114/include/mach}/clock.h | 10 +- .../tegra114/include/mach}/pinmux.h | 18 +- .../tegra114/include/soc}/flow.h | 8 +- .../tegra114/include/soc}/mc.h | 2 +- arch/arm/mach-tegra/tegra114/pinmux.c | 22 +- arch/arm/mach-tegra/tegra114/pllx.c | 33 +++ arch/arm/mach-tegra/tegra124/Makefile | 4 +- arch/arm/mach-tegra/tegra124/clock.c | 11 +- arch/arm/mach-tegra/tegra124/cpu.c | 16 +- arch/arm/mach-tegra/tegra124/funcmux.c | 71 ----- .../tegra124/include/mach}/clock-tables.h | 8 +- .../tegra124/include/mach}/clock.h | 10 +- .../tegra124/include/mach}/pinmux.h | 19 +- .../tegra124/include/soc}/flow.h | 14 +- .../tegra124/include/soc}/mc.h | 3 +- arch/arm/mach-tegra/tegra124/pinmux.c | 34 ++- arch/arm/mach-tegra/tegra124/pllx.c | 33 +++ arch/arm/mach-tegra/tegra124/psci.c | 10 +- arch/arm/mach-tegra/tegra20/Makefile | 8 +- arch/arm/mach-tegra/tegra20/clock.c | 9 +- arch/arm/mach-tegra/tegra20/cpu.c | 6 +- arch/arm/mach-tegra/tegra20/crypto.h | 6 +- arch/arm/mach-tegra/tegra20/display.c | 16 -- arch/arm/mach-tegra/tegra20/emc.c | 40 ++- arch/arm/mach-tegra/{ => tegra20}/emc.h | 5 +- .../emc.h => mach-tegra/tegra20/emc_priv.h} | 17 +- arch/arm/mach-tegra/tegra20/funcmux.c | 298 -------------------- .../asm/arch-tegra => mach-tegra/tegra20}/fuse.h | 8 +- .../tegra20}/gp_padctrl.h | 13 +- .../tegra20/include/mach}/clock-tables.h | 8 +- .../tegra20/include/mach}/clock.h | 5 +- .../tegra20/include/mach}/pinmux.h | 32 ++- .../tegra20/include/soc}/flow.h | 7 +- .../tegra20/include/soc}/mc.h | 2 +- arch/arm/mach-tegra/tegra20/pinmux.c | 211 +++++++++++++- arch/arm/mach-tegra/tegra20/pllx.c | 56 ++++ arch/arm/mach-tegra/tegra20/pmu.c | 23 +- .../tegra20}/sdram_param.h | 6 +- arch/arm/mach-tegra/tegra20/sku.c | 44 +++ arch/arm/mach-tegra/tegra20/sku.h | 12 + arch/arm/mach-tegra/tegra20/warmboot.c | 50 ++-- .../arch-tegra => mach-tegra/tegra20}/warmboot.h | 7 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 21 +- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 10 +- arch/arm/mach-tegra/tegra210/Makefile | 4 +- arch/arm/mach-tegra/tegra210/clock.c | 11 +- arch/arm/mach-tegra/tegra210/funcmux.c | 40 --- .../tegra210/include/mach}/clock-tables.h | 8 +- .../tegra210/include/mach}/clock.h | 11 +- .../tegra210/include/mach}/pinmux.h | 16 +- .../tegra210/include/soc}/flow.h | 22 +- .../tegra210/include/soc}/mc.h | 5 +- arch/arm/mach-tegra/tegra210/pinmux.c | 4 +- arch/arm/mach-tegra/tegra210/pllx.c | 33 +++ arch/arm/mach-tegra/tegra210/xusb-padctl.c | 9 +- arch/arm/mach-tegra/tegra30/Makefile | 5 +- arch/arm/mach-tegra/tegra30/clock.c | 9 +- arch/arm/mach-tegra/tegra30/cpu.c | 29 +- arch/arm/mach-tegra/tegra30/funcmux.c | 51 ---- .../tegra30/include/mach}/clock-tables.h | 8 +- .../tegra30/include/mach}/clock.h | 10 +- .../tegra30/include/mach}/pinmux.h | 18 +- .../tegra30/include/soc}/flow.h | 8 +- .../tegra30/include/soc}/mc.h | 2 +- arch/arm/mach-tegra/tegra30/pinmux.c | 16 +- arch/arm/mach-tegra/tegra30/pllx.c | 34 +++ arch/arm/mach-tegra/xusb-padctl-common.c | 6 +- arch/arm/mach-tegra/xusb-padctl-common.h | 9 +- arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 +- board/avionic-design/common/tamonten-ng.c | 53 ++-- board/avionic-design/common/tamonten.c | 50 ++-- board/compal/paz00/paz00.c | 41 +-- board/compulab/trimslice/trimslice.c | 38 +-- board/nvidia/cardhu/cardhu.c | 47 ++-- board/nvidia/dalmore/dalmore.c | 42 ++- board/nvidia/e2220-1170/e2220-1170.c | 42 ++- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 122 ++++----- board/nvidia/harmony/harmony.c | 54 ++-- board/nvidia/jetson-tk1/jetson-tk1.c | 29 +- board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 106 +++---- board/nvidia/nyan-big/nyan-big.c | 48 ++-- board/nvidia/nyan-big/pinmux-config-nyan-big.h | 98 +++---- board/nvidia/p2371-0000/p2371-0000.c | 42 ++- board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 104 +++---- board/nvidia/p2371-2180/p2371-2180.c | 42 ++- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 126 ++++----- board/nvidia/p2571/p2571.c | 52 ++-- board/nvidia/p2571/pinmux-config-p2571.h | 54 ++-- board/nvidia/seaboard/seaboard.c | 55 ++-- board/nvidia/venice2/as3722_init.c | 21 +- board/nvidia/venice2/pinmux-config-venice2.h | 120 ++++---- board/nvidia/venice2/venice2.c | 22 +- board/nvidia/whistler/whistler.c | 78 +++--- board/toradex/apalis_t30/apalis_t30.c | 32 +-- board/toradex/colibri_t20/colibri_t20.c | 144 ++++------ board/toradex/colibri_t30/colibri_t30.c | 44 ++- drivers/gpio/Kconfig | 8 + drivers/gpio/tegra_gpio.c | 11 +- drivers/gpio/tegra_gpio_priv.h | 76 ++++++ drivers/i2c/tegra_i2c.c | 34 +-- .../tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h | 24 +- drivers/input/tegra-kbc.c | 10 +- drivers/mmc/tegra_mmc.c | 43 ++- .../tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h | 13 +- drivers/mtd/nand/tegra_nand.c | 7 +- drivers/pci/pci_tegra.c | 9 +- drivers/pwm/tegra_pwm.c | 5 +- .../pwm.h => drivers/pwm/tegra_pwm_priv.h | 9 +- drivers/spi/tegra114_spi.c | 6 +- drivers/spi/tegra20_sflash.c | 8 +- drivers/spi/tegra20_slink.c | 6 +- drivers/spi/tegra210_qspi.c | 6 +- .../usb.h => drivers/usb/host/ehci-tegra-priv.h | 11 +- drivers/usb/host/ehci-tegra.c | 9 +- drivers/video/tegra.c | 14 +- drivers/video/tegra124/display.c | 6 +- drivers/video/tegra124/dp.c | 4 +- drivers/video/tegra124/sor.c | 6 +- .../arch-tegra/dc.h => drivers/video/tegra_dc.h | 30 +- include/configs/apalis_t30.h | 7 +- include/configs/cardhu.h | 6 +- include/configs/colibri_t20.h | 6 +- include/configs/colibri_t30.h | 7 +- include/configs/dalmore.h | 6 +- include/configs/e2220-1170.h | 5 +- include/configs/harmony.h | 12 +- include/configs/jetson-tk1.h | 6 +- include/configs/nyan-big.h | 6 +- include/configs/p2371-0000.h | 5 +- include/configs/p2371-2180.h | 5 +- include/configs/p2571.h | 6 +- include/configs/paz00.h | 6 +- include/configs/seaboard.h | 8 +- include/configs/tec-ng.h | 5 +- include/configs/tec.h | 6 +- include/configs/tegra-common.h | 25 +- include/configs/trimslice.h | 7 +- include/configs/venice2.h | 6 +- include/configs/whistler.h | 7 +- 246 files changed, 2460 insertions(+), 5400 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/ap.h delete mode 100644 arch/arm/include/asm/arch-tegra/board.h delete mode 100644 arch/arm/include/asm/arch-tegra/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra/timer.h delete mode 100644 arch/arm/include/asm/arch-tegra/uart.h delete mode 100644 arch/arm/include/asm/arch-tegra114/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra114/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra114/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra114/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h delete mode 100644 arch/arm/include/asm/arch-tegra124/display.h delete mode 100644 arch/arm/include/asm/arch-tegra124/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pwm.h delete mode 100644 arch/arm/include/asm/arch-tegra124/sysctr.h delete mode 100644 arch/arm/include/asm/arch-tegra124/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h delete mode 100644 arch/arm/include/asm/arch-tegra20/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra20/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pwm.h delete mode 100644 arch/arm/include/asm/arch-tegra20/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h delete mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h delete mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra30/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra30/tegra.h rename arch/arm/{include/asm/arch-tegra => mach-tegra}/apb_misc.h (79%) create mode 100644 arch/arm/mach-tegra/config.mk delete mode 100644 arch/arm/mach-tegra/emc.c rename arch/arm/{include/asm/arch-tegra => mach-tegra}/gpu.h (80%) create mode 100644 arch/arm/mach-tegra/i2c_early.c rename arch/arm/{include/asm/arch-tegra/sys_proto.h => mach-tegra/include/mach/board.h} (63%) create mode 100644 arch/arm/mach-tegra/include/mach/board_init.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/clk_rst.h (85%) rename arch/arm/{include/asm/arch-tegra/clock.h => mach-tegra/include/mach/clock_common.h} (98%) rename arch/arm/{include/asm/arch-tegra/pinmux.h => mach-tegra/include/mach/pinmux_common.h} (97%) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/powergate.h (81%) create mode 100644 arch/arm/mach-tegra/include/mach/spl_uart.h rename arch/arm/{include/asm/arch-tegra/gpio.h => mach-tegra/include/mach/tegra_gpio.h} (52%) create mode 100644 arch/arm/mach-tegra/include/mach/tegra_i2c.h rename arch/arm/{include/asm/arch-tegra/mmc.h => mach-tegra/include/mach/tegra_mmc.h} (50%) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/xusb-padctl.h (92%) create mode 100644 arch/arm/mach-tegra/pllx.h rename arch/arm/{include/asm/arch-tegra => mach-tegra}/pmc.h (96%) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/scu.h (91%) create mode 100644 arch/arm/mach-tegra/spl_uart.c rename arch/arm/{include/asm/arch-tegra114 => mach-tegra}/sysctr.h (81%) create mode 100644 arch/arm/mach-tegra/tegra.h delete mode 100644 arch/arm/mach-tegra/tegra114/funcmux.c rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock.h (61%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/pinmux.h (95%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra114/include/soc}/flow.h (67%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/soc}/mc.h (97%) create mode 100644 arch/arm/mach-tegra/tegra114/pllx.c delete mode 100644 arch/arm/mach-tegra/tegra124/funcmux.c rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock.h (85%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/pinmux.h (95%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/flow.h (82%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/mc.h (95%) create mode 100644 arch/arm/mach-tegra/tegra124/pllx.c delete mode 100644 arch/arm/mach-tegra/tegra20/display.c rename arch/arm/mach-tegra/{ => tegra20}/emc.h (62%) rename arch/arm/{include/asm/arch-tegra20/emc.h => mach-tegra/tegra20/emc_priv.h} (83%) delete mode 100644 arch/arm/mach-tegra/tegra20/funcmux.c rename arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/fuse.h (83%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/gp_padctrl.h (88%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock-tables.h (95%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock.h (77%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/pinmux.h (81%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/flow.h (71%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/mc.h (97%) create mode 100644 arch/arm/mach-tegra/tegra20/pllx.c rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/sdram_param.h (96%) create mode 100644 arch/arm/mach-tegra/tegra20/sku.c create mode 100644 arch/arm/mach-tegra/tegra20/sku.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/warmboot.h (95%) delete mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock.h (70%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/pinmux.h (96%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/flow.h (62%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/mc.h (93%) create mode 100644 arch/arm/mach-tegra/tegra210/pllx.c delete mode 100644 arch/arm/mach-tegra/tegra30/funcmux.c rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock.h (58%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/pinmux.h (96%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra30/include/soc}/flow.h (67%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/soc}/mc.h (97%) create mode 100644 arch/arm/mach-tegra/tegra30/pllx.c create mode 100644 drivers/gpio/tegra_gpio_priv.h rename arch/arm/include/asm/arch-tegra/tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h (87%) rename arch/arm/include/asm/arch-tegra/tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h (96%) rename arch/arm/include/asm/arch-tegra/pwm.h => drivers/pwm/tegra_pwm_priv.h (81%) rename arch/arm/include/asm/arch-tegra/usb.h => drivers/usb/host/ehci-tegra-priv.h (97%) rename arch/arm/include/asm/arch-tegra/dc.h => drivers/video/tegra_dc.h (94%)
From: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra*/*.h have accumulated a fair number of unused definitions. This patch aims to delete them all.
While working on this, I noticed a few redundancies and fixed them. No doubt other redundancies still exist simply because I wasn't looking hard for them.
A few definitions were moved between files to allow deletion of headers.
Later changes will attempt to: - Reduce the number of headers in the include directory. - Move headers into arch/arm/mach-tegra/*, or into the same directory as the drivers they serve. - Eliminate remaining duplication. - Refactor the headers to allow addition of future SoC support, where those SoCs don't share many of the definitions currently located in common headers.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/ap.h | 69 --------------------- arch/arm/include/asm/arch-tegra/clk_rst.h | 81 +++---------------------- arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h | 6 +- arch/arm/include/asm/arch-tegra/gpio.h | 4 +- arch/arm/include/asm/arch-tegra/pmc.h | 19 +----- arch/arm/include/asm/arch-tegra/pwm.h | 3 +- arch/arm/include/asm/arch-tegra/sys_proto.h | 4 +- arch/arm/include/asm/arch-tegra/tegra.h | 26 ++------ arch/arm/include/asm/arch-tegra/tegra_i2c.h | 11 +--- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 4 +- arch/arm/include/asm/arch-tegra/timer.h | 15 ----- arch/arm/include/asm/arch-tegra/uart.h | 31 ---------- arch/arm/include/asm/arch-tegra/usb.h | 5 +- arch/arm/include/asm/arch-tegra/warmboot.h | 3 +- arch/arm/include/asm/arch-tegra124/ahb.h | 91 ---------------------------- arch/arm/include/asm/arch-tegra124/display.h | 58 ------------------ arch/arm/include/asm/arch-tegra124/flow.h | 8 +-- arch/arm/include/asm/arch-tegra124/mc.h | 3 +- arch/arm/include/asm/arch-tegra124/tegra.h | 5 +- arch/arm/include/asm/arch-tegra20/tegra.h | 4 +- arch/arm/include/asm/arch-tegra210/ahb.h | 13 +--- arch/arm/include/asm/arch-tegra210/clock.h | 3 +- arch/arm/include/asm/arch-tegra210/flow.h | 16 +---- arch/arm/include/asm/arch-tegra210/mc.h | 5 +- arch/arm/include/asm/arch-tegra210/tegra.h | 5 +- arch/arm/include/asm/arch-tegra30/tegra.h | 4 +- arch/arm/mach-tegra/ap.c | 10 +-- arch/arm/mach-tegra/board.c | 11 ++-- arch/arm/mach-tegra/board2.c | 6 +- arch/arm/mach-tegra/cache.c | 4 +- arch/arm/mach-tegra/clock.c | 4 +- arch/arm/mach-tegra/cpu.h | 34 +++++++---- arch/arm/mach-tegra/emc.c | 5 +- arch/arm/mach-tegra/tegra114/clock.c | 3 +- arch/arm/mach-tegra/tegra124/clock.c | 3 +- arch/arm/mach-tegra/tegra124/cpu.c | 4 +- arch/arm/mach-tegra/tegra124/psci.c | 3 +- arch/arm/mach-tegra/tegra20/clock.c | 3 +- arch/arm/mach-tegra/tegra20/display.c | 5 +- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 6 +- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 6 +- arch/arm/mach-tegra/tegra210/clock.c | 3 +- arch/arm/mach-tegra/tegra30/clock.c | 3 +- board/avionic-design/common/tamonten.c | 9 ++- board/toradex/apalis_t30/apalis_t30.c | 6 +- board/toradex/colibri_t20/colibri_t20.c | 4 +- board/toradex/colibri_t30/colibri_t30.c | 6 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/input/tegra-kbc.c | 5 +- drivers/video/tegra.c | 3 +- include/configs/tegra-common.h | 10 ++- 55 files changed, 117 insertions(+), 553 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/ap.h delete mode 100644 arch/arm/include/asm/arch-tegra/timer.h delete mode 100644 arch/arm/include/asm/arch-tegra/uart.h delete mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h delete mode 100644 arch/arm/include/asm/arch-tegra124/display.h
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h deleted file mode 100644 index 8c2586c6f548..000000000000 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <asm/types.h> - -/* Stabilization delays, in usec */ -#define PLL_STABILIZATION_DELAY (300) -#define IO_STABILIZATION_DELAY (1000) - -#define PLLX_ENABLED (1 << 30) -#define CCLK_BURST_POLICY 0x20008888 -#define SUPER_CCLK_DIVIDER 0x80000000 - -/* Calculate clock fractional divider value from ref and target frequencies */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) - -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - -/* AP base physical address of internal SRAM */ -#define NV_PA_BASE_SRAM 0x40000000 - -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) - -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) -#define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) - -/* This is the main entry into U-Boot, used by the Cortex-A9 */ -extern void _start(void); - -/** - * Works out the SOC/SKU type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_sku(void); - -/** - * Returns the pure SOC (chip ID) from the HIDREV register - * - * @return SOC ID - see CHIPID_TEGRAxx... - */ -int tegra_get_chip(void); - -/** - * Returns the SKU ID from the sku_info register - * - * @return SKU ID - see SKU_ID_Txx... - */ -int tegra_get_sku_info(void); - -/* Do any chip-specific cache config */ -void config_cache(void); - -#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) -bool tegra_cpu_is_non_secure(void); -#endif diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index ee9436e2e53d..304e1148cdcd 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,13 +22,6 @@ struct clk_pll_simple { uint pll_misc; /* other misc things */ };
-struct clk_pllm { - uint pllm_base; /* the control register */ - uint pllm_out; /* output control */ - uint pllm_misc1; /* misc1 */ - uint pllm_misc2; /* misc2 */ -}; - /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ struct clk_set_clr { uint set; @@ -246,9 +239,6 @@ struct clk_rst_ctlr {
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
-#define PLL_LOCK_SHIFT 27 -#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) - /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) @@ -291,20 +281,7 @@ enum { #define PLLP_OUT4_RSTN_EN (0 << 16) #define PLLP_OUT4_CLKEN (1 << 17)
-/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ -#define OSC_XOE_SHIFT 0 -#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) -#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) #define OSC_XOBP_SHIFT 1 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) #define OSC_XOFS_SHIFT 4 @@ -332,65 +309,31 @@ enum { #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ -#define SCLK_SYS_STATE_SHIFT 28U -#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) -enum { - SCLK_SYS_STATE_STDBY, - SCLK_SYS_STATE_IDLE, - SCLK_SYS_STATE_RUN, - SCLK_SYS_STATE_IRQ = 4U, - SCLK_SYS_STATE_FIQ = 8U, -}; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_IDLE 1 +#define SCLK_SYS_STATE_RUN 2
#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 -#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 -#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 -#define SCLK_SWAKEUP_RUN_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
-#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -enum { - SCLK_SOURCE_CLKM, - SCLK_SOURCE_PLLC_OUT1, - SCLK_SOURCE_PLLP_OUT4, - SCLK_SOURCE_PLLP_OUT3, - SCLK_SOURCE_PLLP_OUT2, - SCLK_SOURCE_CLKD, - SCLK_SOURCE_CLKS, - SCLK_SOURCE_PLLM_OUT1, -}; +#define SCLK_SOURCE_CLKM 0 +#define SCLK_SOURCE_PLLP_OUT4 2 + #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ -#define SUPER_SCLK_ENB_SHIFT 31U #define SUPER_SCLK_ENB_MASK (1U << 31) -#define SUPER_SCLK_DIVIDEND_SHIFT 8 -#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) -#define SUPER_SCLK_DIVISOR_SHIFT 0 -#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 -#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 -#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 -#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_APB_RATE_SHIFT 0 -#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ #define CLR_CPURESET0 (1 << 0) @@ -419,14 +362,6 @@ enum { #define CLR_CPU2_CLK_STP (1 << 10) #define CLR_CPU3_CLK_STP (1 << 11)
-/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ -#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) - -/* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) - /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ #define PLL_ACTIVE_POWERDOWN (1 << 12) #define PLL_ENABLE_POWERDOWN (1 << 14) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index e56031d1afa7..a20832b7f35f 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -134,7 +135,6 @@ enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, crc_rst_de = 1 << 4, /* What is de? */ - crc_rst_watchdog = 1 << 8, crc_rst_debug = 1 << 12, };
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h index 695f3e6fba82..854966a30f9e 100644 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,8 +8,6 @@ #ifndef _TEGRA_GP_PADCTRL_H_ #define _TEGRA_GP_PADCTRL_H_
-#define GP_HIDREV 0x804 - /* bit fields definitions for APB_MISC_GP_HIDREV register */ #define HIDREV_CHIPID_SHIFT 8 #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index daf5698e6625..363d16c486d1 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2011, Google Inc. All rights reserved. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * * SPDX-License-Identifier: GPL-2.0+ */
@@ -8,8 +10,6 @@
#define TEGRA_GPIOS_PER_PORT 8 #define TEGRA_PORTS_PER_BANK 4 -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
#define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 66c08797656c..9c9b67448985 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -294,7 +294,6 @@ struct pmc_ctlr { #define CRAIL 0 #define CE0 14 #define C0NC 15 -#define SOR 17
#define PMC_XOFS_SHIFT 1 #define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) @@ -319,20 +318,6 @@ struct pmc_ctlr { #define MULT_16 4 #endif
-#define AMAP_WRITE_SHIFT 20 -#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) - -/* SEC_DISABLE_0, 0x04 */ -#define SEC_DISABLE_WRITE0_ON (1 << 4) -#define SEC_DISABLE_READ0_ON (1 << 5) -#define SEC_DISABLE_WRITE1_ON (1 << 6) -#define SEC_DISABLE_READ1_ON (1 << 7) -#define SEC_DISABLE_WRITE2_ON (1 << 8) -#define SEC_DISABLE_READ2_ON (1 << 9) -#define SEC_DISABLE_WRITE3_ON (1 << 10) -#define SEC_DISABLE_READ3_ON (1 << 11) -#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) - /* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ #define PWRGATE_TOGGLE_PARTID_CRAIL 0 #define PWRGATE_TOGGLE_PARTID_TD 1 diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h index 5a2d9f3a9c1e..b69c0b041f40 100644 --- a/arch/arm/include/asm/arch-tegra/pwm.h +++ b/arch/arm/include/asm/arch-tegra/pwm.h @@ -2,6 +2,7 @@ * Tegra pulse width frequency modulator definitions * * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,8 +16,6 @@ struct pwm_ctlr { uint reserved[3]; /* Space space */ };
-#define PWM_NUM_CHANNELS 4 - /* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ #define PWM_ENABLE_SHIFT 31 #define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h index b64f9d813b0e..8c2f94b578fe 100644 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra/sys_proto.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -8,8 +8,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_
-void invalidate_dcache(void); - /** * tegra_board_id() - Get the board iD * diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3c09bb..4051a7d26630 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -8,6 +8,8 @@ #ifndef _TEGRA_H_ #define _TEGRA_H_
+/* AP base physical address of internal SRAM */ +#define NV_PA_BASE_SRAM 0x40000000 #define NV_PA_ARM_PERIPHBASE 0x50040000 #define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 @@ -22,17 +24,8 @@ #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) -#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) -#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) -#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) -#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) -#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) -#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ defined(CONFIG_TEGRA114) @@ -40,19 +33,11 @@ #else #define NV_PA_CSITE_BASE 0x70800000 #endif -#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE -#define LOW_LEVEL_SRAM_STACK 0x4000FFFC -#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) -#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) +#define PG_UP_TAG_0 0x0 #define PG_UP_TAG_AVP 0xAAAAAAAA
#ifndef __ASSEMBLY__ -struct timerus { - unsigned int cntr_1us; -}; - /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define NV_WB_RUN_ADDRESS 0x40020000
@@ -96,9 +81,8 @@ enum { TEGRA_SOC_CNT, TEGRA_SOC_UNKNOWN = -1, }; +#endif
-#else /* __ASSEMBLY__ */ #define PRM_RSTCTRL NV_PA_PMC_BASE -#endif
#endif /* TEGRA_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 341df74d777d..eb83af89f7f5 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -1,7 +1,7 @@ /* * NVIDIA Tegra I2C controller * - * Copyright 2010-2011 NVIDIA Corporation + * Copyright 2010-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -18,11 +18,7 @@ enum {
enum i2c_transaction_flags { I2C_IS_WRITE = 0x1, /* for I2C write operation */ - I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ - I2C_USE_REPEATED_START = 0x4, /* for repeat start */ - I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ - I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ - I2C_NO_STOP = 0x20, + I2C_USE_REPEATED_START = 0x2, /* for repeat start */ };
/* Contians the I2C transaction details */ @@ -38,7 +34,6 @@ struct i2c_trans_info { * the slave device. */ u8 *buf; - int is_10bit_address; };
struct i2c_control { @@ -142,8 +137,6 @@ struct i2c_ctlr { #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
/* I2C_CLK_DIVISOR_REGISTER */ -#define CLK_DIV_STD_FAST_MODE 0x19 -#define CLK_DIV_HS_MODE 1 #define CLK_MULT_STD_FAST_MODE 8
/** diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a20bdaa61872..9b371add1de4 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -1,7 +1,7 @@ /* + * Copyright (C) 2011-2016 NVIDIA Corporation * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang mk7.kang@samsung.com - * Portions Copyright (C) 2011-2012 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,7 +15,6 @@ /* for mmc_config definition */ #include <mmc.h>
-#ifndef __ASSEMBLY__ struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ @@ -145,5 +144,4 @@ struct mmc_host {
void pad_init_mmc(struct mmc_host *host);
-#endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/timer.h b/arch/arm/include/asm/arch-tegra/timer.h deleted file mode 100644 index 5d5664115f41..000000000000 --- a/arch/arm/include/asm/arch-tegra/timer.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 timer functions */ - -#ifndef _TEGRA_TIMER_H -#define _TEGRA_TIMER_H - -/* returns the current monotonic timer value in microseconds */ -unsigned long timer_get_us(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/uart.h b/arch/arm/include/asm/arch-tegra/uart.h deleted file mode 100644 index fef7f8db3f98..000000000000 --- a/arch/arm/include/asm/arch-tegra/uart.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _UART_H_ -#define _UART_H_ - -/* UART registers */ -struct uart_ctlr { - uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ - uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ - uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ - uint uart_lcr; /* UART_LCR_0, offset 0C */ - uint uart_mcr; /* UART_MCR_0, offset 10 */ - uint uart_lsr; /* UART_LSR_0, offset 14 */ - uint uart_msr; /* UART_MSR_0, offset 18 */ - uint uart_spr; /* UART_SPR_0, offset 1C */ - uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ - uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ - uint uart_asr; /* UART_ASR_0, offset 3C */ -}; - -#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 -#define NV_DEFAULT_DEBUG_BAUD 115200 - -#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ - -#endif /* UART_H */ diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index f400c01a3954..24198e4a33d0 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation + * Copyright (c) 2013-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -355,7 +355,4 @@ struct usb_ctlr { #define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) #define VBUS_B_SESS_VLD_SW_EN (1 << 11)
-/* Setup USB on the board */ -int usb_process_devicetree(const void *blob); - #endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index 2e66e0f23b9b..b6326c8f7b11 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -127,7 +127,6 @@ union scratch3_reg { int warmboot_save_sdram_params(void);
int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); void wb_start(void); /* Start of WB assembly code */ void wb_end(void); /* End of WB assembly code */
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h deleted file mode 100644 index 4e48c43bbf3f..000000000000 --- a/arch/arm/include/asm/arch-tegra124/ahb.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_AHB_H_ -#define _TEGRA124_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - -#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h deleted file mode 100644 index ca6644af345b..000000000000 --- a/arch/arm/include/asm/arch-tegra124/display.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -/** - * Register a new display based on device tree configuration. - * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. - * You should pass in the U-Boot address here, and check the contents of - * struct fdt_disp_config to see what was actually chosen. - * - * @param blob Device tree blob - * @param default_lcd_base Default address of LCD frame buffer - * @return 0 if ok, -1 on error (unsupported bits per pixel) - */ -int tegra_display_probe(const void *blob, void *default_lcd_base); - -/** - * Return the current display configuration - * - * @return pointer to display configuration, or NULL if there is no valid - * config - */ -struct fdt_disp_config *tegra_display_get_config(void); - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -int tegra_lcd_check_next_stage(const void *blob, int wait); - -/** - * Set up the maximum LCD size so we can size the frame buffer. - * - * @param blob fdt blob containing LCD information - */ -void tegra_lcd_early_init(const void *blob); - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 7818b1bd3455..3f70fb190527 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2013 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -35,14 +35,8 @@ struct flow_ctlr { };
/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) #define EVENT_MODE_STOP (2 << 29)
-/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - /* CPUn_CSR_0 */ #define CSR_ENABLE (1 << 0) #define CSR_IMMEDIATE_WAKE (1 << 3) diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index d97b2c87c631..190dd9754ef1 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -66,7 +66,6 @@ struct mc_ctlr {
#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
-#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
#endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h index db3d8379203b..f009925611c6 100644 --- a/arch/arm/include/asm/arch-tegra124/tegra.h +++ b/arch/arm/include/asm/arch-tegra124/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -23,8 +23,5 @@ #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
#define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000
#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 22774abb936d..1cea245e4171 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,8 +13,6 @@
#include <asm/arch-tegra/tegra.h>
-#define TEGRA_USB1_BASE 0xC5000000 - #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
#define MAX_NUM_CPU 2 diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h index 3a37af417748..2e676a436e3d 100644 --- a/arch/arm/include/asm/arch-tegra210/ahb.h +++ b/arch/arm/include/asm/arch-tegra210/ahb.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -77,15 +77,4 @@ struct ahb_ctlr { u32 axicif_fastsync2_mcclk_to_cpuclk; };
-#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - #endif /* _TEGRA210_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h index 3501be2abbb4..54e70439952d 100644 --- a/arch/arm/include/asm/arch-tegra210/clock.h +++ b/arch/arm/include/asm/arch-tegra210/clock.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -20,7 +20,6 @@ #define PLLC_RESET 30 #define PLLC_IDDQ 27 #define PLLD_ENABLE_CLK 21 -#define PLLD_EN_LCKDET 28
int tegra_plle_enable(void);
diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h index e2301aee548f..e4ede6a81500 100644 --- a/arch/arm/include/asm/arch-tegra210/flow.h +++ b/arch/arm/include/asm/arch-tegra210/flow.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -28,18 +28,4 @@ struct flow_ctlr { u32 ram_repair; /* offset 0x40 */ };
-/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) -#define EVENT_MODE_STOP (2 << 29) - -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - -/* CPUn_CSR_0 */ -#define CSR_ENABLE (1 << 0) -#define CSR_IMMEDIATE_WAKE (1 << 3) -#define CSR_WAIT_WFI_SHIFT 8 - #endif /* _TEGRA210_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h index 77e9aa51f60f..dc910b9c7a0f 100644 --- a/arch/arm/include/asm/arch-tegra210/mc.h +++ b/arch/arm/include/asm/arch-tegra210/mc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016 NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -64,9 +64,6 @@ struct mc_ctlr { u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ };
-#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) - -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
#endif /* _TEGRA210_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h index 95c67fbb8e9f..17b9f6af3679 100644 --- a/arch/arm/include/asm/arch-tegra210/tegra.h +++ b/arch/arm/include/asm/arch-tegra210/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -25,8 +25,5 @@ #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
#define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000
#endif /* _TEGRA210_TEGRA_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index 280245e98e87..28f9741a1d76 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -12,8 +12,6 @@
#include <asm/arch-tegra/tegra.h>
-#define TEGRA_USB1_BASE 0x7D000000 - #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
#define MAX_NUM_CPU 4 diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a4fa00c9adae..336a7e08196d 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -1,9 +1,9 @@ /* -* (C) Copyright 2010-2015 -* NVIDIA Corporation <www.nvidia.com> -* + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * * SPDX-License-Identifier: GPL-2.0+ -*/ + */
/* Tegra AP (Application Processor) code */
@@ -12,13 +12,13 @@ #include <asm/io.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/mc.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/scu.h> #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> +#include "cpu.h"
int tegra_get_chip(void) { diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 3d1d26d13d13..098547ab1e88 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +14,6 @@ #include <asm/arch/funcmux.h> #include <asm/arch/mc.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> @@ -77,7 +76,7 @@ static phys_size_t query_sdram_size(void) emem_cfg = readl(&mc->mc_emem_cfg); #if defined(CONFIG_TEGRA20) debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); - size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); + size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE, emem_cfg * 1024); #else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); #ifndef CONFIG_PHYS_64BIT @@ -101,8 +100,8 @@ static phys_size_t query_sdram_size(void) * avoid using it. There's no reason we should need this * validation step anyway. */ - if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) - size_bytes = get_ram_size((void *)PHYS_SDRAM_1, + if (emem_cfg <= (0 - NV_PA_SDRAM_BASE) / (1024 * 1024)) + size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE, size_bytes); #endif } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 141d6e1cb555..33e346017a8b 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,12 +17,10 @@ #include <asm/arch/pinmux.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/uart.h> #include <asm/arch-tegra/warmboot.h> #include <asm/arch-tegra/gpu.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 6dad40325d2f..b93814fcb96b 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -8,8 +8,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h> +#include "cpu.h"
#ifndef CONFIG_ARM64 void config_cache(void) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index c50d56dc888b..80d6fccf2551 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,10 +11,8 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 3f38969a44f1..c0284ce03787 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -21,20 +21,12 @@ #error "Unknown Tegra chip!" #endif
-#define PLLX_ENABLED (1 << 30) #define CCLK_BURST_POLICY 0x20008888 #define SUPER_CCLK_DIVIDER 0x80000000
/* Calculate clock fractional divider value from ref and target frequencies */ #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
-/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - #define CORESIGHT_UNLOCK 0xC5ACCE55
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) @@ -53,10 +45,6 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ -#define SB_AA64_RESET_LOW 0x6000C230 -#define SB_AA64_RESET_HIGH 0x6000C234 - struct clk_pll_table { u16 n; u16 m; @@ -71,8 +59,28 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ int tegra_get_chip(void); +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ int tegra_get_sku_info(void); +/** + * Works out the SOC/SKU type used for clocks settings + * + * @return SOC type - see TEGRA_SOC... + */ int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); void pmic_enable_cpu_vdd(void); +/* Do any chip-specific cache config */ +void config_cache(void); +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +bool tegra_cpu_is_non_secure(void); +#endif diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 8c62f36a7b04..70aec7fc1b3d 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -1,19 +1,20 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> -#include "emc.h" #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/sys_proto.h> +#include "emc.h" +#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index e6ef873c8dc4..7a73e159a7cd 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 1e71146236e9..1219b6413844 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 0aca6583bacd..be31cb4ac881 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,14 +7,12 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/ahb.h> #include <asm/arch/clock.h> #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/ap.h> #include "../cpu.h"
/* Tegra124-specific CPU init code */ diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index 16d196508c6e..08225e32dbd4 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -1,6 +1,7 @@ /* * (C) Copyright 2015, Siemens AG * Author: Jan Kiszka jan.kiszka@siemens.com + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,8 +11,8 @@ #include <asm/psci.h> #include <asm/arch/flow.h> #include <asm/arch/powergate.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/pmc.h> +#include "../cpu.h"
static void park_cpu(void) { diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index cd9fb9a55340..0ff538830abd 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,7 +14,6 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 73be9a9cbd1f..52a476eb7d8a 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,5 +12,4 @@ #include <asm/arch/display.h> #include <asm/arch-tegra/dc.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h>
diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index ed2462ab0fa6..eab61b7cd2ab 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,7 +8,6 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index a774246a2779..0da704cd4f3c 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,9 +10,9 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra_i2c.h> #include <asm/arch-tegra/sys_proto.h> +#include "../cpu.h"
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */ diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5fdc4bbb5007..1013441d4265 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 - 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,12 +14,12 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include "crypto.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 27ce5f480f54..616358b657be 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 - 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -11,11 +11,11 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../cpu.h" #include "warmboot_avp.h"
#define DEBUG_RESET_CORESIGHT @@ -204,7 +204,7 @@ void wb_start(void)
reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | - SCLK_SYS_STATE_IDLE; + (SCLK_SYS_STATE_IDLE << SCLK_SYS_STATE_SHIFT); writel(reg, &clkrst->crc_sclk_brst_pol);
/* avp_resume: no return after the write */ diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 7b86acb15632..85892b023fad 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -12,9 +12,6 @@ #define TEGRA_DEV_H 1 #define TEGRA_DEV_U 2
-#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) -#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) - #define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) #define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
@@ -49,7 +46,6 @@ #define PLLM_OUT1_CLKEN_ENABLE (1 << 1) #define PLLM_OUT1_RATIO_VAL_8 (8 << 8)
-#define SCLK_SYS_STATE_IDLE (1 << 28) #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index f0052e7934a1..b025711acf09 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,7 +14,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 1f104f288e57..98289b8ac7a7 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h>
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 9c8677943ad3..981862ce1aff 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -1,8 +1,8 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011-2012 - * Avionic Design GmbH <www.avionic-design.de> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011-2012 + * Avionic Design GmbH <www.avionic-design.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,7 +18,6 @@ #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/uart.h>
#ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 3f56971a13b1..8fdee023ee8a 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -1,6 +1,7 @@ /* - * (C) Copyright 2014 - * Marcel Ziswiler marcel@ziswiler.com + * (C) Copyright 2014 + * Marcel Ziswiler marcel@ziswiler.com + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <common.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 879f25a5384b..b9f845a09b6a 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Lucas Stach + * Copyright (C) 2012 Lucas Stach + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 44b5beb92832..3902bff203d5 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -1,6 +1,7 @@ /* - * (C) Copyright 2014 - * Stefan Agner stefan@agner.ch + * (C) Copyright 2014 + * Stefan Agner stefan@agner.ch + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <common.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2fa07f9c57c4..0735ea0b2b12 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (c) 2010-2011 NVIDIA Corporation - * NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2010-2016 NVIDIA Corporation + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -292,7 +292,6 @@ static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, if (end_with_repeated_start) trans_info.flags |= I2C_USE_REPEATED_START; trans_info.num_bytes = len; - trans_info.is_10bit_address = 0;
error = send_recv_packets(i2c_bus, &trans_info); if (error) @@ -311,7 +310,6 @@ static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, trans_info.buf = data; trans_info.flags = 0; trans_info.num_bytes = len; - trans_info.is_10bit_address = 0;
error = send_recv_packets(i2c_bus, &trans_info); if (error) diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index c77f61076962..349d95804201 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,7 +16,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch-tegra/timer.h> #include <linux/input.h>
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 7fd10e6af35e..13b10645478e 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * * SPDX-License-Identifier: GPL-2.0+ */
@@ -17,7 +19,6 @@ #include <asm/arch/pinmux.h> #include <asm/arch/pwm.h> #include <asm/arch/display.h> -#include <asm/arch-tegra/timer.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index b07ee5645bb8..776394151661 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -84,7 +84,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRAM_BASE + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#ifndef CONFIG_ARM64 @@ -97,11 +97,9 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE NV_PA_SDRAM_BASE
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra*/*.h have accumulated a fair number of unused definitions. This patch aims to delete them all.
While working on this, I noticed a few redundancies and fixed them. No doubt other redundancies still exist simply because I wasn't looking hard for them.
A few definitions were moved between files to allow deletion of headers.
Later changes will attempt to:
- Reduce the number of headers in the include directory.
- Move headers into arch/arm/mach-tegra/*, or into the same directory as the drivers they serve.
- Eliminate remaining duplication.
- Refactor the headers to allow addition of future SoC support, where those SoCs don't share many of the definitions currently located in common headers.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/ap.h | 69 --------------------- arch/arm/include/asm/arch-tegra/clk_rst.h | 81 +++---------------------- arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h | 6 +- arch/arm/include/asm/arch-tegra/gpio.h | 4 +- arch/arm/include/asm/arch-tegra/pmc.h | 19 +----- arch/arm/include/asm/arch-tegra/pwm.h | 3 +- arch/arm/include/asm/arch-tegra/sys_proto.h | 4 +- arch/arm/include/asm/arch-tegra/tegra.h | 26 ++------ arch/arm/include/asm/arch-tegra/tegra_i2c.h | 11 +--- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 4 +- arch/arm/include/asm/arch-tegra/timer.h | 15 ----- arch/arm/include/asm/arch-tegra/uart.h | 31 ---------- arch/arm/include/asm/arch-tegra/usb.h | 5 +- arch/arm/include/asm/arch-tegra/warmboot.h | 3 +- arch/arm/include/asm/arch-tegra124/ahb.h | 91 ---------------------------- arch/arm/include/asm/arch-tegra124/display.h | 58 ------------------ arch/arm/include/asm/arch-tegra124/flow.h | 8 +-- arch/arm/include/asm/arch-tegra124/mc.h | 3 +- arch/arm/include/asm/arch-tegra124/tegra.h | 5 +- arch/arm/include/asm/arch-tegra20/tegra.h | 4 +- arch/arm/include/asm/arch-tegra210/ahb.h | 13 +--- arch/arm/include/asm/arch-tegra210/clock.h | 3 +- arch/arm/include/asm/arch-tegra210/flow.h | 16 +---- arch/arm/include/asm/arch-tegra210/mc.h | 5 +- arch/arm/include/asm/arch-tegra210/tegra.h | 5 +- arch/arm/include/asm/arch-tegra30/tegra.h | 4 +- arch/arm/mach-tegra/ap.c | 10 +-- arch/arm/mach-tegra/board.c | 11 ++-- arch/arm/mach-tegra/board2.c | 6 +- arch/arm/mach-tegra/cache.c | 4 +- arch/arm/mach-tegra/clock.c | 4 +- arch/arm/mach-tegra/cpu.h | 34 +++++++---- arch/arm/mach-tegra/emc.c | 5 +- arch/arm/mach-tegra/tegra114/clock.c | 3 +- arch/arm/mach-tegra/tegra124/clock.c | 3 +- arch/arm/mach-tegra/tegra124/cpu.c | 4 +- arch/arm/mach-tegra/tegra124/psci.c | 3 +- arch/arm/mach-tegra/tegra20/clock.c | 3 +- arch/arm/mach-tegra/tegra20/display.c | 5 +- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 6 +- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 6 +- arch/arm/mach-tegra/tegra210/clock.c | 3 +- arch/arm/mach-tegra/tegra30/clock.c | 3 +- board/avionic-design/common/tamonten.c | 9 ++- board/toradex/apalis_t30/apalis_t30.c | 6 +- board/toradex/colibri_t20/colibri_t20.c | 4 +- board/toradex/colibri_t30/colibri_t30.c | 6 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/input/tegra-kbc.c | 5 +- drivers/video/tegra.c | 3 +- include/configs/tegra-common.h | 10 ++- 55 files changed, 117 insertions(+), 553 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/ap.h delete mode 100644 arch/arm/include/asm/arch-tegra/timer.h delete mode 100644 arch/arm/include/asm/arch-tegra/uart.h delete mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h delete mode 100644 arch/arm/include/asm/arch-tegra124/display.h
Reviewed-by: Simon Glass sjg@chromium.org
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/*
- Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
Thanks.
Best regards,
Wolfgang Denk
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/*
- Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Dear Stephen,
In message 571E7135.2030807@wwwdotorg.org you wrote:
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Yes, I know these arguments. But actually this is b*llsh*t. Is there really no chance to drop that?
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Well, obviously other people were either notrequested to add this "All rights reserved." phrase, or found other ways to avoid it.
Can you please try to do the same?
Best regards,
Wolfgang Denk
On 04/25/2016 03:46 PM, Wolfgang Denk wrote:
Dear Stephen,
In message 571E7135.2030807@wwwdotorg.org you wrote:
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Yes, I know these arguments. But actually this is b*llsh*t. Is there really no chance to drop that?
I could ask NVIDIA legal again, but it's been discuss before and the guidance given was not changed, so I don't imagine it would be productive.
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Well, obviously other people were either notrequested to add this "All rights reserved." phrase, or found other ways to avoid it.
Can you please try to do the same?
Given that message about says "2010" as the start date, I imagine the file was created (or copied blindly from another file that was created) before NVIDIA legal gave guidance for us to follow. I could only do the same by not following their current guidance, or claiming I forgot this time, which would be rather hard to do given this email thread. Either way, our internal systems will ding me for this when I rebase the copy of U-Boot we use internally, so I'll have to explain it then.
Hi Stephen,
On 25 April 2016 at 13:34, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/*
- Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Perhaps you could consider just not updating the notices? It isn't required by U-Boot. I tend not to do it.
Also the all rights reserved thing is apparently pointless.
Regards, Simon
On 04/25/2016 03:54 PM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:34, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/* * Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Perhaps you could consider just not updating the notices? It isn't required by U-Boot. I tend not to do it.
Also the all rights reserved thing is apparently pointless.
NVIDIA legal says I have to.
I believe the only choice I have is whether to contribute to U-Boot.
That said, I will go and double check again.
Hi Stephen,
On 25 April 2016 at 16:02, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/25/2016 03:54 PM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:34, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/* * Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Perhaps you could consider just not updating the notices? It isn't required by U-Boot. I tend not to do it.
Also the all rights reserved thing is apparently pointless.
NVIDIA legal says I have to.
I believe the only choice I have is whether to contribute to U-Boot.
That said, I will go and double check again.
Also point them to this:
https://en.wikipedia.org/wiki/All_rights_reserved
I recall a similar discussion before...
Regards, Simon
On Mon, Apr 25, 2016 at 04:02:13PM -0600, Stephen Warren wrote:
On 04/25/2016 03:54 PM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:34, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-2-git-send-email-swarren@wwwdotorg.org you wrote:
...
/*
- Copyright (c) 2011 The Chromium OS Authors.
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
Can you please get rid of this "All rights reserved." ?
Sorry, that is the format I'm required to use by NVIDIA legal.
To address your next question, "all rights reserved" is 100% compatible with OSS licenses. Equally, the phrase already exists throughout both the U-Boot and Linux kernel code-base (just a couple of prominent examples) for both NVIDIA's copyright notices, and those of many other prominent entities such as The Linux Foundation, Red Hat, Intel, The Chromium OS Authors, etc.
Please fix this globally in the whole patch set.
I assume it cannot be a problem to do that, as in other places you did not add this either, for example here:
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /*
- (C) Copyright 2010-2015
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2010-2016
- NVIDIA Corporation <www.nvidia.com>
The primary purpose of this patch-set isn't to clean up copyright notices. As such, where I added new copyright notices I followed the format that NVIDIA legal requests me to. However, where I simply edited the date in existing notices I didn't do any other cleanup.
Perhaps you could consider just not updating the notices? It isn't required by U-Boot. I tend not to do it.
Also the all rights reserved thing is apparently pointless.
NVIDIA legal says I have to.
I believe the only choice I have is whether to contribute to U-Boot.
That said, I will go and double check again.
Please do go double check. Full disclosure, it's not something that's a dealbreaker for contributions, but I'd still rather not see it be added.
From: Stephen Warren swarren@nvidia.com
The initialization performed by this code is SoC-specific not board- specific. It also solely touches MMC controller registers. As such, it should be part of the MMC driver itself. Move it there.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 -- arch/arm/mach-tegra/board2.c | 29 -------------------------- drivers/mmc/tegra_mmc.c | 32 +++++++++++++++++++++++++++-- 3 files changed, 30 insertions(+), 33 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 9b371add1de4..adc9772a3c18 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -142,6 +142,4 @@ struct mmc_host { struct mmc_config cfg; /* mmc configuration */ };
-void pad_init_mmc(struct mmc_host *host); - #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 33e346017a8b..98fd94646909 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -31,7 +31,6 @@ #include <usb.h> #endif #ifdef CONFIG_TEGRA_MMC -#include <asm/arch-tegra/tegra_mmc.h> #include <asm/arch-tegra/mmc.h> #endif #include <asm/arch-tegra/xusb-padctl.h> @@ -246,34 +245,6 @@ int board_mmc_init(bd_t *bd)
return 0; } - -void pad_init_mmc(struct mmc_host *host) -{ -#if defined(CONFIG_TEGRA30) - enum periph_id id = host->mmc_id; - u32 val; - - debug("%s: sdmmc address = %08x, id = %d\n", __func__, - (unsigned int)host->reg, id); - - /* Set the pad drive strength for SDMMC1 or 3 only */ - if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { - debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); - return; - } - - val = readl(&host->reg->sdmemcmppadctl); - val &= 0xFFFFFFF0; - val |= MEMCOMP_PADCTRL_VREF; - writel(val, &host->reg->sdmemcmppadctl); - - val = readl(&host->reg->autocalcfg); - val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; - writel(val, &host->reg->autocalcfg); -#endif /* T30 */ -} #endif /* MMC */
/* diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 573819a01e21..23c6c2cf4583 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -1,8 +1,8 @@ /* + * Copyright 2011-2016 NVIDIA Corporation * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang mk7.kang@samsung.com * Jaehoon Chung jh80.chung@samsung.com - * Portions Copyright 2011-2015 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -428,6 +428,34 @@ static void tegra_mmc_set_ios(struct mmc *mmc) debug("mmc_set_ios: hostctl = %08X\n", ctrl); }
+static void tegra_mmc_pad_init(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + enum periph_id id = host->mmc_id; + u32 val; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} + static void mmc_reset(struct mmc_host *host, struct mmc *mmc) { unsigned int timeout; @@ -461,7 +489,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
/* Make sure SDIO pads are set up */ - pad_init_mmc(host); + tegra_mmc_pad_init(host); }
static int tegra_mmc_core_init(struct mmc *mmc)
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
The initialization performed by this code is SoC-specific not board- specific. It also solely touches MMC controller registers. As such, it should be part of the MMC driver itself. Move it there.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 -- arch/arm/mach-tegra/board2.c | 29 -------------------------- drivers/mmc/tegra_mmc.c | 32 +++++++++++++++++++++++++++-- 3 files changed, 30 insertions(+), 33 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Dear Stephen,
In message 1461099580-3866-3-git-send-email-swarren@wwwdotorg.org you wrote:
/*
- Copyright 2011-2016 NVIDIA Corporation
- (C) Copyright 2009 SAMSUNG Electronics
- Minkyu Kang mk7.kang@samsung.com
- Jaehoon Chung jh80.chung@samsung.com
*/
- Portions Copyright 2011-2015 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0+
Both the change of the position of the copyright note and the rewording contain a subtle but still significant change of meaning.
Now it seems as if Nvidia was the major copyright holder. Is this intentional?
Best regards,
Wolfgang Denk
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-3-git-send-email-swarren@wwwdotorg.org you wrote:
/*
- Copyright 2011-2016 NVIDIA Corporation
- (C) Copyright 2009 SAMSUNG Electronics
- Minkyu Kang mk7.kang@samsung.com
- Jaehoon Chung jh80.chung@samsung.com
*/
- Portions Copyright 2011-2015 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0+
Both the change of the position of the copyright note and the rewording contain a subtle but still significant change of meaning.
Now it seems as if Nvidia was the major copyright holder. Is this intentional?
I was not aware that the order actually implied anything. I would imagine the copyright dates and "git blame" output were more relevant since they pin-point specific changes, whereas copyright headers don't have the detail to convey the whole picture.
In this case, both "git log" and "git blame" certainly show that NVIDIA is the primary author of this code. I deliberately removed "Portions" because it was something uncommon and seems inaccurate. I don't recall why I changed the order; probably because I was editing a lot of files and just happened to paste the message there. I imagine the Samsung copyright notice is only there because the general structure of the file (set of functions implemented) was based on an existing driver, rather than because any of the non-boilerplate code was written by them.
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-3-git-send-email-swarren@wwwdotorg.org you wrote:
/*
- Copyright 2011-2016 NVIDIA Corporation
- (C) Copyright 2009 SAMSUNG Electronics
- Minkyu Kang mk7.kang@samsung.com
- Jaehoon Chung jh80.chung@samsung.com
*/
- Portions Copyright 2011-2015 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0+
Both the change of the position of the copyright note and the rewording contain a subtle but still significant change of meaning.
Now it seems as if Nvidia was the major copyright holder. Is this intentional?
I was not aware that the order actually implied anything. I would imagine the copyright dates and "git blame" output were more relevant since they pin-point specific changes, whereas copyright headers don't have the detail to convey the whole picture.
Well, just read the text before and after the patch, and let the meaning sink in...
In this case, both "git log" and "git blame" certainly show that NVIDIA is the primary author of this code. I deliberately removed "Portions" because it was something uncommon and seems inaccurate. I don't recall why I changed the order; probably because I was editing a lot of files and just happened to paste the message there. I imagine the Samsung copyright notice is only there because the general structure of the file (set of functions implemented) was based on an existing driver, rather than because any of the non-boilerplate code was written by them.
I did not check this, and I don't intend to do so. you may actually be right, and your modification may be perfectly OK.
But from just reading the patch, it leaves a stale aftertaste.
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
It is difficult for any outside party to verify this. I feel such changes require a lot of tact, and global edits are probably not a good idea. You know that I don't post very often lately, so you can imagine that this must have stirred me a bit.
Best regards,
Wolfgang Denk
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
On Mon, Apr 25, 2016 at 05:11:16PM -0600, Stephen Warren wrote:
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
Unfortunately we've (NVIDIA at least) been a little lax making sure the NVIDIA copyright messages are kept up-to-date when editing files, hence why this series had to change a lot of them for the first time recently. If we went back and re-wrote all of git history paying strict attention to the copyright notice dates and formatting, I imagine the set of copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
OK. And I assume you're globbing on file paths to check / update? Doing you can do 'git log --since=YYYY-01-01-YYYY-12-31' to find the first/last commits in a given year, git diff a..b | diffstat > Y.txt to get a diffstat and check your numbers vs that. This doesn't feel like an undue burden on making sure copyright stuff is year-correct for last-touch.
On 04/25/2016 05:26 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:11:16PM -0600, Stephen Warren wrote:
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote:
Dear Stephen Warren,
In message 571E733A.1060208@wwwdotorg.org you wrote:
[snip]
> Unfortunately we've (NVIDIA at least) been a little lax making sure the > NVIDIA copyright messages are kept up-to-date when editing files, hence > why this series had to change a lot of them for the first time recently. > If we went back and re-wrote all of git history paying strict attention > to the copyright notice dates and formatting, I imagine the set of > copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
OK. And I assume you're globbing on file paths to check / update? Doing you can do 'git log --since=YYYY-01-01-YYYY-12-31' to find the first/last commits in a given year, git diff a..b | diffstat > Y.txt to get a diffstat and check your numbers vs that. This doesn't feel like an undue burden on making sure copyright stuff is year-correct for last-touch.
Well, by "yet" I assumed you mean "before this patch set". There are no changes in the patch set that do nothing but edit/add a copyright notice without making other changes. The only edits to copyrights in this series are because I've edited files for the purpose behind the patch, and then have updated the copyright while doing so.
What I did was: a) Make all the changes. b) Go through all the patches with "git rebase -i", get the list of files edited in the patch, and ensure the copyright date reflected the edit made in that patch.
BTW, while code re-org is not the most involved of coding, I don't see a reason to make developers decide legal issues such as what amounts to a change that's large enough to change the copyright date, or add a copyright header. The rule should be simple and unambiguous (edit a file -> change the copyright); anything else is asking for different people to argue over interpretation, which just everybody's wastes time. Let's leave that to lawyers and just deal with code.
On Mon, Apr 25, 2016 at 05:34:55PM -0600, Stephen Warren wrote:
On 04/25/2016 05:26 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:11:16PM -0600, Stephen Warren wrote:
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote: >Dear Stephen Warren, > >In message 571E733A.1060208@wwwdotorg.org you wrote: [snip] >>Unfortunately we've (NVIDIA at least) been a little lax making sure the >>NVIDIA copyright messages are kept up-to-date when editing files, hence >>why this series had to change a lot of them for the first time recently. >>If we went back and re-wrote all of git history paying strict attention >>to the copyright notice dates and formatting, I imagine the set of >>copyright-related changes in this series would be much smaller.
I'm quoting Wolfgang's email here, but, yes, keeping the copyright notices correct is important. Now, what do you mean by would be smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
OK. And I assume you're globbing on file paths to check / update? Doing you can do 'git log --since=YYYY-01-01-YYYY-12-31' to find the first/last commits in a given year, git diff a..b | diffstat > Y.txt to get a diffstat and check your numbers vs that. This doesn't feel like an undue burden on making sure copyright stuff is year-correct for last-touch.
Well, by "yet" I assumed you mean "before this patch set". There are no changes in the patch set that do nothing but edit/add a copyright notice without making other changes. The only edits to copyrights in this series are because I've edited files for the purpose behind the patch, and then have updated the copyright while doing so.
What I did was: a) Make all the changes. b) Go through all the patches with "git rebase -i", get the list of files edited in the patch, and ensure the copyright date reflected the edit made in that patch.
OK. This should make any quick sanity checks easier, rather than harder. Generate the lists, diffstat your series, for F in series, grep -q year-list && echo touched $F;done
BTW, while code re-org is not the most involved of coding, I don't see a reason to make developers decide legal issues such as what amounts to a change that's large enough to change the copyright date, or add a copyright header. The rule should be simple and unambiguous (edit a file -> change the copyright); anything else is asking for different people to argue over interpretation, which just everybody's wastes time. Let's leave that to lawyers and just deal with code.
I agree in spirit, with a caveat about meeting a significance threshold. I think you need to push back on your legal department if they are asking that every change requires a copyright notice, regardless of length or complexity. I _cannot_ start having patches conflict because the contents are fine but now I have to fixup the copyright notices added since the patch was generated, and then I suppose toss in my own copyright too, because now I've made some change to the file. Since you mentioned the kernel, I just popped open git log -p in the kernel and I do not see a flood of "made a change, add/update copyright".
On 04/25/2016 06:14 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:34:55PM -0600, Stephen Warren wrote:
On 04/25/2016 05:26 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:11:16PM -0600, Stephen Warren wrote:
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote:
On 04/25/2016 04:37 PM, Tom Rini wrote: > On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote: >> Dear Stephen Warren, >> >> In message 571E733A.1060208@wwwdotorg.org you wrote: > [snip] >>> Unfortunately we've (NVIDIA at least) been a little lax making sure the >>> NVIDIA copyright messages are kept up-to-date when editing files, hence >>> why this series had to change a lot of them for the first time recently. >>> If we went back and re-wrote all of git history paying strict attention >>> to the copyright notice dates and formatting, I imagine the set of >>> copyright-related changes in this series would be much smaller. > > I'm quoting Wolfgang's email here, but, yes, keeping the copyright > notices correct is important. Now, what do you mean by would be > smaller?
Personally I want to spend my time coding rather than dealing with licensing. As such, it's easy to forget to update the dates in copyright notices when changing files, or to put the correct information into new files when creating new ones (often by just cutting/pasting some other file with similar issues). If we had done that 100% correctly in every commit across history, my inclination is that more files would already have an NVIDIA copyright message, and/or already have 2016 in the date, and hence this series wouldn't include an edit to those messages since they'd already be up-to-date. Still, I have no searched all history to confirm that; it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
OK. And I assume you're globbing on file paths to check / update? Doing you can do 'git log --since=YYYY-01-01-YYYY-12-31' to find the first/last commits in a given year, git diff a..b | diffstat > Y.txt to get a diffstat and check your numbers vs that. This doesn't feel like an undue burden on making sure copyright stuff is year-correct for last-touch.
Well, by "yet" I assumed you mean "before this patch set". There are no changes in the patch set that do nothing but edit/add a copyright notice without making other changes. The only edits to copyrights in this series are because I've edited files for the purpose behind the patch, and then have updated the copyright while doing so.
What I did was: a) Make all the changes. b) Go through all the patches with "git rebase -i", get the list of files edited in the patch, and ensure the copyright date reflected the edit made in that patch.
OK. This should make any quick sanity checks easier, rather than harder. Generate the lists, diffstat your series, for F in series, grep -q year-list && echo touched $F;done
BTW, while code re-org is not the most involved of coding, I don't see a reason to make developers decide legal issues such as what amounts to a change that's large enough to change the copyright date, or add a copyright header. The rule should be simple and unambiguous (edit a file -> change the copyright); anything else is asking for different people to argue over interpretation, which just everybody's wastes time. Let's leave that to lawyers and just deal with code.
I agree in spirit, with a caveat about meeting a significance threshold. I think you need to push back on your legal department if they are asking that every change requires a copyright notice, regardless of length or complexity. I _cannot_ start having patches conflict because the contents are fine but now I have to fixup the copyright notices added since the patch was generated,
I'm not sure why. Let's say the two conflicting patches are both unambiguously significant works, by two different people/entities. Surely there's no issue with the copyright notices both being added/updated in that case? If so, then the only difference is the volume of conflicts. Volume doesn't seem a great argument since it's not a problem with the core issue itself.
On Tue, Apr 26, 2016 at 10:21:08AM -0600, Stephen Warren wrote:
On 04/25/2016 06:14 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:34:55PM -0600, Stephen Warren wrote:
On 04/25/2016 05:26 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 05:11:16PM -0600, Stephen Warren wrote:
On 04/25/2016 05:05 PM, Tom Rini wrote:
On Mon, Apr 25, 2016 at 04:43:34PM -0600, Stephen Warren wrote: >On 04/25/2016 04:37 PM, Tom Rini wrote: >>On Mon, Apr 25, 2016 at 11:52:53PM +0200, Wolfgang Denk wrote: >>>Dear Stephen Warren, >>> >>>In message 571E733A.1060208@wwwdotorg.org you wrote: >>[snip] >>>>Unfortunately we've (NVIDIA at least) been a little lax making sure the >>>>NVIDIA copyright messages are kept up-to-date when editing files, hence >>>>why this series had to change a lot of them for the first time recently. >>>>If we went back and re-wrote all of git history paying strict attention >>>>to the copyright notice dates and formatting, I imagine the set of >>>>copyright-related changes in this series would be much smaller. >> >>I'm quoting Wolfgang's email here, but, yes, keeping the copyright >>notices correct is important. Now, what do you mean by would be >>smaller? > >Personally I want to spend my time coding rather than dealing with >licensing. As such, it's easy to forget to update the dates in >copyright notices when changing files, or to put the correct >information into new files when creating new ones (often by just >cutting/pasting some other file with similar issues). If we had done >that 100% correctly in every commit across history, my inclination >is that more files would already have an NVIDIA copyright message, >and/or already have 2016 in the date, and hence this series wouldn't >include an edit to those messages since they'd already be >up-to-date. Still, I have no searched all history to confirm that; >it's just my gut instinct.
Right, OK. So you're saying you may, in some cases, be adding 2016 to files you haven't touched this year yet?
Yes, I'm sure there's a mix.
OK. And I assume you're globbing on file paths to check / update? Doing you can do 'git log --since=YYYY-01-01-YYYY-12-31' to find the first/last commits in a given year, git diff a..b | diffstat > Y.txt to get a diffstat and check your numbers vs that. This doesn't feel like an undue burden on making sure copyright stuff is year-correct for last-touch.
Well, by "yet" I assumed you mean "before this patch set". There are no changes in the patch set that do nothing but edit/add a copyright notice without making other changes. The only edits to copyrights in this series are because I've edited files for the purpose behind the patch, and then have updated the copyright while doing so.
What I did was: a) Make all the changes. b) Go through all the patches with "git rebase -i", get the list of files edited in the patch, and ensure the copyright date reflected the edit made in that patch.
OK. This should make any quick sanity checks easier, rather than harder. Generate the lists, diffstat your series, for F in series, grep -q year-list && echo touched $F;done
BTW, while code re-org is not the most involved of coding, I don't see a reason to make developers decide legal issues such as what amounts to a change that's large enough to change the copyright date, or add a copyright header. The rule should be simple and unambiguous (edit a file -> change the copyright); anything else is asking for different people to argue over interpretation, which just everybody's wastes time. Let's leave that to lawyers and just deal with code.
I agree in spirit, with a caveat about meeting a significance threshold. I think you need to push back on your legal department if they are asking that every change requires a copyright notice, regardless of length or complexity. I _cannot_ start having patches conflict because the contents are fine but now I have to fixup the copyright notices added since the patch was generated,
I'm not sure why. Let's say the two conflicting patches are both unambiguously significant works, by two different people/entities. Surely there's no issue with the copyright notices both being added/updated in that case? If so, then the only difference is the volume of conflicts. Volume doesn't seem a great argument since it's not a problem with the core issue itself.
The problem here is that much of this series is not making unambiguously significant changes. I do not have a problem with (but maybe I need to chat with the Software Freedom Conservancy folks more) adding / extending copyrights when adding significant changes to existing files nor adding them to new files.
Dear Stephen,
In message 571EA99F.7030602@wwwdotorg.org you wrote:
BTW, while code re-org is not the most involved of coding, I don't see a reason to make developers decide legal issues such as what amounts to a change that's large enough to change the copyright date, or add a copyright header. The rule should be simple and unambiguous (edit a file -> change the copyright); anything else is asking for different people to argue over interpretation, which just everybody's wastes time. Let's leave that to lawyers and just deal with code.
There is no simple rule. Adding a copyright header means you claim your (or your company's) copyright, i. e. you are referring to legal rules, which ar inherently non-trivial. even more so, as this is a multi-national project - even though nternation copyright laws are pretty much similar worldwide (there are international treaties like the Berne convention), there may still be differences.
One area where (to the best of my knowledge - IANAL) there appears to be agreement is that you must meet some "Creativity Requirement" with the work you created to make it copyrightable at all.
Moving two include lines around is not really creative, and I feel sad that we have to go into such lengthy discussions here.
Best regards,
Wolfgang Denk
From: Stephen Warren swarren@nvidia.com
tegra_mmc.h only contains private definitions for use inside the MMC driver. Move it out of the global include directory since nothing needs to access it there.
tegra_mmc.h doesn't depend on anything from <fdtdec.h>, so move that include to the C file.
Signed-off-by: Stephen Warren swarren@nvidia.com --- drivers/mmc/tegra_mmc.c | 3 ++- .../asm/arch-tegra/tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h | 7 +++---- 2 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/include/asm/arch-tegra/tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h (98%)
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 23c6c2cf4583..12b14fc35d08 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -9,13 +9,14 @@
#include <bouncebuf.h> #include <common.h> +#include <fdtdec.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/mmc.h> -#include <asm/arch-tegra/tegra_mmc.h> #include <mmc.h> +#include "tegra_mmc_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/drivers/mmc/tegra_mmc_priv.h similarity index 98% rename from arch/arm/include/asm/arch-tegra/tegra_mmc.h rename to drivers/mmc/tegra_mmc_priv.h index adc9772a3c18..3d9bcb78187c 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/drivers/mmc/tegra_mmc_priv.h @@ -6,10 +6,9 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __TEGRA_MMC_H_ -#define __TEGRA_MMC_H_ +#ifndef __TEGRA_MMC_PRIV_H_ +#define __TEGRA_MMC_PRIV_H_
-#include <fdtdec.h> #include <asm/gpio.h>
/* for mmc_config definition */ @@ -142,4 +141,4 @@ struct mmc_host { struct mmc_config cfg; /* mmc configuration */ };
-#endif /* __TEGRA_MMC_H_ */ +#endif
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
tegra_mmc.h only contains private definitions for use inside the MMC driver. Move it out of the global include directory since nothing needs to access it there.
tegra_mmc.h doesn't depend on anything from <fdtdec.h>, so move that include to the C file.
Signed-off-by: Stephen Warren swarren@nvidia.com
drivers/mmc/tegra_mmc.c | 3 ++- .../asm/arch-tegra/tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h | 7 +++---- 2 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/include/asm/arch-tegra/tegra_mmc.h => drivers/mmc/tegra_mmc_priv.h (98%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra/mmc.h => mach-tegra/include/mach/tegra_mmc.h} | 7 ++++--- drivers/mmc/tegra_mmc.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra/mmc.h => mach-tegra/include/mach/tegra_mmc.h} (50%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 98fd94646909..05e83268cd40 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -31,7 +31,7 @@ #include <usb.h> #endif #ifdef CONFIG_TEGRA_MMC -#include <asm/arch-tegra/mmc.h> +#include <mach/tegra_mmc.h> #endif #include <asm/arch-tegra/xusb-padctl.h> #include <power/as3722.h> diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/mach-tegra/include/mach/tegra_mmc.h similarity index 50% rename from arch/arm/include/asm/arch-tegra/mmc.h rename to arch/arm/mach-tegra/include/mach/tegra_mmc.h index c2d52b297743..23f90e300b2a 100644 --- a/arch/arm/include/asm/arch-tegra/mmc.h +++ b/arch/arm/mach-tegra/include/mach/tegra_mmc.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2011, Google Inc. All rights reserved. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_MMC_H_ -#define _TEGRA_MMC_H_ +#ifndef _MACH_TEGRA_MMC_H_ +#define _MACH_TEGRA_MMC_H_
void tegra_mmc_init(void);
-#endif /* _TEGRA_MMC_H_ */ +#endif diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 12b14fc35d08..6e1667b3bce7 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -10,12 +10,12 @@ #include <bouncebuf.h> #include <common.h> #include <fdtdec.h> +#include <mmc.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/mmc.h> -#include <mmc.h> +#include <mach/tegra_mmc.h> #include "tegra_mmc_priv.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra/mmc.h => mach-tegra/include/mach/tegra_mmc.h} | 7 ++++--- drivers/mmc/tegra_mmc.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra/mmc.h => mach-tegra/include/mach/tegra_mmc.h} (50%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Tegra's pwm.h only contains private definitions for use inside the Tegra PWM driver. Move it out of the global include directory since nothing needs to access it there.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra124/pwm.h | 14 -------------- arch/arm/include/asm/arch-tegra20/pwm.h | 14 -------------- drivers/pwm/tegra_pwm.c | 3 ++- .../asm/arch-tegra/pwm.h => drivers/pwm/tegra_pwm_priv.h | 6 +++--- drivers/video/tegra.c | 1 - drivers/video/tegra124/display.c | 2 +- 6 files changed, 6 insertions(+), 34 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra124/pwm.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pwm.h rename arch/arm/include/asm/arch-tegra/pwm.h => drivers/pwm/tegra_pwm_priv.h (86%)
diff --git a/arch/arm/include/asm/arch-tegra124/pwm.h b/arch/arm/include/asm/arch-tegra124/pwm.h deleted file mode 100644 index 3d2c4324dc1d..000000000000 --- a/arch/arm/include/asm/arch-tegra124/pwm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA124_PWM_H -#define __ASM_ARCH_TEGRA124_PWM_H - -#include <asm/arch-tegra/pwm.h> - -#endif /* __ASM_ARCH_TEGRA124_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h deleted file mode 100644 index 2207d9cd4d74..000000000000 --- a/arch/arm/include/asm/arch-tegra20/pwm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA20_PWM_H -#define __ASM_ARCH_TEGRA20_PWM_H - -#include <asm/arch-tegra/pwm.h> - -#endif /* __ASM_ARCH_TEGRA20_PWM_H */ diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index 10e1fdc9b562..a0f204a216de 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -1,5 +1,6 @@ /* * Copyright 2016 Google Inc. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +10,7 @@ #include <pwm.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pwm.h> +#include "tegra_pwm_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/drivers/pwm/tegra_pwm_priv.h similarity index 86% rename from arch/arm/include/asm/arch-tegra/pwm.h rename to drivers/pwm/tegra_pwm_priv.h index b69c0b041f40..25943494fb5c 100644 --- a/arch/arm/include/asm/arch-tegra/pwm.h +++ b/drivers/pwm/tegra_pwm_priv.h @@ -7,8 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __ASM_ARCH_TEGRA_PWM_H -#define __ASM_ARCH_TEGRA_PWM_H +#ifndef _TEGRA_PWM_PRIV_H +#define _TEGRA_PWM_PRIV_H
/* This is a single PWM channel */ struct pwm_ctlr { @@ -26,4 +26,4 @@ struct pwm_ctlr { #define PWM_DIVIDER_SHIFT 0 #define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
-#endif /* __ASM_ARCH_TEGRA_PWM_H */ +#endif diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 13b10645478e..b4c83b674147 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -17,7 +17,6 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/pwm.h> #include <asm/arch/display.h>
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index 2f1f0df20eb1..d627285b8081 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -1,5 +1,6 @@ /* * Copyright 2014 Google Inc. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ * @@ -18,7 +19,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pwm.h> #include <asm/arch-tegra/dc.h> #include <dm/uclass-internal.h> #include "displayport.h"
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's pwm.h only contains private definitions for use inside the Tegra PWM driver. Move it out of the global include directory since nothing needs to access it there.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra124/pwm.h | 14 -------------- arch/arm/include/asm/arch-tegra20/pwm.h | 14 -------------- drivers/pwm/tegra_pwm.c | 3 ++- .../asm/arch-tegra/pwm.h => drivers/pwm/tegra_pwm_priv.h | 6 +++--- drivers/video/tegra.c | 1 - drivers/video/tegra124/display.c | 2 +- 6 files changed, 6 insertions(+), 34 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra124/pwm.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pwm.h rename arch/arm/include/asm/arch-tegra/pwm.h => drivers/pwm/tegra_pwm_priv.h (86%)
Reviewed-by: Simon Glass sjg@chromium.org
Dear Stephen,
In message 1461099580-3866-6-git-send-email-swarren@wwwdotorg.org you wrote:
Tegra's pwm.h only contains private definitions for use inside the Tegra PWM driver. Move it out of the global include directory since nothing needs to access it there.
If I understand correctly, all this is just a reorganisation of code. There is no new code or functionality added, right?
-/*
- Tegra pulse width frequency modulator definitions
- Copyright (c) 2011 The Chromium OS Authors.
...
-/*
- Tegra pulse width frequency modulator definitions
- Copyright (c) 2011 The Chromium OS Authors.
...
/*
- Copyright 2016 Google Inc.
- Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
...
But then, you drop the original copyright notices of the Chromium project, and replace it by a Nvidia note, and even with this exasperating "All rights reserved" note.
Sorry, but this seems politically incorrect to me.
Best regards,
Wolfgang Denk
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-6-git-send-email-swarren@wwwdotorg.org you wrote:
Tegra's pwm.h only contains private definitions for use inside the Tegra PWM driver. Move it out of the global include directory since nothing needs to access it there.
If I understand correctly, all this is just a reorganisation of code. There is no new code or functionality added, right?
That's true in this patch, certainly.
-/*
- Tegra pulse width frequency modulator definitions
- Copyright (c) 2011 The Chromium OS Authors.
...
-/*
- Tegra pulse width frequency modulator definitions
- Copyright (c) 2011 The Chromium OS Authors.
...
/*
- Copyright 2016 Google Inc.
- Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
...
But then, you drop the original copyright notices of the Chromium project,
Those copyright messages were deleted because those files were deleted. In this case (this patch) at least, those files contained nothing but a #include for other files.
For files that were moved (e.g. arch/arm/include/asm/arch-tegra/pwm.h in this patch), all original copyright messages (in this case, both Chromium OS and NVIDIA) were maintained.
I'm not aware of any deletions of copyright messages in files that were not completely deleted, or where the same content was moved elsewhere. If you find any, it was a simple oversight.
From: Stephen Warren swarren@nvidia.com
tegra_i2c.h contains primarily private definitions for use inside the I2C driver. Move those out of the global include directory since nothing should need to access them.
The Tegra I2C driver exports a Tegra-specific API. Move its prototype into a <mach/*> header. Hopefully one day this will go away.
Tegra's SPL doesn't (yet?) support the full I2C driver stack. However, SPL must make some I2C accesses to program the PMIC to boot the main CPU complex (note that Tegra's SPL runs on a different CPU). Share the implementation of those functions in a new file. This isolates the hacky use of private register definitions to a single file.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/Makefile | 3 ++- arch/arm/mach-tegra/i2c_early.c | 28 ++++++++++++++++++++++ arch/arm/mach-tegra/include/mach/tegra_i2c.h | 25 +++++++++++++++++++ arch/arm/mach-tegra/tegra20/pmu.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 19 ++------------- board/nvidia/venice2/as3722_init.c | 20 ++-------------- drivers/i2c/tegra_i2c.c | 3 ++- .../tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h | 13 +++------- 8 files changed, 65 insertions(+), 48 deletions(-) create mode 100644 arch/arm/mach-tegra/i2c_early.c create mode 100644 arch/arm/mach-tegra/include/mach/tegra_i2c.h rename arch/arm/include/asm/arch-tegra/tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h (95%)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index b2dbc6999c71..197bdfeadd57 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2010-2015 Nvidia Corporation. +# (C) Copyright 2010-2016 Nvidia Corporation. # # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -26,6 +26,7 @@ obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_SPL_BUILD) += i2c_early.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/arch/arm/mach-tegra/i2c_early.c b/arch/arm/mach-tegra/i2c_early.c new file mode 100644 index 000000000000..dcdd86cef71e --- /dev/null +++ b/arch/arm/mach-tegra/i2c_early.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2010-2016 NVIDIA Corporation + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/tegra_i2c.h> +#include "../../../drivers/i2c/tegra_i2c_priv.h" + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} diff --git a/arch/arm/mach-tegra/include/mach/tegra_i2c.h b/arch/arm/mach-tegra/include/mach/tegra_i2c.h new file mode 100644 index 000000000000..57837885176a --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/tegra_i2c.h @@ -0,0 +1,25 @@ +/* + * NVIDIA Tegra I2C controller custom API + * + * Copyright 2010-2016 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MACH_TEGRA_I2C_H_ +#define _MACH_TEGRA_I2C_H_ + +struct udevice; + +/* Custom APIs for very early I2C access */ +void tegra_i2c_ll_write_addr(uint addr, uint config); +void tegra_i2c_ll_write_data(uint data, uint config); + +/** + * Returns the bus number of the DVC controller + * + * @return number of bus, or -1 if there is no DVC active + */ +int tegra_i2c_get_dvc_bus(struct udevice **busp); + +#endif diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 0da704cd4f3c..8488d97d5cde 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -10,8 +10,8 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/tegra_i2c.h> #include <asm/arch-tegra/sys_proto.h> +#include <mach/tegra_i2c.h> #include "../cpu.h"
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 66b021b82459..774207354064 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,25 +11,10 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> #include "../cpu.h"
/* Tegra30-specific CPU init code */ -void tegra_i2c_ll_write_addr(uint addr, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(addr, ®->cmd_addr0); - writel(config, ®->cnfg); -} - -void tegra_i2c_ll_write_data(uint data, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(data, ®->cmd_data1); - writel(config, ®->cnfg); -}
#define TPS62366A_I2C_ADDR 0xC0 #define TPS62366A_SET1_REG 0x01 diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 960fea7ee7e3..86b164db3be1 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,27 +7,11 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> #include "as3722_init.h"
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
-void tegra_i2c_ll_write_addr(uint addr, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(addr, ®->cmd_addr0); - writel(config, ®->cnfg); -} - -void tegra_i2c_ll_write_data(uint data, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(data, ®->cmd_data1); - writel(config, ®->cnfg); -} - void pmic_enable_cpu_vdd(void) { debug("%s entry\n", __func__); diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 0735ea0b2b12..2a8ab2d5e0b9 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -17,7 +17,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> +#include "tegra_i2c_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/drivers/i2c/tegra_i2c_priv.h similarity index 95% rename from arch/arm/include/asm/arch-tegra/tegra_i2c.h rename to drivers/i2c/tegra_i2c_priv.h index eb83af89f7f5..95c73293d341 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/drivers/i2c/tegra_i2c_priv.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0 */
-#ifndef _TEGRA_I2C_H_ -#define _TEGRA_I2C_H_ +#ifndef _TEGRA_I2C_PRIV_H +#define _TEGRA_I2C_PRIV_H
#include <asm/types.h>
@@ -139,11 +139,4 @@ struct i2c_ctlr { /* I2C_CLK_DIVISOR_REGISTER */ #define CLK_MULT_STD_FAST_MODE 8
-/** - * Returns the bus number of the DVC controller - * - * @return number of bus, or -1 if there is no DVC active - */ -int tegra_i2c_get_dvc_bus(struct udevice **busp); - -#endif /* _TEGRA_I2C_H_ */ +#endif
Hello Stephen,
Am 19.04.2016 um 22:58 schrieb Stephen Warren:
From: Stephen Warren swarren@nvidia.com
tegra_i2c.h contains primarily private definitions for use inside the I2C driver. Move those out of the global include directory since nothing should need to access them.
The Tegra I2C driver exports a Tegra-specific API. Move its prototype into a <mach/*> header. Hopefully one day this will go away.
Tegra's SPL doesn't (yet?) support the full I2C driver stack. However, SPL must make some I2C accesses to program the PMIC to boot the main CPU complex (note that Tegra's SPL runs on a different CPU). Share the implementation of those functions in a new file. This isolates the hacky use of private register definitions to a single file.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/Makefile | 3 ++- arch/arm/mach-tegra/i2c_early.c | 28 ++++++++++++++++++++++ arch/arm/mach-tegra/include/mach/tegra_i2c.h | 25 +++++++++++++++++++ arch/arm/mach-tegra/tegra20/pmu.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 19 ++------------- board/nvidia/venice2/as3722_init.c | 20 ++-------------- drivers/i2c/tegra_i2c.c | 3 ++- .../tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h | 13 +++------- 8 files changed, 65 insertions(+), 48 deletions(-) create mode 100644 arch/arm/mach-tegra/i2c_early.c create mode 100644 arch/arm/mach-tegra/include/mach/tegra_i2c.h rename arch/arm/include/asm/arch-tegra/tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h (95%)
Thanks!
Acked-by: Heiko Schocher hs@denx.de
bye, Heiko
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index b2dbc6999c71..197bdfeadd57 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2010-2015 Nvidia Corporation. +# (C) Copyright 2010-2016 Nvidia Corporation. # # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -26,6 +26,7 @@ obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_SPL_BUILD) += i2c_early.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/arch/arm/mach-tegra/i2c_early.c b/arch/arm/mach-tegra/i2c_early.c new file mode 100644 index 000000000000..dcdd86cef71e --- /dev/null +++ b/arch/arm/mach-tegra/i2c_early.c @@ -0,0 +1,28 @@ +/*
- Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
- Copyright (c) 2010-2016 NVIDIA Corporation
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <mach/tegra_i2c.h> +#include "../../../drivers/i2c/tegra_i2c_priv.h"
+void tegra_i2c_ll_write_addr(uint addr, uint config) +{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
+}
+void tegra_i2c_ll_write_data(uint data, uint config) +{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
+} diff --git a/arch/arm/mach-tegra/include/mach/tegra_i2c.h b/arch/arm/mach-tegra/include/mach/tegra_i2c.h new file mode 100644 index 000000000000..57837885176a --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/tegra_i2c.h @@ -0,0 +1,25 @@ +/*
- NVIDIA Tegra I2C controller custom API
- Copyright 2010-2016 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0
- */
+#ifndef _MACH_TEGRA_I2C_H_ +#define _MACH_TEGRA_I2C_H_
+struct udevice;
+/* Custom APIs for very early I2C access */ +void tegra_i2c_ll_write_addr(uint addr, uint config); +void tegra_i2c_ll_write_data(uint data, uint config);
+/**
- Returns the bus number of the DVC controller
- @return number of bus, or -1 if there is no DVC active
- */
+int tegra_i2c_get_dvc_bus(struct udevice **busp);
+#endif diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 0da704cd4f3c..8488d97d5cde 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -10,8 +10,8 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/tegra_i2c.h> #include <asm/arch-tegra/sys_proto.h> +#include <mach/tegra_i2c.h> #include "../cpu.h"
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 66b021b82459..774207354064 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -1,5 +1,5 @@ /*
- Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*/
- Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0
@@ -11,25 +11,10 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> #include "../cpu.h"
/* Tegra30-specific CPU init code */ -void tegra_i2c_ll_write_addr(uint addr, uint config) -{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
-}
-void tegra_i2c_ll_write_data(uint data, uint config) -{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
-}
#define TPS62366A_I2C_ADDR 0xC0 #define TPS62366A_SET1_REG 0x01 diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 960fea7ee7e3..86b164db3be1 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -1,5 +1,5 @@ /*
- (C) Copyright 2013
- (C) Copyright 2013-2016
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
@@ -7,27 +7,11 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> #include "as3722_init.h"
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
-void tegra_i2c_ll_write_addr(uint addr, uint config) -{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
-}
-void tegra_i2c_ll_write_data(uint data, uint config) -{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
-}
- void pmic_enable_cpu_vdd(void) { debug("%s entry\n", __func__);
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 0735ea0b2b12..2a8ab2d5e0b9 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -17,7 +17,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/tegra_i2c.h> +#include <mach/tegra_i2c.h> +#include "tegra_i2c_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/drivers/i2c/tegra_i2c_priv.h similarity index 95% rename from arch/arm/include/asm/arch-tegra/tegra_i2c.h rename to drivers/i2c/tegra_i2c_priv.h index eb83af89f7f5..95c73293d341 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/drivers/i2c/tegra_i2c_priv.h @@ -6,8 +6,8 @@
- SPDX-License-Identifier: GPL-2.0
*/
-#ifndef _TEGRA_I2C_H_ -#define _TEGRA_I2C_H_ +#ifndef _TEGRA_I2C_PRIV_H +#define _TEGRA_I2C_PRIV_H
#include <asm/types.h>
@@ -139,11 +139,4 @@ struct i2c_ctlr { /* I2C_CLK_DIVISOR_REGISTER */ #define CLK_MULT_STD_FAST_MODE 8
-/**
- Returns the bus number of the DVC controller
- @return number of bus, or -1 if there is no DVC active
- */
-int tegra_i2c_get_dvc_bus(struct udevice **busp);
-#endif /* _TEGRA_I2C_H_ */ +#endif
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
tegra_i2c.h contains primarily private definitions for use inside the I2C driver. Move those out of the global include directory since nothing should need to access them.
The Tegra I2C driver exports a Tegra-specific API. Move its prototype into a <mach/*> header. Hopefully one day this will go away.
Tegra's SPL doesn't (yet?) support the full I2C driver stack. However, SPL must make some I2C accesses to program the PMIC to boot the main CPU complex (note that Tegra's SPL runs on a different CPU). Share the implementation of those functions in a new file. This isolates the hacky use of private register definitions to a single file.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/Makefile | 3 ++- arch/arm/mach-tegra/i2c_early.c | 28 ++++++++++++++++++++++ arch/arm/mach-tegra/include/mach/tegra_i2c.h | 25 +++++++++++++++++++ arch/arm/mach-tegra/tegra20/pmu.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 19 ++------------- board/nvidia/venice2/as3722_init.c | 20 ++-------------- drivers/i2c/tegra_i2c.c | 3 ++- .../tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h | 13 +++------- 8 files changed, 65 insertions(+), 48 deletions(-) create mode 100644 arch/arm/mach-tegra/i2c_early.c create mode 100644 arch/arm/mach-tegra/include/mach/tegra_i2c.h rename arch/arm/include/asm/arch-tegra/tegra_i2c.h => drivers/i2c/tegra_i2c_priv.h (95%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Tegra's usb.h only contains private definitions for use inside the Tegra EHCI driver. Move it out of the global include directory since nothing should need to access them.
One access to these registers does exist; a boot-time cleanup of any previous USB device-mode session. Hopefully this can be moved into the EHCI controller probe/bind at some point, presuming that USB devices get probed/bound at boot even before USB is used.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra/usb.h => drivers/usb/host/ehci-tegra-priv.h | 6 +++--- drivers/usb/host/ehci-tegra.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/include/asm/arch-tegra/usb.h => drivers/usb/host/ehci-tegra-priv.h (99%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 05e83268cd40..3ee65ee3f921 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -26,7 +26,7 @@ #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif -#include <asm/arch-tegra/usb.h> +#include "../../../drivers/usb/host/ehci-tegra-priv.h" #ifdef CONFIG_USB_EHCI_TEGRA #include <usb.h> #endif diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/drivers/usb/host/ehci-tegra-priv.h similarity index 99% rename from arch/arm/include/asm/arch-tegra/usb.h rename to drivers/usb/host/ehci-tegra-priv.h index 24198e4a33d0..72d8a1a7eb9c 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/drivers/usb/host/ehci-tegra-priv.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_USB_H_ -#define _TEGRA_USB_H_ +#ifndef _EHCI_TEGRA_PRIV_H +#define _EHCI_TEGRA_PRIV_H
/* USB Controller (USBx_CONTROLLER_) regs */ struct usb_ctlr { @@ -355,4 +355,4 @@ struct usb_ctlr { #define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) #define VBUS_B_SESS_VLD_SW_EN (1 << 11)
-#endif /* _TEGRA_USB_H_ */ +#endif diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 31d54ab285bf..9bf069382605 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2009-2015 NVIDIA Corporation + * Copyright (c) 2009-2016 NVIDIA Corporation * Copyright (c) 2013 Lucas Stach * * SPDX-License-Identifier: GPL-2.0+ @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm-generic/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch-tegra/usb.h> #include <asm/arch-tegra/clk_rst.h> #include <usb.h> #include <usb/ulpi.h> @@ -20,6 +19,7 @@ #include <fdtdec.h>
#include "ehci.h" +#include "ehci-tegra-priv.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's usb.h only contains private definitions for use inside the Tegra EHCI driver. Move it out of the global include directory since nothing should need to access them.
One access to these registers does exist; a boot-time cleanup of any previous USB device-mode session. Hopefully this can be moved into the EHCI controller probe/bind at some point, presuming that USB devices get probed/bound at boot even before USB is used.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra/usb.h => drivers/usb/host/ehci-tegra-priv.h | 6 +++--- drivers/usb/host/ehci-tegra.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/include/asm/arch-tegra/usb.h => drivers/usb/host/ehci-tegra-priv.h (99%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Tegra's dc.h/display.h only contain private definitions for use inside the Tegra display driver. Move them out of the global include directory since nothing needs to access it there. Since they both describe DC registers, combine then into a single header.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra20/display.h | 29 --------------------- arch/arm/mach-tegra/tegra20/display.c | 15 ----------- drivers/video/tegra.c | 3 +-- drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/dp.c | 4 +-- drivers/video/tegra124/sor.c | 4 +-- .../arch-tegra/dc.h => drivers/video/tegra_dc.h | 30 +++++++++++++++++++--- 7 files changed, 32 insertions(+), 55 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h delete mode 100644 arch/arm/mach-tegra/tegra20/display.c rename arch/arm/include/asm/arch-tegra/dc.h => drivers/video/tegra_dc.h (94%)
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index ee5a3f6c91c0..000000000000 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c deleted file mode 100644 index 52a476eb7d8a..000000000000 --- a/arch/arm/mach-tegra/tegra20/display.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/tegra.h> -#include <asm/arch/display.h> -#include <asm/arch-tegra/dc.h> -#include <asm/arch-tegra/clk_rst.h> - diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index b4c83b674147..45a2876d4030 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -13,11 +13,10 @@ #include <asm/system.h> #include <asm/gpio.h> #include <asm/io.h> - #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/display.h> +#include "tegra_dc.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index d627285b8081..bc31103e8b92 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -19,8 +19,8 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch-tegra/dc.h> #include <dm/uclass-internal.h> +#include "../tegra_dc.h" #include "displayport.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c index 5bf8524a5e8a..4e97b6de276a 100644 --- a/drivers/video/tegra124/dp.c +++ b/drivers/video/tegra124/dp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013, NVIDIA Corporation. + * Copyright (c) 2011-2016, NVIDIA Corporation. * Copyright 2014 Google Inc. * * SPDX-License-Identifier: GPL-2.0 @@ -13,7 +13,7 @@ #include <fdtdec.h> #include <video_bridge.h> #include <asm/io.h> -#include <asm/arch-tegra/dc.h> +#include "../tegra_dc.h" #include "display.h" #include "edid.h" #include "sor.h" diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index e5cea51d48c8..40d9dd22a2c4 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013, NVIDIA Corporation. + * Copyright (c) 2011-2016, NVIDIA Corporation. * * SPDX-License-Identifier: GPL-2.0 */ @@ -13,7 +13,7 @@ #include <video_bridge.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch-tegra/dc.h> +#include "../tegra_dc.h" #include "displayport.h" #include "sor.h"
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/drivers/video/tegra_dc.h similarity index 94% rename from arch/arm/include/asm/arch-tegra/dc.h rename to drivers/video/tegra_dc.h index 3a7ee5e77baf..77ff2122de3c 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/drivers/video/tegra_dc.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __ASM_ARCH_TEGRA_DC_H -#define __ASM_ARCH_TEGRA_DC_H +#ifndef _VIDEO_TEGRA_DC_H +#define _VIDEO_TEGRA_DC_H
/* Register definitions for the Tegra display controller */
@@ -566,4 +566,26 @@ enum { #define DC_N_WINDOWS 5 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
-#endif /* __ASM_ARCH_TEGRA_DC_H */ +#ifdef CONFIG_TEGRA20 +/* + * I am not sure if this structure actually only applies to Tegra20, or simply + * was only in <arch-tegra20/display.h> and nowhere else for no good reason. + */ +/* This holds information about a window which can be displayed */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + unsigned bpp; /* Bits per pixel */ + phys_addr_t phys_addr; /* Physical address in memory */ + unsigned x; /* Horizontal address offset (bytes) */ + unsigned y; /* Veritical address offset (bytes) */ + unsigned w; /* Width of source window */ + unsigned h; /* Height of source window */ + unsigned stride; /* Number of bytes per line */ + unsigned out_x; /* Left edge of output window (col) */ + unsigned out_y; /* Top edge of output window (row) */ + unsigned out_w; /* Width of output window in pixels */ + unsigned out_h; /* Height of output window in pixels */ +}; +#endif + +#endif
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's dc.h/display.h only contain private definitions for use inside the Tegra display driver. Move them out of the global include directory since nothing needs to access it there. Since they both describe DC registers, combine then into a single header.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra20/display.h | 29 --------------------- arch/arm/mach-tegra/tegra20/display.c | 15 ----------- drivers/video/tegra.c | 3 +-- drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/dp.c | 4 +-- drivers/video/tegra124/sor.c | 4 +-- .../arch-tegra/dc.h => drivers/video/tegra_dc.h | 30 +++++++++++++++++++--- 7 files changed, 32 insertions(+), 55 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h delete mode 100644 arch/arm/mach-tegra/tegra20/display.c rename arch/arm/include/asm/arch-tegra/dc.h => drivers/video/tegra_dc.h (94%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
In most current Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this isn't the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. Update U-Boot's DTs to fix this issue.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra124-nyan-big.dts | 8 +++--- arch/arm/dts/tegra124-nyan.dtsi | 4 +-- arch/arm/dts/tegra210-e2220-1170.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-0000.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-2180.dts | 20 +++++++------- arch/arm/dts/tegra210-p2571.dts | 48 ++++++++++++++++----------------- arch/arm/dts/tegra210.dtsi | 52 ++++++++++++++++++------------------ 7 files changed, 82 insertions(+), 82 deletions(-)
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 20e0be30e980..75821fcda647 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -15,8 +15,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; sdhci0 = "/sdhci@700b0600"; sdhci1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; @@ -58,7 +58,7 @@ ddc-i2c-bus = <&dpaux>; };
- sdhci@0,700b0400 { /* SD Card on this bus */ + sdhci@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; };
@@ -69,7 +69,7 @@ nvidia,model = "GoogleNyanBig"; };
- pinmux@0,70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>;
diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 1b6931fae806..780131f7361c 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -3,8 +3,8 @@
/ { aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; serial0 = &uarta; };
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts index 75efbba1061e..fe27a81e4337 100644 --- a/arch/arm/dts/tegra210-e2220-1170.dts +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -11,34 +11,34 @@ };
aliases { - i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; };
memory { reg = <0x0 0x80000000 0x0 0xc0000000>; };
- sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; };
- sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; };
- i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; };
- usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "peripheral"; }; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 10172a23ad70..3f0e14d62c2c 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -11,34 +11,34 @@ };
aliases { - i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; };
memory { reg = <0x0 0x80000000 0x0 0xc0000000>; };
- sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; };
- sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; };
- i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; };
- usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index bf35497d83f7..c1f40e91e318 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -11,17 +11,17 @@ };
aliases { - i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; };
memory { reg = <0x0 0x80000000 0x0 0xc0000000>; };
- pcie-controller@0,01003000 { + pcie-controller@01003000 { status = "okay";
pci@1,0 { @@ -33,7 +33,7 @@ }; };
- padctl@0,7009f000 { + padctl@7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default";
@@ -71,7 +71,7 @@ }; };
- sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; @@ -79,17 +79,17 @@ bus-width = <4>; };
- sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; };
- i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; };
- usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index de35bba44bef..ca413904964d 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -11,82 +11,82 @@ };
aliases { - i2c0 = "/i2c@0,7000d000"; - i2c1 = "/i2c@0,7000c000"; - i2c2 = "/i2c@0,7000c400"; - i2c3 = "/i2c@0,7000c500"; - i2c4 = "/i2c@0,7000c700"; - i2c5 = "/i2c@0,7000d100"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; - spi0 = "/spi@0,7000d400"; - spi1 = "/spi@0,7000da00"; - spi2 = "/spi@0,70410000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0000"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + spi2 = "/spi@70410000"; + usb0 = "/usb@7d000000"; };
memory { reg = <0x0 0x80000000 0x0 0xc0000000>; };
- i2c@0,7000c000 { + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; };
- i2c@0,7000c400 { + i2c@7000c400 { status = "okay"; clock-frequency = <100000>; };
- i2c@0,7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <100000>; };
- i2c@0,7000c700 { + i2c@7000c700 { status = "okay"; clock-frequency = <100000>; };
- i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; };
- i2c@0,7000d100 { + i2c@7000d100 { status = "okay"; clock-frequency = <400000>; };
- spi@0,7000d400 { + spi@7000d400 { status = "okay"; spi-max-frequency = <25000000>; };
- spi@0,7000da00 { + spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; };
- spi@0,70410000 { + spi@70410000 { status = "okay"; spi-max-frequency = <24000000>; };
- sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; };
- sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; };
- usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; }; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index a8c2f1994ff7..fd4cc793d906 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -12,7 +12,7 @@ #address-cells = <2>; #size-cells = <2>;
- pcie-controller@0,01003000 { + pcie-controller@01003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -78,7 +78,7 @@ }; };
- gic: interrupt-controller@0,50041000 { + gic: interrupt-controller@50041000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; @@ -91,14 +91,14 @@ interrupt-parent = <&gic>; };
- tegra_car: clock@0,60006000 { + tegra_car: clock@60006000 { compatible = "nvidia,tegra210-car"; reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; };
- gpio: gpio@0,6000d000 { + gpio: gpio@6000d000 { compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, @@ -115,7 +115,7 @@ interrupt-controller; };
- i2c@0,7000c000 { + i2c@7000c000 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = <0 38 0x04>; @@ -125,7 +125,7 @@ status = "disabled"; };
- i2c@0,7000c400 { + i2c@7000c400 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = <0 84 0x04>; @@ -135,7 +135,7 @@ status = "disabled"; };
- i2c@0,7000c500 { + i2c@7000c500 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = <0 92 0x04>; @@ -145,7 +145,7 @@ status = "disabled"; };
- i2c@0,7000c700 { + i2c@7000c700 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = <0 120 0x04>; @@ -155,7 +155,7 @@ status = "disabled"; };
- i2c@0,7000d000 { + i2c@7000d000 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = <0 53 0x04>; @@ -165,7 +165,7 @@ status = "disabled"; };
- i2c@0,7000d100 { + i2c@7000d100 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = <0 53 0x04>; @@ -175,7 +175,7 @@ status = "disabled"; };
- uarta: serial@0,70006000 { + uarta: serial@70006000 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; @@ -186,7 +186,7 @@ status = "disabled"; };
- uartb: serial@0,70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; @@ -197,7 +197,7 @@ status = "disabled"; };
- uartc: serial@0,70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; @@ -208,7 +208,7 @@ status = "disabled"; };
- uartd: serial@0,70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; @@ -219,7 +219,7 @@ status = "disabled"; };
- spi@0,7000d400 { + spi@7000d400 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d400 0x0 0x200>; interrupts = <0 59 0x04>; @@ -231,7 +231,7 @@ status = "disabled"; };
- spi@0,7000d600 { + spi@7000d600 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d600 0x0 0x200>; interrupts = <0 82 0x04>; @@ -243,7 +243,7 @@ status = "disabled"; };
- spi@0,7000d800 { + spi@7000d800 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d800 0x0 0x200>; interrupts = <0 83 0x04>; @@ -255,7 +255,7 @@ status = "disabled"; };
- spi@0,7000da00 { + spi@7000da00 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000da00 0x0 0x200>; interrupts = <0 93 0x04>; @@ -267,7 +267,7 @@ status = "disabled"; };
- spi@0,70410000 { + spi@70410000 { compatible = "nvidia,tegra210-qspi"; reg = <0x0 0x70410000 0x0 0x1000>; interrupts = <0 10 0x04>; @@ -277,7 +277,7 @@ status = "disabled"; };
- padctl: padctl@0,7009f000 { + padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; @@ -285,7 +285,7 @@ #phy-cells = <1>; };
- sdhci@0,700b0000 { + sdhci@700b0000 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = <0 14 0x04>; @@ -295,7 +295,7 @@ status = "disabled"; };
- sdhci@0,700b0200 { + sdhci@700b0200 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = <0 15 0x04>; @@ -305,7 +305,7 @@ status = "disabled"; };
- sdhci@0,700b0400 { + sdhci@700b0400 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = <0 19 0x04>; @@ -315,7 +315,7 @@ status = "disabled"; };
- sdhci@0,700b0600 { + sdhci@700b0600 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = <0 31 0x04>; @@ -325,7 +325,7 @@ status = "disabled"; };
- usb@0,7d000000 { + usb@7d000000 { compatible = "nvidia,tegra210-ehci"; reg = <0x0 0x7d000000 0x0 0x4000>; interrupts = <0 20 0x04>; @@ -336,7 +336,7 @@ status = "disabled"; };
- usb@0,7d004000 { + usb@7d004000 { compatible = "nvidia,tegra210-ehci"; reg = <0x0 0x7d004000 0x0 0x4000>; interrupts = < 53 >;
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
In most current Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this isn't the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. Update U-Boot's DTs to fix this issue.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra124-nyan-big.dts | 8 +++--- arch/arm/dts/tegra124-nyan.dtsi | 4 +-- arch/arm/dts/tegra210-e2220-1170.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-0000.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-2180.dts | 20 +++++++------- arch/arm/dts/tegra210-p2571.dts | 48 ++++++++++++++++----------------- arch/arm/dts/tegra210.dtsi | 52 ++++++++++++++++++------------------ 7 files changed, 82 insertions(+), 82 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This complies with my OCD.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra124-nyan-big.dts | 2 +- arch/arm/dts/tegra20-colibri.dts | 2 +- arch/arm/dts/tegra20-harmony.dts | 4 ++-- arch/arm/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/dts/tegra20-paz00.dts | 2 +- arch/arm/dts/tegra20-plutux.dts | 2 +- arch/arm/dts/tegra20-seaboard.dts | 4 ++-- arch/arm/dts/tegra20-tec.dts | 2 +- arch/arm/dts/tegra20-trimslice.dts | 4 ++-- arch/arm/dts/tegra20-ventana.dts | 2 +- arch/arm/dts/tegra20-whistler.dts | 2 +- 11 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 75821fcda647..d41c995dcc14 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -8,7 +8,6 @@
aliases { console = &uarta; - stdout-path = &uarta; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; @@ -17,6 +16,7 @@ i2c5 = "/i2c@7000d100"; rtc0 = "/i2c@7000d000/pmic@40"; rtc1 = "/rtc@7000e000"; + stdout-path = &uarta; sdhci0 = "/sdhci@700b0600"; sdhci1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index 2cf24d3ee771..dbbdd59c82a1 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -14,10 +14,10 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; + sdhci0 = "/sdhci@c8000600"; usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; usb2 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; };
host1x@50000000 { diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 623eb90a8a00..23dbf2ce79ae 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -11,10 +11,10 @@ };
aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5004000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000200"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5004000"; };
memory { diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index 3d37257189e0..f016961f0c45 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -11,8 +11,8 @@ };
aliases { - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; + usb0 = "/usb@c5008000"; };
memory { diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5c7e80558da3..eb451bef019c 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -11,9 +11,9 @@ };
aliases { - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000000"; + usb0 = "/usb@c5008000"; };
memory { diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index 7f57f1d4b573..45acd3a35ef7 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -11,8 +11,8 @@ };
aliases { - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; + usb0 = "/usb@c5008000"; };
memory { diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index eada59073efc..886836bfd41c 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -16,14 +16,14 @@
aliases { /* This defines the order of our ports */ - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000400"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; };
memory { diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 4f68077fafa1..830029741797 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -11,8 +11,8 @@ };
aliases { - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; + usb0 = "/usb@c5008000"; };
memory { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index db13ff965178..1acdd78b5f33 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -11,11 +11,11 @@ };
aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000000"; spi0 = "/spi@7000c380"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; };
memory { diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 851e0ed8d9a4..5047d0982ba9 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -11,9 +11,9 @@ };
aliases { - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000400"; + usb0 = "/usb@c5008000"; };
memory { diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts index 358c5824f7cc..fb6a4fcf9133 100644 --- a/arch/arm/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -12,9 +12,9 @@
aliases { i2c0 = "/i2c@7000d000"; - usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000400"; + usb0 = "/usb@c5008000"; };
memory {
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This complies with my OCD.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra124-nyan-big.dts | 2 +- arch/arm/dts/tegra20-colibri.dts | 2 +- arch/arm/dts/tegra20-harmony.dts | 4 ++-- arch/arm/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/dts/tegra20-paz00.dts | 2 +- arch/arm/dts/tegra20-plutux.dts | 2 +- arch/arm/dts/tegra20-seaboard.dts | 4 ++-- arch/arm/dts/tegra20-tec.dts | 2 +- arch/arm/dts/tegra20-trimslice.dts | 4 ++-- arch/arm/dts/tegra20-ventana.dts | 2 +- arch/arm/dts/tegra20-whistler.dts | 2 +- 11 files changed, 14 insertions(+), 14 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Future Tegra chips contain multiple entirely separate GPIO controllers. It is plausible that boards using those chips will end up with non-DT-driven code that manipulates GPIOs, just like a few Tegra boards do today. In that case, we'll want to make sure that the mapping from the global integer GPIO numbering to GPIO controller occurs in a defined order, so that the right GPIO is chosen in each case. To guarantee that order, GPIO controllers must have specific DM "seq" values. This can be ensured via DT aliases.
This is a no-op for current chips since there's only one GPIO controller. However, it provides a good example for cargo-cult programming:-)
The aliases are added to the SoC DTSI files since there is no need for them to vary between boards, and doing so avoids having to duplicate the entry in each board's DT file. Any additional board-specific GPIO controllers can be referenced by additional aliases (starting at 1) in board DT files if needed.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra114.dtsi | 4 ++++ arch/arm/dts/tegra20.dtsi | 4 ++++ arch/arm/dts/tegra210.dtsi | 4 ++++ arch/arm/dts/tegra30.dtsi | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 88bdc4904508..fd43cb1805aa 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -7,6 +7,10 @@ / { compatible = "nvidia,tegra114";
+ aliases { + gpio0 = "/gpio@6000d000"; + }; + tegra_car: clock { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 31223e4fc9aa..fd1197e73d30 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -9,6 +9,10 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&lic>;
+ aliases { + gpio0 = "/gpio@6000d000"; + }; + host1x@50000000 { u-boot,dm-pre-reloc; compatible = "nvidia,tegra20-host1x", "simple-bus"; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index fd4cc793d906..8f6a30851e21 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -12,6 +12,10 @@ #address-cells = <2>; #size-cells = <2>;
+ aliases { + gpio0 = "/gpio@6000d000"; + }; + pcie-controller@01003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 5ea7e347f3fa..f6d4fd54d4f3 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -8,6 +8,10 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>;
+ aliases { + gpio0 = "/gpio@6000d000"; + }; + intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Future Tegra chips contain multiple entirely separate GPIO controllers. It is plausible that boards using those chips will end up with non-DT-driven code that manipulates GPIOs, just like a few Tegra boards do today. In that case, we'll want to make sure that the mapping from the global integer GPIO numbering to GPIO controller occurs in a defined order, so that the right GPIO is chosen in each case. To guarantee that order, GPIO controllers must have specific DM "seq" values. This can be ensured via DT aliases.
This is a no-op for current chips since there's only one GPIO controller. However, it provides a good example for cargo-cult programming:-)
The aliases are added to the SoC DTSI files since there is no need for them to vary between boards, and doing so avoids having to duplicate the entry in each board's DT file. Any additional board-specific GPIO controllers can be referenced by additional aliases (starting at 1) in board DT files if needed.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra114.dtsi | 4 ++++ arch/arm/dts/tegra20.dtsi | 4 ++++ arch/arm/dts/tegra210.dtsi | 4 ++++ arch/arm/dts/tegra30.dtsi | 4 ++++ 4 files changed, 16 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
TEGRA_PORTS_PER_BANK and TEGRA_GPIO_PORTS represent the same thing. TEGRA_GPIO_PORTS is more widely used, so replace all usage with that, and remove the redundant definition.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/gpio.h | 1 - drivers/gpio/tegra_gpio.c | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index 363d16c486d1..07921f34b9d7 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -9,7 +9,6 @@ #define _TEGRA_GPIO_H_
#define TEGRA_GPIOS_PER_PORT 8 -#define TEGRA_PORTS_PER_BANK 4
#define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 5a031159ca37..9abab13daaa9 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -1,6 +1,6 @@ /* * NVIDIA Tegra20 GPIO handling. - * (C) Copyright 2010-2012,2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -346,7 +346,7 @@ static int gpio_tegra_bind(struct udevice *parent) for (bank = 0; bank < bank_count; bank++) { int port;
- for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { + for (port = 0; port < TEGRA_GPIO_PORTS; port++) { struct tegra_gpio_platdata *plat; struct udevice *dev; int base_port; @@ -355,7 +355,7 @@ static int gpio_tegra_bind(struct udevice *parent) if (!plat) return -ENOMEM; plat->bank = &ctlr->gpio_bank[bank]; - base_port = bank * TEGRA_PORTS_PER_BANK + port; + base_port = bank * TEGRA_GPIO_PORTS + port; plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; plat->port_name = gpio_port_name(base_port);
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
TEGRA_PORTS_PER_BANK and TEGRA_GPIO_PORTS represent the same thing. TEGRA_GPIO_PORTS is more widely used, so replace all usage with that, and remove the redundant definition.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/gpio.h | 1 - drivers/gpio/tegra_gpio.c | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
The order is general includes, general asm includes, arch asm includes, local files.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/avionic-design/common/tamonten-ng.c | 5 +++-- board/nvidia/cardhu/cardhu.c | 6 +++--- board/nvidia/jetson-tk1/jetson-tk1.c | 4 +--- board/nvidia/nyan-big/nyan-big.c | 6 +++--- board/nvidia/p2571/p2571.c | 4 ++-- board/nvidia/seaboard/seaboard.c | 6 +++--- board/toradex/colibri_t20/colibri_t20.c | 6 +++--- board/toradex/colibri_t30/colibri_t30.c | 6 +++--- 8 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 170462711264..352f5d7ba5d1 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -1,18 +1,19 @@ /* * (C) Copyright 2013 * Avionic Design GmbH <www.avionic-design.de> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-tamonten-ng.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ba15e2e6cf0c..ffa74a3e8acb 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2013 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,12 +7,12 @@
#include <common.h> #include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-cardhu.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index a66b710cddab..05f847e7f430 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,10 +7,8 @@
#include <common.h> #include <power/as3722.h> - #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> - #include "pinmux-config-jetson-tk1.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ba964018901a..8fef0d3d91a9 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +7,8 @@
#include <common.h> #include <errno.h> +#include <power/as3722.h> +#include <power/pmic.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/pinmux.h> @@ -14,8 +16,6 @@ #include <asm/arch/mc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <power/as3722.h> -#include <power/pmic.h> #include "pinmux-config-nyan-big.h"
/* diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index d80a7d0d3e31..32c8da552b85 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,9 +7,9 @@
#include <common.h> #include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> -#include <asm/gpio.h> #include "max77620_init.h" #include "pinmux-config-p2571.h"
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 2d07001800e3..a8300742eed3 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -1,19 +1,19 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> -#include <asm/gpio.h> +#include <asm/arch-tegra/board.h>
/* TODO: Remove this code when the SPI switch is working */ #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index b9f845a09b6a..74421819d0f0 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -6,14 +6,14 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/tegra.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 3902bff203d5..413cf1b498fe 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -7,12 +7,12 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <asm/io.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <i2c.h> #include "pinmux-config-colibri_t30.h"
int arch_misc_init(void)
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
The order is general includes, general asm includes, arch asm includes, local files.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten-ng.c | 5 +++-- board/nvidia/cardhu/cardhu.c | 6 +++--- board/nvidia/jetson-tk1/jetson-tk1.c | 4 +--- board/nvidia/nyan-big/nyan-big.c | 6 +++--- board/nvidia/p2571/p2571.c | 4 ++-- board/nvidia/seaboard/seaboard.c | 6 +++--- board/toradex/colibri_t20/colibri_t20.c | 6 +++--- board/toradex/colibri_t30/colibri_t30.c | 6 +++--- 8 files changed, 21 insertions(+), 22 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Dear Stephen,
In message 1461099580-3866-14-git-send-email-swarren@wwwdotorg.org you wrote:
--- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -1,18 +1,19 @@ /*
- (C) Copyright 2013
- Avionic Design GmbH <www.avionic-design.de>
*/
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
#include <common.h> #include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-tamonten-ng.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D
Do you really think that moving around two lines of code is a big enough creative achievement to justify adding a copyright note on it?
And even with "All rights reserved."?
I stop reviewing this patch set here. I'm sorry, but I really dislike the way how it - intentionally or unintentionally - appears to be driven by the attempt to increase Nvidias presence in copyright claims.
This seems not fair to me, and I would like to ask you to rework this whole patch set and be a little less aggressive in copyright claims.
Thanks in advance.
Best regards,
Wolfgang Denk
On 04/24/2016 04:20 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 1461099580-3866-14-git-send-email-swarren@wwwdotorg.org you wrote:
--- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -1,18 +1,19 @@ /*
- (C) Copyright 2013
- Avionic Design GmbH <www.avionic-design.de>
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h> #include <dm.h>
+#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-tamonten-ng.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D
Do you really think that moving around two lines of code is a big enough creative achievement to justify adding a copyright note on it?
My understanding is yes; I edited the file in a non-trival way and so NVIDIA's copyright applies to those portions. I'd consider whitespace or spelling fixes to be trivial, but not much else. I believe there is creative achievement in cleaning up the code-base this way.
Of course, I'm not a lawyer and I'm sure there are plenty of lawyers who could argue either way, perhaps depending on who pays them:-)
I'm sorry, but I really dislike the way how it - intentionally or unintentionally - appears to be driven by the attempt to increase Nvidias presence in copyright claims.
FWIW, the purpose is to create a cleaner separate between the core Tegra SoC support code and board/driver code, to reduce their current rather tight coupling. The copyright changes are just correct application of the process of editing files; something I admit we/I've been a bit lax about in the past.
This seems not fair to me, and I would like to ask you to rework this whole patch set and be a little less aggressive in copyright claims.
I don't see what's unfair either way. As far as I'm concerned, the copyright notices are simply due to my following the process I must follow. I don't believe the presence of NVIDIA's copyright notices takes anything away from anyone else, and as I mentioned above, they seem valid to me.
Dear Stephen,
In message 571E75E2.6020008@wwwdotorg.org you wrote:
/*
- (C) Copyright 2013
- Avionic Design GmbH <www.avionic-design.de>
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h> #include <dm.h>
+#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-tamonten-ng.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D
Do you really think that moving around two lines of code is a big enough creative achievement to justify adding a copyright note on it?
My understanding is yes; I edited the file in a non-trival way and so NVIDIA's copyright applies to those portions. I'd consider whitespace or spelling fixes to be trivial, but not much else. I believe there is creative achievement in cleaning up the code-base this way.
Well, do you _really_ mean that moving two ines of code a few lines up is a non-trivial change? Sorry, but I strongly disagree here.
This is not any change where you can claim any copyright for.
FWIW, the purpose is to create a cleaner separate between the core Tegra SoC support code and board/driver code, to reduce their current rather tight coupling. The copyright changes are just correct application of the process of editing files; something I admit we/I've been a bit lax about in the past.
s/correct/aggressive/
This seems not fair to me, and I would like to ask you to rework this whole patch set and be a little less aggressive in copyright claims.
I don't see what's unfair either way. As far as I'm concerned, the copyright notices are simply due to my following the process I must follow. I don't believe the presence of NVIDIA's copyright notices takes anything away from anyone else, and as I mentioned above, they seem valid to me.
Well, if I read the code before and after your changes, I see a lot of places where new copyright notes appear in prominent places, and some old ones are gone, or are now just an also-ran.
I do not think that this is your intention, but it is how this appears to me, and I really dislike it. It expresses an attitude I dislike.
Best regards,
Wolfgang Denk
On Mon, Apr 25, 2016 at 11:59:39PM +0200, Wolfgang Denk wrote:
Dear Stephen,
In message 571E75E2.6020008@wwwdotorg.org you wrote:
/*
- (C) Copyright 2013
- Avionic Design GmbH <www.avionic-design.de>
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h> #include <dm.h>
+#include <i2c.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/gpio.h> #include "pinmux-config-tamonten-ng.h" -#include <i2c.h>
#define PMU_I2C_ADDRESS 0x2D
Do you really think that moving around two lines of code is a big enough creative achievement to justify adding a copyright note on it?
My understanding is yes; I edited the file in a non-trival way and so NVIDIA's copyright applies to those portions. I'd consider whitespace or spelling fixes to be trivial, but not much else. I believe there is creative achievement in cleaning up the code-base this way.
Well, do you _really_ mean that moving two ines of code a few lines up is a non-trivial change? Sorry, but I strongly disagree here.
I want to echo my agreement on this point. Re-ordering includes does not rise to the level of adding copyright/author/etc lines. This is not the old days before various OSS projects used some sort of SCM and the only way you could show people you did X was to have your name somewhere.
Lawyers can argue, but projects have guidelines. I mean heck, I've see you remind people to fix the include order in new patches. Do they need to add an NVIDIA copyright notice too? No, of course not. Now, if your legal department is going to say that every change you make must include a new copyright notice, I'll be very sad and have to ask you to limit those kind of small clean-ups to places that already have a notice on them for NVIDIA.
This is not any change where you can claim any copyright for.
FWIW, the purpose is to create a cleaner separate between the core Tegra SoC support code and board/driver code, to reduce their current rather tight coupling. The copyright changes are just correct application of the process of editing files; something I admit we/I've been a bit lax about in the past.
I applaud re-organizing the code and making sure customer boards continue to work. But by that same token I do not know how Siemens would feel if I added TI notices to their platforms back when I was at TI and cleaning up and working on the SoC side of things. So it's not just NVIDIA legal and community folks that you need to consider here.
s/correct/aggressive/
This seems not fair to me, and I would like to ask you to rework this whole patch set and be a little less aggressive in copyright claims.
I don't see what's unfair either way. As far as I'm concerned, the copyright notices are simply due to my following the process I must follow. I don't believe the presence of NVIDIA's copyright notices takes anything away from anyone else, and as I mentioned above, they seem valid to me.
I know company lawyers come up with various policies and some are more restrictive than others. Anything about the exact guidelines you can share would be appreciated.
On 04/25/2016 05:22 PM, Tom Rini wrote: ...
I know company lawyers come up with various policies and some are more restrictive than others. Anything about the exact guidelines you can share would be appreciated.
They're simple and I would assume quite standard:
1) When creating a new file, add an NVIDIA copyright header.
2) When performing a non-trival edit to an existing file, if it has an existing NVIDIA copyright header, update the data, and if not, add one.
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
Re-ordering your email slightly:
I want to echo my agreement on this point. Re-ordering includes does not rise to the level of adding copyright/author/etc lines.
I can see your argument re: copyright headers in the individual files, although again I'd echo my previous comments re: a simple and unambiguous process being preferable.
However, I don't agree with that argument for the patch/series overall; it's certainly a creative process with work behind it to decide upon and implement the overall operation. But, if the changes to every individual file are trivial and the real work is in the idea (of the appropriate directory organization/separation) itself, there's nowhere left to represent that. Perhaps copyright should be applied to the patch as a whole, and represented in the patch description, rather than individual files in this case. I don't imagine that would satisfy lawyers though, since e.g. .tar distributions would not contain that meta-data. I wonder if an overall README listing all copyright holders and saying "for details, see git log" would be satisfactory to them, at least for "cleanup style" commits.
Dear Stephen,
In message 571F94BE.2030106@wwwdotorg.org you wrote:
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
recommended search term: Copyright Creativity Requirement
Best regards,
Wolfgang Denk
In message 20160426181301.92F78100386@atlas.denx.de I wrote:
Dear Stephen,
In message 571F94BE.2030106@wwwdotorg.org you wrote:
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
recommended search term: Copyright Creativity Requirement
Quoting from [1]:
4.1 Non-trivial originality (Durham)
In Durham Industries, Inc. v. Tomy Corp.,21 the Second Circuit Court of Appeals stated that copyright’s applicability to derivative works is subject to the limitation that “the original aspects of a derivative work must be more than trivial.” ... However, the Alfred Bell court considered non-trivial variation to be a requirement of the originality standard, and merely a restatement of the principle that, to be original, a work must be “recognizably [the author’s] own.” ...
4.2 Substantial difference (Gracen)
[1] https://softwarefreedom.org/resources/2007/originality-requirements.html
Best regards,
Wolfgang Denk
On Tue, Apr 26, 2016 at 10:18:06AM -0600, Stephen Warren wrote:
On 04/25/2016 05:22 PM, Tom Rini wrote: ...
I know company lawyers come up with various policies and some are more restrictive than others. Anything about the exact guidelines you can share would be appreciated.
They're simple and I would assume quite standard:
When creating a new file, add an NVIDIA copyright header.
When performing a non-trival edit to an existing file, if it has
an existing NVIDIA copyright header, update the data, and if not, add one.
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
Re-ordering your email slightly:
I want to echo my agreement on this point. Re-ordering includes does not rise to the level of adding copyright/author/etc lines.
I can see your argument re: copyright headers in the individual files, although again I'd echo my previous comments re: a simple and unambiguous process being preferable.
Here's where I hope I don't get everyone at NVIDIA that's doing Linux Kernel or other F/OSS work in trouble. Point #1 above is quite understandable. Point #2 is something I can see but has totally not been done by the folks doing Linux Kernel work.
What I do not want to see is a changing of the norms and when possible and makes sense, a deviation from the norms of the Linux Kernel. And that would be that you have to make a pretty huge change (at which point for maintainability and refactoring and so forth, it's probably a new file or set of new files) to add a Copyright line to an existing file. But we're not the kernel, true. But looking over the current changes for the year, same thing.
Now, if you want to instead make the point that in various cases fileB.c is based heavily on fileA.c and the copyright was missing on fileA.c when fileB.c was made, that makes sense. Or if they dropped the copyright line (and we assume no malice), add it back in.
But I do not want to see the threshold for "add your copyright to a file" be set at "made a non-whitespace/non-typo change".
However, I don't agree with that argument for the patch/series overall; it's certainly a creative process with work behind it to decide upon and implement the overall operation. But, if the changes to every individual file are trivial and the real work is in the idea (of the appropriate directory organization/separation) itself, there's nowhere left to represent that. Perhaps copyright should be applied to the patch as a whole, and represented in the patch description, rather than individual files in this case. I don't imagine that would satisfy lawyers though, since e.g. .tar distributions would not contain that meta-data. I wonder if an overall README listing all copyright holders and saying "for details, see git log" would be satisfactory to them, at least for "cleanup style" commits.
The review on this patch series itself has indeed been derailed, which I do not like either. With respect to copyright on individual changes and so forth, is this a concern you have, or a concern the lawyers at NVIDIA have?
On 04/26/2016 12:15 PM, Tom Rini wrote:
On Tue, Apr 26, 2016 at 10:18:06AM -0600, Stephen Warren wrote:
On 04/25/2016 05:22 PM, Tom Rini wrote: ...
I know company lawyers come up with various policies and some are more restrictive than others. Anything about the exact guidelines you can share would be appreciated.
They're simple and I would assume quite standard:
When creating a new file, add an NVIDIA copyright header.
When performing a non-trival edit to an existing file, if it has
an existing NVIDIA copyright header, update the data, and if not, add one.
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
Re-ordering your email slightly:
I want to echo my agreement on this point. Re-ordering includes does not rise to the level of adding copyright/author/etc lines.
I can see your argument re: copyright headers in the individual files, although again I'd echo my previous comments re: a simple and unambiguous process being preferable.
Here's where I hope I don't get everyone at NVIDIA that's doing Linux Kernel or other F/OSS work in trouble. Point #1 above is quite understandable. Point #2 is something I can see but has totally not been done by the folks doing Linux Kernel work.
Admittedly compliance is spotty; the last thing someone wants to do when having completed a patch is think about all kinds of nit-picks like updating copyrights, checkpatch, testing, even compiling:-)
However, it's certainly not unheard of. Here are a few examples I was able to spot quickly:
NVIDIA: af6313d61a78 (Alex Courbot) 08acae34e8da (Paul Walsmley) 891846516317 (Thierry Reding) 783c8f4c8445 (Peter De Schrijver) 0ffdd4b61b13 (Stephen Warren)
Red Hat 1363074667a6 (Hans De Goede) 25462f7f5295 (Wei Huang) 54cea3f6681a (Milan Broz)
Texas Instruments 2f67864b6d5b (Andrew F. Davis) 0d6fa53fd805 (Andy Gross)
Denx 88eeb72ec4c1 (Stefan Roese)
Admittedly those don't look like refactoring changes, but it sounded to me like you were arguing completely against point (2) in my original email above. That's not reasonable. Arguing against (2) for simple refactoring could be.
The review on this patch series itself has indeed been derailed, which I do not like either. With respect to copyright on individual changes and so forth, is this a concern you have, or a concern the lawyers at NVIDIA have?
The lawyers have dictated the process which I should follow. I often forget, so I made sure that for such a large series I'd follow the process correctly this time. To be honest, I'm way beyond care about anything to do with copyright at this point; I'd rather just work on something where it wasn't an issue in any form at all.
On Tue, Apr 26, 2016 at 02:44:24PM -0600, Stephen Warren wrote:
On 04/26/2016 12:15 PM, Tom Rini wrote:
On Tue, Apr 26, 2016 at 10:18:06AM -0600, Stephen Warren wrote:
On 04/25/2016 05:22 PM, Tom Rini wrote: ...
I know company lawyers come up with various policies and some are more restrictive than others. Anything about the exact guidelines you can share would be appreciated.
They're simple and I would assume quite standard:
When creating a new file, add an NVIDIA copyright header.
When performing a non-trival edit to an existing file, if it has
an existing NVIDIA copyright header, update the data, and if not, add one.
Guidance on "non-trivial" isn't given. I would take it to mean anything other than typos and whitespace fixes.
Re-ordering your email slightly:
I want to echo my agreement on this point. Re-ordering includes does not rise to the level of adding copyright/author/etc lines.
I can see your argument re: copyright headers in the individual files, although again I'd echo my previous comments re: a simple and unambiguous process being preferable.
Here's where I hope I don't get everyone at NVIDIA that's doing Linux Kernel or other F/OSS work in trouble. Point #1 above is quite understandable. Point #2 is something I can see but has totally not been done by the folks doing Linux Kernel work.
Admittedly compliance is spotty; the last thing someone wants to do when having completed a patch is think about all kinds of nit-picks like updating copyrights, checkpatch, testing, even compiling:-)
However, it's certainly not unheard of. Here are a few examples I was able to spot quickly:
NVIDIA: af6313d61a78 (Alex Courbot) 08acae34e8da (Paul Walsmley) 891846516317 (Thierry Reding) 783c8f4c8445 (Peter De Schrijver) 0ffdd4b61b13 (Stephen Warren)
Red Hat 1363074667a6 (Hans De Goede) 25462f7f5295 (Wei Huang) 54cea3f6681a (Milan Broz)
Texas Instruments 2f67864b6d5b (Andrew F. Davis) 0d6fa53fd805 (Andy Gross)
Denx 88eeb72ec4c1 (Stefan Roese)
Admittedly those don't look like refactoring changes, but it sounded to me like you were arguing completely against point (2) in my original email above. That's not reasonable. Arguing against (2) for simple refactoring could be.
I'm arguing in favour of what all of those commits did, extending existing copyright notices. I'm fine with that. To be clear, in _this_ patch what I object to is adding the NVIDIA copyright line to board/avionic-design/common/tamonten-ng.c and I am fine with extending it on all of the board/nvidia/ files and now wondering you didn't add it to board/toradex/.
The review on this patch series itself has indeed been derailed, which I do not like either. With respect to copyright on individual changes and so forth, is this a concern you have, or a concern the lawyers at NVIDIA have?
The lawyers have dictated the process which I should follow. I often forget, so I made sure that for such a large series I'd follow the process correctly this time. To be honest, I'm way beyond care about anything to do with copyright at this point; I'd rather just work on something where it wasn't an issue in any form at all.
Indeed :(
On 04/25/2016 05:22 PM, Tom Rini wrote:
Lawyers can argue, but projects have guidelines. I mean heck, I've see you remind people to fix the include order in new patches. Do they need to add an NVIDIA copyright notice too? No, of course not.
Well honestly all patch review does contribute to the creative process and affect the final result, so I don't actually think it'd be that much of a stretch that a reviewer's copyright applies to the final patch; they were involved in the creation of it. Perhaps Reviewed-by tags or the mailing list history would be enough evidence of this though, if such were needed later.
On Tue, Apr 26, 2016 at 10:23:36AM -0600, Stephen Warren wrote:
On 04/25/2016 05:22 PM, Tom Rini wrote:
Lawyers can argue, but projects have guidelines. I mean heck, I've see you remind people to fix the include order in new patches. Do they need to add an NVIDIA copyright notice too? No, of course not.
Well honestly all patch review does contribute to the creative process and affect the final result, so I don't actually think it'd be that much of a stretch that a reviewer's copyright applies to the final patch; they were involved in the creation of it. Perhaps Reviewed-by tags or the mailing list history would be enough evidence of this though, if such were needed later.
And this is why I love patchwork and hope that as it starts to handle series more directly it will also handle "For the series, ..." messages in addition to collecting up Acked/Reviewed/Tested by lines. These are important for history of changes to the codebase.
From: Stephen Warren swarren@nvidia.com
There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra124/gpio.h | 261 +-------------------- arch/arm/include/asm/arch-tegra20/gpio.h | 229 +----------------- arch/arm/include/asm/arch-tegra210/gpio.h | 261 +-------------------- arch/arm/include/asm/arch-tegra30/gpio.h | 253 +------------------- board/avionic-design/common/tamonten-ng.c | 14 +- board/avionic-design/common/tamonten.c | 5 +- board/nvidia/cardhu/cardhu.c | 6 +- board/nvidia/e2220-1170/e2220-1170.c | 3 +- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 122 +++++----- board/nvidia/jetson-tk1/jetson-tk1.c | 1 + board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 106 ++++----- board/nvidia/nyan-big/nyan-big.c | 6 +- board/nvidia/nyan-big/pinmux-config-nyan-big.h | 98 ++++---- board/nvidia/p2371-0000/p2371-0000.c | 3 +- board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 104 ++++---- board/nvidia/p2371-2180/p2371-2180.c | 3 +- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 126 +++++----- board/nvidia/p2571/p2571.c | 5 +- board/nvidia/p2571/pinmux-config-p2571.h | 54 ++--- board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/venice2/pinmux-config-venice2.h | 120 +++++----- board/nvidia/venice2/venice2.c | 3 +- board/toradex/colibri_t20/colibri_t20.c | 7 +- board/toradex/colibri_t30/colibri_t30.c | 7 +- 24 files changed, 409 insertions(+), 1394 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h index 1a6dcb8715d3..8fddb63f44c2 100644 --- a/arch/arm/include/asm/arch-tegra124/gpio.h +++ b/arch/arm/include/asm/arch-tegra124/gpio.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -41,263 +41,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
-enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, - GPIO_PFF0, /* pin 248 */ - GPIO_PFF1, - GPIO_PFF2, - GPIO_PFF3, - GPIO_PFF4, - GPIO_PFF5, - GPIO_PFF6, - GPIO_PFF7, /* pin 255 */ -}; - #endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h index b40b1ff9c512..46dcc28f727c 100644 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ b/arch/arm/include/asm/arch-tegra20/gpio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011, Google Inc. All rights reserved. - * Portions Copyright 2011-2012 NVIDIA Corporation + * Portions Copyright 2011-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -33,231 +33,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
-enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, /* pin 223 */ -}; - #endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h index 71af423956f7..f2279d0f3e92 100644 --- a/arch/arm/include/asm/arch-tegra210/gpio.h +++ b/arch/arm/include/asm/arch-tegra210/gpio.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -41,263 +41,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
-enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, - GPIO_PFF0, /* pin 248 */ - GPIO_PFF1, - GPIO_PFF2, - GPIO_PFF3, - GPIO_PFF4, - GPIO_PFF5, - GPIO_PFF6, - GPIO_PFF7, /* pin 255 */ -}; - #endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h index d2c6c78e08b3..288451df2ff6 100644 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ b/arch/arm/include/asm/arch-tegra30/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -40,255 +40,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
-enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, /* pin 247 */ -}; - #endif /* _TEGRA30_GPIO_H_ */ diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 352f5d7ba5d1..aa1fd0ebce1e 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -9,10 +9,10 @@ #include <common.h> #include <dm.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/gpio.h> #include "pinmux-config-tamonten-ng.h"
#define PMU_I2C_ADDRESS 0x2D @@ -43,12 +43,12 @@ void pinmux_init(void) void gpio_early_init(void) { /* Turn on the alive signal */ - gpio_request(GPIO_PV2, "ALIVE"); - gpio_direction_output(GPIO_PV2, 1); + gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); + gpio_direction_output(TEGRA_GPIO(V, 2), 1);
/* Remove the reset on the external periph */ - gpio_request(GPIO_PI4, "nRST_PERIPH"); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH"); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); }
void pmu_write(uchar reg, uchar data) @@ -74,8 +74,8 @@ void board_sdmmc_voltage_init(void) pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
/* Switch the power on */ - gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); - gpio_direction_output(GPIO_PJ2, 1); + gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC"); + gpio_direction_output(TEGRA_GPIO(J, 2), 1); }
/* diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 981862ce1aff..c05113c1c36c 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -9,6 +9,7 @@
#include <common.h> #include <ns16550.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> @@ -22,8 +23,8 @@ #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) { - gpio_request(GPIO_PI4, NULL); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), NULL); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } #endif
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ffa74a3e8acb..ff46e0cf0419 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -8,10 +8,10 @@ #include <common.h> #include <dm.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/gpio.h> #include "pinmux-config-cardhu.h"
#define PMU_I2C_ADDRESS 0x2D @@ -110,11 +110,11 @@ int tegra_pcie_board_init(void) }
/* GPIO: PEX = 3.3V */ - err = gpio_request(GPIO_PL7, "PEX"); + err = gpio_request(TEGRA_GPIO(L, 7), "PEX"); if (err < 0) return err;
- gpio_direction_output(GPIO_PL7, 1); + gpio_direction_output(TEGRA_GPIO(L, 7), 1);
/* TPS659110: LDO2_REG = 1.05V, ACTIVE */ data[0] = 0x15; diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index d66a72e5204c..db6fa74ae1fe 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +7,7 @@
#include <common.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include "../p2571/max77620_init.h" diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h index 7eb1e6c1b3e9..f943fcf536d7 100644 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,71 +15,71 @@ #ifndef _PINMUX_CONFIG_E2220_1170_H_ #define _PINMUX_CONFIG_E2220_1170_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(A6, IN), - GPIO_INIT(B4, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(G2, OUT0), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, OUT0), - GPIO_INIT(K3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB4, IN), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(A, 6, IN), + GPIO_INIT(B, 4, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 2, OUT0), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, OUT0), + GPIO_INIT(K, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 4, IN), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 5, OUT0), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 05f847e7f430..4b7058e3bc89 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 00e0cdc4b8c0..416d9cfdca0c 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,63 +15,63 @@ #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(G4, IN), - GPIO_INIT(H2, OUT0), - GPIO_INIT(H4, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(N7, IN), - GPIO_INIT(O1, IN), - GPIO_INIT(O4, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q5, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R2, OUT0), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S7, IN), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, IN), - GPIO_INIT(U0, IN), - GPIO_INIT(U1, IN), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB5, OUT0), - GPIO_INIT(BB6, OUT0), - GPIO_INIT(BB7, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC2, IN), - GPIO_INIT(EE2, OUT1), + /* port, pin, init_val */ + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(G, 4, IN), + GPIO_INIT(H, 2, OUT0), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 1, IN), + GPIO_INIT(O, 4, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 5, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 2, OUT0), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 0, IN), + GPIO_INIT(U, 1, IN), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 5, OUT0), + GPIO_INIT(BB, 6, OUT0), + GPIO_INIT(BB, 7, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 2, IN), + GPIO_INIT(EE, 2, OUT1), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 8fef0d3d91a9..56e15bda93ec 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -7,6 +7,7 @@
#include <common.h> #include <errno.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> #include <power/pmic.h> #include <asm/gpio.h> @@ -36,8 +37,9 @@ void pinmux_init(void)
int tegra_board_id(void) { - static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1, - GPIO_PX4, -1}; + static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1), + TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4), + -1};
gpio_claim_vector(vector, "board_id%d"); return gpio_get_values_as_int(vector); diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index dca0171f26b3..583fc15e73f2 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,59 +15,59 @@ #ifndef _PINMUX_CONFIG_NYAN_BIG_H_ #define _PINMUX_CONFIG_NYAN_BIG_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config nyan_big_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(I7, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(I, 7, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index 9df543a4c9e8..0fec3d497d7d 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +7,7 @@
#include <common.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include "../p2571/max77620_init.h" diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h index 35706b47454d..54cdcc8bd84e 100644 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,62 +15,62 @@ #ifndef _PINMUX_CONFIG_P2371_0000_H_ #define _PINMUX_CONFIG_P2371_0000_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(E6, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(V7, OUT1), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(V, 7, OUT1), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa796..bc3389976942 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +7,7 @@
#include <common.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include "../p2571/max77620_init.h" diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h index d5be6ecda93e..904c4a4b0401 100644 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,73 +15,73 @@ #ifndef _PINMUX_CONFIG_P2371_2180_H_ #define _PINMUX_CONFIG_P2371_2180_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(B0, IN), - GPIO_INIT(B1, IN), - GPIO_INIT(B2, IN), - GPIO_INIT(B3, IN), - GPIO_INIT(C0, IN), - GPIO_INIT(C1, IN), - GPIO_INIT(C2, IN), - GPIO_INIT(C3, IN), - GPIO_INIT(C4, IN), - GPIO_INIT(E4, IN), - GPIO_INIT(E5, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, IN), - GPIO_INIT(L1, IN), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z2, IN), - GPIO_INIT(Z3, OUT0), - GPIO_INIT(BB0, IN), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, IN), - GPIO_INIT(CC1, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(B, 0, IN), + GPIO_INIT(B, 1, IN), + GPIO_INIT(B, 2, IN), + GPIO_INIT(B, 3, IN), + GPIO_INIT(C, 0, IN), + GPIO_INIT(C, 1, IN), + GPIO_INIT(C, 2, IN), + GPIO_INIT(C, 3, IN), + GPIO_INIT(C, 4, IN), + GPIO_INIT(E, 4, IN), + GPIO_INIT(E, 5, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, IN), + GPIO_INIT(L, 1, IN), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 2, IN), + GPIO_INIT(Z, 3, OUT0), + GPIO_INIT(BB, 0, IN), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, IN), + GPIO_INIT(CC, 1, IN), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 32c8da552b85..794830bac3b3 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -7,6 +7,7 @@
#include <common.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> @@ -58,6 +59,6 @@ void pinmux_init(void) void start_cpu_fan(void) { /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ - gpio_request(GPIO_PE4, "FAN_VDD"); - gpio_direction_output(GPIO_PE4, 1); + gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD"); + gpio_direction_output(TEGRA_GPIO(E, 4), 1); } diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d3233016b52b..179f3d424a89 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,37 +15,37 @@ #ifndef _PINMUX_CONFIG_P2571_H_ #define _PINMUX_CONFIG_P2571_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config p2571_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(A5, IN), - GPIO_INIT(D4, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(G0, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V6, OUT1), - GPIO_INIT(X4, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC3, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(A, 5, IN), + GPIO_INIT(D, 4, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(G, 0, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 6, OUT1), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 3, IN), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index a8300742eed3..9c92fc2e29e2 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -6,12 +6,12 @@ */
#include <common.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/board.h>
@@ -20,8 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, "uart_en"); - gpio_direction_output(GPIO_PI3, 0); + gpio_request(TEGRA_GPIO(I, 3), "uart_en"); + gpio_direction_output(TEGRA_GPIO(I, 3), 0); } #endif
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index fb444b3b1dd6..585592b35604 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,70 +15,70 @@ #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_
-#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ }
static const struct tegra_gpio_config venice2_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(CC5, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 5, OUT0), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 4, OUT0), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 3, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 2, IN), + GPIO_INIT(O, 5, IN), + GPIO_INIT(O, 6, OUT0), + GPIO_INIT(O, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(S, 0, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(CC, 5, OUT0), };
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index c56ef129d6c7..4373de6a26bd 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -1,11 +1,12 @@ /* - * (C) Copyright 2013-2014 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include "pinmux-config-venice2.h" diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 74421819d0f0..e47565fa6389 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <i2c.h> #include <asm/gpio.h> #include <asm/io.h> @@ -103,11 +104,11 @@ void pin_mux_usb(void) pinmux_tristate_disable(PMUX_PINGRP_DTE);
/* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PV4, "LAN_RESET"); - gpio_direction_output(GPIO_PV4, 0); + gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(V, 4), 0); pinmux_tristate_disable(PMUX_PINGRP_GPV); udelay(5); - gpio_set_value(GPIO_PV4, 1); + gpio_set_value(TEGRA_GPIO(V, 4), 1);
/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 413cf1b498fe..4312f79f2d00 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -8,6 +8,7 @@
#include <common.h> #include <i2c.h> +#include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/gp_padctrl.h> @@ -47,8 +48,8 @@ void pinmux_init(void) void pin_mux_usb(void) { /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PDD0, "LAN_RESET"); - gpio_direction_output(GPIO_PDD0, 0); + gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(DD, 0), 0); udelay(5); - gpio_set_value(GPIO_PDD0, 1); + gpio_set_value(TEGRA_GPIO(DD, 0), 1); }
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra124/gpio.h | 261 +-------------------- arch/arm/include/asm/arch-tegra20/gpio.h | 229 +----------------- arch/arm/include/asm/arch-tegra210/gpio.h | 261 +-------------------- arch/arm/include/asm/arch-tegra30/gpio.h | 253 +------------------- board/avionic-design/common/tamonten-ng.c | 14 +- board/avionic-design/common/tamonten.c | 5 +- board/nvidia/cardhu/cardhu.c | 6 +- board/nvidia/e2220-1170/e2220-1170.c | 3 +- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 122 +++++----- board/nvidia/jetson-tk1/jetson-tk1.c | 1 + board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 106 ++++----- board/nvidia/nyan-big/nyan-big.c | 6 +- board/nvidia/nyan-big/pinmux-config-nyan-big.h | 98 ++++---- board/nvidia/p2371-0000/p2371-0000.c | 3 +- board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 104 ++++---- board/nvidia/p2371-2180/p2371-2180.c | 3 +- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 126 +++++----- board/nvidia/p2571/p2571.c | 5 +- board/nvidia/p2571/pinmux-config-p2571.h | 54 ++--- board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/venice2/pinmux-config-venice2.h | 120 +++++----- board/nvidia/venice2/venice2.c | 3 +- board/toradex/colibri_t20/colibri_t20.c | 7 +- board/toradex/colibri_t30/colibri_t30.c | 7 +- 24 files changed, 409 insertions(+), 1394 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra114/gpio.h | 20 ------ arch/arm/include/asm/arch-tegra124/gpio.h | 44 ------------- arch/arm/include/asm/arch-tegra20/gpio.h | 36 ---------- arch/arm/include/asm/arch-tegra210/gpio.h | 44 ------------- arch/arm/include/asm/arch-tegra30/gpio.h | 43 ------------ arch/arm/include/asm/gpio.h | 2 +- .../include/mach/tegra_gpio.h} | 13 +--- board/nvidia/e2220-1170/e2220-1170.c | 3 +- board/nvidia/jetson-tk1/jetson-tk1.c | 3 +- board/nvidia/nyan-big/nyan-big.c | 1 + board/nvidia/p2371-0000/p2371-0000.c | 3 +- board/nvidia/p2371-2180/p2371-2180.c | 3 +- board/nvidia/p2571/p2571.c | 2 +- board/nvidia/venice2/venice2.c | 3 +- drivers/gpio/tegra_gpio.c | 2 + drivers/gpio/tegra_gpio_priv.h | 76 ++++++++++++++++++++++ drivers/i2c/tegra_i2c.c | 1 - 17 files changed, 94 insertions(+), 205 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra20/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gpio.h rename arch/arm/{include/asm/arch-tegra/gpio.h => mach-tegra/include/mach/tegra_gpio.h} (67%) create mode 100644 drivers/gpio/tegra_gpio_priv.h
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h deleted file mode 100644 index d6eaa1bd40e8..000000000000 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA114_GPIO_H_ -#define _TEGRA114_GPIO_H_ - -/* - * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> -#include <asm/arch-tegra30/gpio.h> - -#endif /* _TEGRA114_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h deleted file mode 100644 index 8fddb63f44c2..000000000000 --- a/arch/arm/include/asm/arch-tegra124/gpio.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_GPIO_H_ -#define _TEGRA124_GPIO_H_ - -/* - * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h deleted file mode 100644 index 46dcc28f727c..000000000000 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * Portions Copyright 2011-2016 NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_GPIO_H_ -#define _TEGRA20_GPIO_H_ - -/* - * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 7 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h deleted file mode 100644 index f2279d0f3e92..000000000000 --- a/arch/arm/include/asm/arch-tegra210/gpio.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_GPIO_H_ -#define _TEGRA210_GPIO_H_ - -/* - * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h deleted file mode 100644 index 288451df2ff6..000000000000 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA30_GPIO_H_ -#define _TEGRA30_GPIO_H_ - -/* - * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA30_GPIO_H_ */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index fe4419cae4cf..751a5ade17c7 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,4 +1,4 @@ -#ifndef CONFIG_ARCH_UNIPHIER +#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_TEGRA) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/mach-tegra/include/mach/tegra_gpio.h similarity index 67% rename from arch/arm/include/asm/arch-tegra/gpio.h rename to arch/arm/mach-tegra/include/mach/tegra_gpio.h index 07921f34b9d7..09b813bc79ac 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/mach-tegra/include/mach/tegra_gpio.h @@ -5,15 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_ - -#define TEGRA_GPIOS_PER_PORT 8 - -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) +#ifndef _MACH_TEGRA_GPIO_H +#define _MACH_TEGRA_GPIO_H
enum tegra_gpio_init { TEGRA_GPIO_INIT_IN, @@ -34,4 +27,4 @@ struct tegra_gpio_config { */ void gpio_config_table(const struct tegra_gpio_config *config, int len);
-#endif /* TEGRA_GPIO_H_ */ +#endif diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index db6fa74ae1fe..c2b5e5e09d21 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-e2220-1170.h"
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 4b7058e3bc89..422a18a4e530 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -8,8 +8,9 @@ #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-jetson-tk1.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 56e15bda93ec..64d98f59a4c7 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -17,6 +17,7 @@ #include <asm/arch/mc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-nyan-big.h"
/* diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index 0fec3d497d7d..a23dfc8afaef 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-0000.h"
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index bc3389976942..3989ab8bde32 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h"
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 794830bac3b3..7faec788f3cf 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -9,8 +9,8 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "max77620_init.h" #include "pinmux-config-p2571.h"
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index 4373de6a26bd..5791e0d73522 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -7,8 +7,9 @@
#include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-venice2.h"
/* diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 9abab13daaa9..a3b6878e47bd 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -22,6 +22,8 @@ #include <asm/gpio.h> #include <dm/device-internal.h> #include <dt-bindings/gpio/gpio.h> +#include <mach/tegra_gpio.h> +#include "tegra_gpio_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h new file mode 100644 index 000000000000..edf5540da72f --- /dev/null +++ b/drivers/gpio/tegra_gpio_priv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * Copyright 2011-2016 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_GPIO_PRIV_H +#define _TEGRA_GPIO_PRIV_H + +/* + * GPIOs are arranged into ports, each of which controls 8 GPIOs. + * + * Ports are aggregated into banks (U-Boot terminology used below) or + * "controllers" (Tegra TRM terminology) each containing 4 ports. + * + * Banks/controllers are aggregated into the overall GPIO controller hardware + * module. Tegra20 implements only 7 banks. However, the register location of + * the "masked" registers is designed to leave space for 8 banks. Tegra30 and + * onwards implement 8 banks. In many cases, the last bank contains ports + * and/or GPIOs that are not implemented, or at least not connected to any + * pad/pin. + */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIOS_PER_PORT 8 + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_FULLPORT(x) ((x) >> 3) +#define GPIO_BIT(x) ((x) & 0x7) + +/* + * GPIO registers are split into two chunks; low and high. + * On Tegra20, all low chunks appear first, then all high chunks. + * In later SoCs, the low and high chunks are interleaved together. + */ +#define GPIO_CTLR_BANK_HIGH_REGS \ + uint gpio_masked_config[TEGRA_GPIO_PORTS]; \ + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \ + uint gpio_masked_out[TEGRA_GPIO_PORTS]; \ + uint reserved0[TEGRA_GPIO_PORTS]; \ + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \ + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \ + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \ + uint reserved1[TEGRA_GPIO_PORTS]; + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; +#ifndef CONFIG_TEGRA20 + GPIO_CTLR_BANK_HIGH_REGS +#endif +}; + +#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high { + GPIO_CTLR_BANK_HIGH_REGS +}; +#endif + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +#ifdef CONFIG_TEGRA20 + struct gpio_ctlr_bank_high gpio_bank_high[TEGRA_GPIO_BANKS]; +#endif +}; + +#endif diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2a8ab2d5e0b9..f1b8877be228 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_i2c.h>
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra114/gpio.h | 20 ------ arch/arm/include/asm/arch-tegra124/gpio.h | 44 ------------- arch/arm/include/asm/arch-tegra20/gpio.h | 36 ---------- arch/arm/include/asm/arch-tegra210/gpio.h | 44 ------------- arch/arm/include/asm/arch-tegra30/gpio.h | 43 ------------ arch/arm/include/asm/gpio.h | 2 +- .../include/mach/tegra_gpio.h} | 13 +--- board/nvidia/e2220-1170/e2220-1170.c | 3 +- board/nvidia/jetson-tk1/jetson-tk1.c | 3 +- board/nvidia/nyan-big/nyan-big.c | 1 + board/nvidia/p2371-0000/p2371-0000.c | 3 +- board/nvidia/p2371-2180/p2371-2180.c | 3 +- board/nvidia/p2571/p2571.c | 2 +- board/nvidia/venice2/venice2.c | 3 +- drivers/gpio/tegra_gpio.c | 2 + drivers/gpio/tegra_gpio_priv.h | 76 ++++++++++++++++++++++ drivers/i2c/tegra_i2c.c | 1 - 17 files changed, 94 insertions(+), 205 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra20/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gpio.h rename arch/arm/{include/asm/arch-tegra/gpio.h => mach-tegra/include/mach/tegra_gpio.h} (67%) create mode 100644 drivers/gpio/tegra_gpio_priv.h
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h deleted file mode 100644 index d6eaa1bd40e8..000000000000 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ /dev/null @@ -1,20 +0,0 @@ -/*
- Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0
- */
-#ifndef _TEGRA114_GPIO_H_ -#define _TEGRA114_GPIO_H_
-/*
- The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
- each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */
-#include <asm/arch-tegra/gpio.h> -#include <asm/arch-tegra30/gpio.h>
-#endif /* _TEGRA114_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h deleted file mode 100644 index 8fddb63f44c2..000000000000 --- a/arch/arm/include/asm/arch-tegra124/gpio.h +++ /dev/null @@ -1,44 +0,0 @@ -/*
- (C) Copyright 2013-2016
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _TEGRA124_GPIO_H_ -#define _TEGRA124_GPIO_H_
-/*
- The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
- each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */
-#include <asm/arch-tegra/gpio.h>
-/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];uint gpio_masked_config[TEGRA_GPIO_PORTS];uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];uint gpio_masked_out[TEGRA_GPIO_PORTS];uint gpio_masked_in[TEGRA_GPIO_PORTS];uint gpio_masked_int_status[TEGRA_GPIO_PORTS];uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];uint gpio_masked_int_level[TEGRA_GPIO_PORTS];uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];-};
-struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];-};
-#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h deleted file mode 100644 index 46dcc28f727c..000000000000 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ /dev/null @@ -1,36 +0,0 @@ -/*
- Copyright (c) 2011, Google Inc. All rights reserved.
- Portions Copyright 2011-2016 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _TEGRA20_GPIO_H_ -#define _TEGRA20_GPIO_H_
-/*
- The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
- each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 7 /* number of banks */
-#include <asm/arch-tegra/gpio.h>
-/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];-};
-struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];-};
-#endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h deleted file mode 100644 index f2279d0f3e92..000000000000 --- a/arch/arm/include/asm/arch-tegra210/gpio.h +++ /dev/null @@ -1,44 +0,0 @@ -/*
- (C) Copyright 2013-2016
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _TEGRA210_GPIO_H_ -#define _TEGRA210_GPIO_H_
-/*
- The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
- each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */
-#include <asm/arch-tegra/gpio.h>
-/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];uint gpio_masked_config[TEGRA_GPIO_PORTS];uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];uint gpio_masked_out[TEGRA_GPIO_PORTS];uint gpio_masked_in[TEGRA_GPIO_PORTS];uint gpio_masked_int_status[TEGRA_GPIO_PORTS];uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];uint gpio_masked_int_level[TEGRA_GPIO_PORTS];uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];-};
-struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];-};
-#endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h deleted file mode 100644 index 288451df2ff6..000000000000 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ /dev/null @@ -1,43 +0,0 @@ -/*
- Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0
- */
-#ifndef _TEGRA30_GPIO_H_ -#define _TEGRA30_GPIO_H_
-/*
- The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
- each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */
-#include <asm/arch-tegra/gpio.h>
-/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];uint gpio_masked_config[TEGRA_GPIO_PORTS];uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];uint gpio_masked_out[TEGRA_GPIO_PORTS];uint gpio_masked_in[TEGRA_GPIO_PORTS];uint gpio_masked_int_status[TEGRA_GPIO_PORTS];uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];uint gpio_masked_int_level[TEGRA_GPIO_PORTS];uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];-};
-struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];-};
-#endif /* _TEGRA30_GPIO_H_ */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index fe4419cae4cf..751a5ade17c7 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,4 +1,4 @@ -#ifndef CONFIG_ARCH_UNIPHIER +#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_TEGRA) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/mach-tegra/include/mach/tegra_gpio.h similarity index 67% rename from arch/arm/include/asm/arch-tegra/gpio.h rename to arch/arm/mach-tegra/include/mach/tegra_gpio.h index 07921f34b9d7..09b813bc79ac 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/mach-tegra/include/mach/tegra_gpio.h @@ -5,15 +5,8 @@
- SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_
-#define TEGRA_GPIOS_PER_PORT 8
-#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) +#ifndef _MACH_TEGRA_GPIO_H +#define _MACH_TEGRA_GPIO_H
enum tegra_gpio_init { TEGRA_GPIO_INIT_IN, @@ -34,4 +27,4 @@ struct tegra_gpio_config { */ void gpio_config_table(const struct tegra_gpio_config *config, int len);
-#endif /* TEGRA_GPIO_H_ */ +#endif diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index db6fa74ae1fe..c2b5e5e09d21 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-e2220-1170.h"
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 4b7058e3bc89..422a18a4e530 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -8,8 +8,9 @@ #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-jetson-tk1.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 56e15bda93ec..64d98f59a4c7 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -17,6 +17,7 @@ #include <asm/arch/mc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-nyan-big.h"
/* diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index 0fec3d497d7d..a23dfc8afaef 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-0000.h"
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index bc3389976942..3989ab8bde32 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -8,8 +8,9 @@ #include <common.h> #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h"
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 794830bac3b3..7faec788f3cf 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -9,8 +9,8 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "max77620_init.h" #include "pinmux-config-p2571.h"
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index 4373de6a26bd..5791e0d73522 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -7,8 +7,9 @@
#include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <mach/tegra_gpio.h> #include "pinmux-config-venice2.h"
/* diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 9abab13daaa9..a3b6878e47bd 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -22,6 +22,8 @@ #include <asm/gpio.h> #include <dm/device-internal.h> #include <dt-bindings/gpio/gpio.h> +#include <mach/tegra_gpio.h> +#include "tegra_gpio_priv.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h new file mode 100644 index 000000000000..edf5540da72f --- /dev/null +++ b/drivers/gpio/tegra_gpio_priv.h @@ -0,0 +1,76 @@ +/*
- Copyright (c) 2011, Google Inc. All rights reserved.
- Copyright 2011-2016 NVIDIA Corporation
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _TEGRA_GPIO_PRIV_H +#define _TEGRA_GPIO_PRIV_H
+/*
- GPIOs are arranged into ports, each of which controls 8 GPIOs.
- Ports are aggregated into banks (U-Boot terminology used below) or
- "controllers" (Tegra TRM terminology) each containing 4 ports.
- Banks/controllers are aggregated into the overall GPIO controller hardware
- module. Tegra20 implements only 7 banks. However, the register location of
- the "masked" registers is designed to leave space for 8 banks. Tegra30 and
- onwards implement 8 banks. In many cases, the last bank contains ports
- and/or GPIOs that are not implemented, or at least not connected to any
- pad/pin.
- */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIOS_PER_PORT 8
+#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_FULLPORT(x) ((x) >> 3) +#define GPIO_BIT(x) ((x) & 0x7)
+/*
- GPIO registers are split into two chunks; low and high.
- On Tegra20, all low chunks appear first, then all high chunks.
- In later SoCs, the low and high chunks are interleaved together.
- */
+#define GPIO_CTLR_BANK_HIGH_REGS \
uint gpio_masked_config[TEGRA_GPIO_PORTS]; \uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \uint gpio_masked_out[TEGRA_GPIO_PORTS]; \uint reserved0[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \uint reserved1[TEGRA_GPIO_PORTS];+/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];+#ifndef CONFIG_TEGRA20
GPIO_CTLR_BANK_HIGH_REGS+#endif +};
+#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high {
GPIO_CTLR_BANK_HIGH_REGS
This seems a bit ugly. Perhaps you could havestruct gpio_ctlr_high_regs and include that here? It adds a level of indirection but that doesn't seem very important.
+}; +#endif
+struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];+#ifdef CONFIG_TEGRA20
struct gpio_ctlr_bank_high gpio_bank_high[TEGRA_GPIO_BANKS];+#endif +};
+#endif diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2a8ab2d5e0b9..f1b8877be228 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h>
#include <mach/tegra_i2c.h>
2.8.1
Regards, Simon
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h
+/*
- GPIO registers are split into two chunks; low and high.
- On Tegra20, all low chunks appear first, then all high chunks.
- In later SoCs, the low and high chunks are interleaved together.
- */
+#define GPIO_CTLR_BANK_HIGH_REGS \
uint gpio_masked_config[TEGRA_GPIO_PORTS]; \uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \uint gpio_masked_out[TEGRA_GPIO_PORTS]; \uint reserved0[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \uint reserved1[TEGRA_GPIO_PORTS];+/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];+#ifndef CONFIG_TEGRA20
GPIO_CTLR_BANK_HIGH_REGS+#endif +};
+#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high {
GPIO_CTLR_BANK_HIGH_REGSThis seems a bit ugly. Perhaps you could havestruct gpio_ctlr_high_regs and include that here? It adds a level of indirection but that doesn't seem very important.
In newer Tegras, there's no differentiation between the two register sets that were "low" and "high" in Tegra20. I'd rather not saddle the non-Tegra20 struct layouts with some odd naming/nesting just because the Tegra20 layout was odd. I don't see any problem with using a #define for this; it doesn't seem to make the code complex.
I wonder if we should just convert away from structs for registers entirely. Everything in the HW docs is just numbers, matching those to the structs is always painful, and if we used #defines instead of structs, representing this HW difference would end up being much cleaner and avoid using a macro to "cut/paste" a register list 2 times; see the way the Linux kernel driver handles this.
Hi Stephen,
On 20 April 2016 at 16:01, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h
+/*
- GPIO registers are split into two chunks; low and high.
- On Tegra20, all low chunks appear first, then all high chunks.
- In later SoCs, the low and high chunks are interleaved together.
- */
+#define GPIO_CTLR_BANK_HIGH_REGS \
uint gpio_masked_config[TEGRA_GPIO_PORTS]; \uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \uint gpio_masked_out[TEGRA_GPIO_PORTS]; \uint reserved0[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \uint reserved1[TEGRA_GPIO_PORTS];+/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];+#ifndef CONFIG_TEGRA20
GPIO_CTLR_BANK_HIGH_REGS+#endif +};
+#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high {
GPIO_CTLR_BANK_HIGH_REGSThis seems a bit ugly. Perhaps you could havestruct gpio_ctlr_high_regs and include that here? It adds a level of indirection but that doesn't seem very important.
In newer Tegras, there's no differentiation between the two register sets that were "low" and "high" in Tegra20. I'd rather not saddle the non-Tegra20 struct layouts with some odd naming/nesting just because the Tegra20 layout was odd. I don't see any problem with using a #define for this; it doesn't seem to make the code complex.
OK, well then how about just duplicating the two structs, and dropping the #define?
#ifdfef CONFIG_TEGRA20 struct gpio_ctlr_bank {
}; #else struct gpio_ctlr_bank { }; #endif
I wonder if we should just convert away from structs for registers entirely. Everything in the HW docs is just numbers, matching those to the structs is always painful, and if we used #defines instead of structs, representing this HW difference would end up being much cleaner and avoid using a macro to "cut/paste" a register list 2 times; see the way the Linux kernel driver handles this.
Structs are definitely easier to read and particularly in this case where each struct element is an array.
Why are you worried about code duplication in a header file?
Regards, Simon
On 04/21/2016 08:11 AM, Simon Glass wrote:
Hi Stephen,
On 20 April 2016 at 16:01, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h
+/*
- GPIO registers are split into two chunks; low and high.
- On Tegra20, all low chunks appear first, then all high chunks.
- In later SoCs, the low and high chunks are interleaved together.
- */
+#define GPIO_CTLR_BANK_HIGH_REGS \
uint gpio_masked_config[TEGRA_GPIO_PORTS]; \uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \uint gpio_masked_out[TEGRA_GPIO_PORTS]; \uint reserved0[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \uint reserved1[TEGRA_GPIO_PORTS];+/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];+#ifndef CONFIG_TEGRA20
GPIO_CTLR_BANK_HIGH_REGS+#endif +};
+#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high {
GPIO_CTLR_BANK_HIGH_REGSThis seems a bit ugly. Perhaps you could havestruct gpio_ctlr_high_regs and include that here? It adds a level of indirection but that doesn't seem very important.
In newer Tegras, there's no differentiation between the two register sets that were "low" and "high" in Tegra20. I'd rather not saddle the non-Tegra20 struct layouts with some odd naming/nesting just because the Tegra20 layout was odd. I don't see any problem with using a #define for this; it doesn't seem to make the code complex.
OK, well then how about just duplicating the two structs, and dropping the #define?
#ifdfef CONFIG_TEGRA20 struct gpio_ctlr_bank {
}; #else struct gpio_ctlr_bank { }; #endif
Given that the driver doesn't use any registers in the high bank, and indeed can't; the driver's reliance on structs rather than register defines means that the high bank registers would have to be accessed differently between Tegra20 and other SoCs, I propose simply not representing those registers. Instead, how about:
struct gpio_ctlr_bank { uint gpio_config[TEGRA_GPIO_PORTS]; uint gpio_dir_out[TEGRA_GPIO_PORTS]; uint gpio_out[TEGRA_GPIO_PORTS]; uint gpio_in[TEGRA_GPIO_PORTS]; uint gpio_int_status[TEGRA_GPIO_PORTS]; uint gpio_int_enable[TEGRA_GPIO_PORTS]; uint gpio_int_level[TEGRA_GPIO_PORTS]; uint gpio_int_clear[TEGRA_GPIO_PORTS]; #ifndef CONFIG_TEGRA20 uint unused[TEGRA_GPIO_PORTS * 8]; #endif };
struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
That removes all the duplication, without any macros etc.
Does that look reasonable? If I fixup the patch like that, I'll add a brief comment describing what the unused registers are, similar to the one in patch v1.
I wonder if we should just convert away from structs for registers entirely. Everything in the HW docs is just numbers, matching those to the structs is always painful, and if we used #defines instead of structs, representing this HW difference would end up being much cleaner and avoid using a macro to "cut/paste" a register list 2 times; see the way the Linux kernel driver handles this.
Structs are definitely easier to read and particularly in this case where each struct element is an array.
I'm not really sure there's much objective difference between the readability of the two. Arrays can easily be abstracted via a macro or inline function so that the call site looks essentially identical; () vs [].
Why are you worried about code duplication in a header file?
I'm not sure why I would special case my concerns and ignore duplication in certain locations yet still care about duplication in general or elsewhere?
Hi Stephen,
On 21 April 2016 at 10:40, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/21/2016 08:11 AM, Simon Glass wrote:
Hi Stephen,
On 20 April 2016 at 16:01, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra's gpio.h contains a mix of private definitions for use inside the GPIO driver and custom machine-specific APIs. Move the private definitions out of the global include directory since nothing should need to access them. Move the public definitions to the machine-specific include directory <mach/>.
diff --git a/drivers/gpio/tegra_gpio_priv.h b/drivers/gpio/tegra_gpio_priv.h
+/*
- GPIO registers are split into two chunks; low and high.
- On Tegra20, all low chunks appear first, then all high chunks.
- In later SoCs, the low and high chunks are interleaved together.
- */
+#define GPIO_CTLR_BANK_HIGH_REGS \
uint gpio_masked_config[TEGRA_GPIO_PORTS]; \uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; \uint gpio_masked_out[TEGRA_GPIO_PORTS]; \uint reserved0[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; \uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; \uint reserved1[TEGRA_GPIO_PORTS];+/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];uint gpio_dir_out[TEGRA_GPIO_PORTS];uint gpio_out[TEGRA_GPIO_PORTS];uint gpio_in[TEGRA_GPIO_PORTS];uint gpio_int_status[TEGRA_GPIO_PORTS];uint gpio_int_enable[TEGRA_GPIO_PORTS];uint gpio_int_level[TEGRA_GPIO_PORTS];uint gpio_int_clear[TEGRA_GPIO_PORTS];+#ifndef CONFIG_TEGRA20
GPIO_CTLR_BANK_HIGH_REGS+#endif +};
+#ifdef CONFIG_TEGRA20 +struct gpio_ctlr_bank_high {
GPIO_CTLR_BANK_HIGH_REGSThis seems a bit ugly. Perhaps you could havestruct gpio_ctlr_high_regs and include that here? It adds a level of indirection but that doesn't seem very important.
In newer Tegras, there's no differentiation between the two register sets that were "low" and "high" in Tegra20. I'd rather not saddle the non-Tegra20 struct layouts with some odd naming/nesting just because the Tegra20 layout was odd. I don't see any problem with using a #define for this; it doesn't seem to make the code complex.
OK, well then how about just duplicating the two structs, and dropping the #define?
#ifdfef CONFIG_TEGRA20 struct gpio_ctlr_bank {
}; #else struct gpio_ctlr_bank { }; #endif
Given that the driver doesn't use any registers in the high bank, and indeed can't; the driver's reliance on structs rather than register defines means that the high bank registers would have to be accessed differently between Tegra20 and other SoCs, I propose simply not representing those registers. Instead, how about:
struct gpio_ctlr_bank { uint gpio_config[TEGRA_GPIO_PORTS]; uint gpio_dir_out[TEGRA_GPIO_PORTS]; uint gpio_out[TEGRA_GPIO_PORTS]; uint gpio_in[TEGRA_GPIO_PORTS]; uint gpio_int_status[TEGRA_GPIO_PORTS]; uint gpio_int_enable[TEGRA_GPIO_PORTS]; uint gpio_int_level[TEGRA_GPIO_PORTS]; uint gpio_int_clear[TEGRA_GPIO_PORTS]; #ifndef CONFIG_TEGRA20 uint unused[TEGRA_GPIO_PORTS * 8]; #endif };
struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; };
That removes all the duplication, without any macros etc.
Does that look reasonable? If I fixup the patch like that, I'll add a brief comment describing what the unused registers are, similar to the one in patch v1.
SGTM
I wonder if we should just convert away from structs for registers entirely. Everything in the HW docs is just numbers, matching those to the structs is always painful, and if we used #defines instead of structs, representing this HW difference would end up being much cleaner and avoid using a macro to "cut/paste" a register list 2 times; see the way the Linux kernel driver handles this.
Structs are definitely easier to read and particularly in this case where each struct element is an array.
I'm not really sure there's much objective difference between the readability of the two. Arrays can easily be abstracted via a macro or inline function so that the call site looks essentially identical; () vs [].
IMO the code is much harder to follow when you need to look up macros, etc. C already supports arrays :-)
Why are you worried about code duplication in a header file?
I'm not sure why I would special case my concerns and ignore duplication in certain locations yet still care about duplication in general or elsewhere?
We commonly put ugliness in header files. So long as the resulting syntax (in C files) is pretty obvious and non-surprising, this makes sense. Most of the time these header files are ignored by humans when reading the code since it is pretty obvious from the C code what is going on.
Examples include static inline to drop functions, hardware register definitions, bitfield definitions, #ifdef setup (see image.h), etc.
Perhaps by that argument your original #define scheme is fine. I don't like things that make it hard to grep the code for stuff, but this is minor. So I'm going to withdraw my objection (sorry).
Reviewed-by: Simon Glass sjg@chromium.org
Regards, Simon
From: Stephen Warren swarren@nvidia.com
All configuration is migrating to Kconfig. This moves one piece.
TEGRA_GPIO is default y since it's almost certain to be needed, and this setting matches the stanza removed from the config header file.
CONFIG_HAS_TEGRA_GPIO is introduced so that drivers/gpio/Kconfig doesn't have to know which Tegra chips contain this GPIO controller, thus isolating such knowledge into mach-tegra/Kconfig. All currently supported chips do, but the next chip contains a different GPIO controller and hence requires a different driver.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/Kconfig | 5 +++++ drivers/gpio/Kconfig | 8 ++++++++ include/configs/tegra-common.h | 1 - 3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ba6983f3dfd3..32ea2f944fa9 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,8 @@ if TEGRA
+config HAS_TEGRA_GPIO + bool "SoC contains Tegra20..210 GPIO controller" + config TEGRA_COMMON bool "Tegra common options" select DM @@ -19,6 +22,7 @@ config TEGRA_COMMON config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select CPU_V7 + select HAS_TEGRA_GPIO select SPL select SUPPORT_SPL select TEGRA_COMMON @@ -50,6 +54,7 @@ config TEGRA124
config TEGRA210 bool "Tegra210 family" + select HAS_TEGRA_GPIO select TEGRA_ARMV8_COMMON
endchoice diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f56a60621ff0..85700922a2da 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -109,6 +109,14 @@ config SANDBOX_GPIO_COUNT of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs.
+config TEGRA_GPIO + bool "Tegra20..210 GPIO driver" + depends on DM_GPIO && HAS_TEGRA_GPIO + default y + help + Support for the GPIO controller contained in NVIDIA Tegra20 through + Tegra210. + config GPIO_UNIPHIER bool "UniPhier GPIO" depends on ARCH_UNIPHIER diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 776394151661..b6506e2fb3df 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -109,7 +109,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)
-#define CONFIG_TEGRA_GPIO #define CONFIG_CMD_ENTERRCM
/* Defines for SPL */
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
All configuration is migrating to Kconfig. This moves one piece.
TEGRA_GPIO is default y since it's almost certain to be needed, and this setting matches the stanza removed from the config header file.
CONFIG_HAS_TEGRA_GPIO is introduced so that drivers/gpio/Kconfig doesn't have to know which Tegra chips contain this GPIO controller, thus isolating such knowledge into mach-tegra/Kconfig. All currently supported chips do, but the next chip contains a different GPIO controller and hence requires a different driver.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/Kconfig | 5 +++++ drivers/gpio/Kconfig | 8 ++++++++ include/configs/tegra-common.h | 1 - 3 files changed, 13 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra/, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/{include/asm/arch-tegra => mach-tegra}/apb_misc.h | 5 +++-- arch/arm/mach-tegra/spl.c | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/apb_misc.h (79%)
diff --git a/arch/arm/include/asm/arch-tegra/apb_misc.h b/arch/arm/mach-tegra/apb_misc.h similarity index 79% rename from arch/arm/include/asm/arch-tegra/apb_misc.h rename to arch/arm/mach-tegra/apb_misc.h index a5bc092ffdc1..8622826172e9 100644 --- a/arch/arm/include/asm/arch-tegra/apb_misc.h +++ b/arch/arm/mach-tegra/apb_misc.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2012 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ +#ifndef _TEGRA_APB_MISC_H +#define _TEGRA_APB_MISC_H
/* APB_MISC_PP registers */ struct apb_misc_pp_ctlr { diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index e0f9d5b6b4e9..ad13ad5ba5fb 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2012 + * (C) Copyright 2012-2016 * NVIDIA Inc, <www.nvidia.com> * * Allen Martin amartin@nvidia.com @@ -13,9 +13,9 @@ #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/board.h> #include <asm/spl.h> +#include "apb_misc.h" #include "cpu.h"
void spl_board_init(void) diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index eab61b7cd2ab..ace5fb5aa758 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -8,10 +8,10 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/tegra.h> +#include "../apb_misc.h"
/* * The EMC registers have shadow registers. When the EMC clock is updated diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 1013441d4265..427af25032bc 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -14,11 +14,11 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h" #include "crypto.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 616358b657be..0ae401c569b6 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -11,10 +11,10 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h" #include "../cpu.h" #include "warmboot_avp.h"
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra/, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/{include/asm/arch-tegra => mach-tegra}/apb_misc.h | 5 +++-- arch/arm/mach-tegra/spl.c | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/apb_misc.h (79%)
diff --git a/arch/arm/include/asm/arch-tegra/apb_misc.h b/arch/arm/mach-tegra/apb_misc.h similarity index 79% rename from arch/arm/include/asm/arch-tegra/apb_misc.h rename to arch/arm/mach-tegra/apb_misc.h index a5bc092ffdc1..8622826172e9 100644 --- a/arch/arm/include/asm/arch-tegra/apb_misc.h +++ b/arch/arm/mach-tegra/apb_misc.h @@ -1,11 +1,12 @@ /*
- Copyright (c) 2012 The Chromium OS Authors.
*/
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
-#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ +#ifndef _TEGRA_APB_MISC_H +#define _TEGRA_APB_MISC_H
/* APB_MISC_PP registers */ struct apb_misc_pp_ctlr { diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index e0f9d5b6b4e9..ad13ad5ba5fb 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -1,5 +1,5 @@ /*
- (C) Copyright 2012
- (C) Copyright 2012-2016
- NVIDIA Inc, <www.nvidia.com>
- Allen Martin amartin@nvidia.com
@@ -13,9 +13,9 @@ #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/board.h> #include <asm/spl.h> +#include "apb_misc.h" #include "cpu.h"
void spl_board_init(void) diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index eab61b7cd2ab..ace5fb5aa758 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -8,10 +8,10 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/tegra.h> +#include "../apb_misc.h"
/*
- The EMC registers have shadow registers. When the EMC clock is updated
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 1013441d4265..427af25032bc 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -14,11 +14,11 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h" #include "crypto.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 616358b657be..0ae401c569b6 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -11,10 +11,10 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h"
Is this really an improvement? What's the rationale?
#include "../cpu.h" #include "warmboot_avp.h"
-- 2.8.1
Regards, Simon
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra/, so move it there to avoid polluting the global include path.
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 616358b657be..0ae401c569b6 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -11,10 +11,10 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h"
Is this really an improvement?
Yes:-P
What's the rationale?
As mentioned in the commit description, the content of the header is only used by code in arch/arm/mach-tegra/. By moving the header file out of a directory that's part of the include path, we ensure that code (such as drivers and core code) can't access the header without explicitly doing something unusual, which should ring alarm bells. This will help avoid future additions of code that touches Tegra internals rather than accessing functionality through standard/generic (or even custom but explicitly "exported") APIs.
Hi Stephen,
On 20 April 2016 at 15:56, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra/, so move it there to avoid polluting the global include path.
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 616358b657be..0ae401c569b6 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -11,10 +11,10 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h"
Is this really an improvement?
Yes:-P
What's the rationale?
As mentioned in the commit description, the content of the header is only used by code in arch/arm/mach-tegra/. By moving the header file out of a directory that's part of the include path, we ensure that code (such as drivers and core code) can't access the header without explicitly doing something unusual, which should ring alarm bells. This will help avoid future additions of code that touches Tegra internals rather than accessing functionality through standard/generic (or even custom but explicitly "exported") APIs.
Well if that's what you want, OK.
The ../xxx.h looks odd to me - like a temporary hack. Also if we have a driver for SoC functionality then it will likely need access to this stuff. But I can't see a better way to do this, and it does achieve your goal...
Reviewed-by: Simon Glass sjg@chromium.org
Regards, Simon
On 04/21/2016 02:59 PM, Simon Glass wrote:
Hi Stephen,
On 20 April 2016 at 15:56, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/20/2016 01:26 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra/, so move it there to avoid polluting the global include path.
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 616358b657be..0ae401c569b6 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -11,10 +11,10 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../apb_misc.h"
Is this really an improvement?
Yes:-P
What's the rationale?
As mentioned in the commit description, the content of the header is only used by code in arch/arm/mach-tegra/. By moving the header file out of a directory that's part of the include path, we ensure that code (such as drivers and core code) can't access the header without explicitly doing something unusual, which should ring alarm bells. This will help avoid future additions of code that touches Tegra internals rather than accessing functionality through standard/generic (or even custom but explicitly "exported") APIs.
Well if that's what you want, OK.
The ../xxx.h looks odd to me - like a temporary hack. Also if we have a driver for SoC functionality then it will likely need access to this stuff. But I can't see a better way to do this, and it does achieve your goal...
Reviewed-by: Simon Glass sjg@chromium.org
Thanks.
If we do end up with a "real" driver for this in drivers/xxx/, I would hope the register header would move into the same directory along with the C file so nothing else could access it, and other code would only access those registers by calling functions in the driver, those functions being prototyped in some public header file in include/ or arch/arm/mach-tegra/include/mach/ depending on whether the API was U-Boot-wide or Tegra-specific.
This current patch does mean if we get a driver, we'll have to move the header again, but I don't expect that to happen imminently (perhaps ever?) for most of the code in arch/arm/mach-tegra, with the possible exception of clock/reset/XUSB drivers. Equally, there would be so much change involved in converting everything not to access the register directly but instead use clean APIs that including a header move as well would likely be close to noise.
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra}/fuse.h | 8 ++++---- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/fuse.h (83%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 336a7e08196d..d226d546a1e5 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -13,12 +13,12 @@ #include <asm/arch/gp_padctrl.h> #include <asm/arch/mc.h> #include <asm/arch-tegra/clock.h> -#include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/scu.h> #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> #include "cpu.h" +#include "fuse.h"
int tegra_get_chip(void) { diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h similarity index 83% rename from arch/arm/include/asm/arch-tegra/fuse.h rename to arch/arm/mach-tegra/fuse.h index 39b578c00d2c..448cf0869cde 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _FUSE_H_ -#define _FUSE_H_ +#ifndef _TEGRA_FUSE_H +#define _TEGRA_FUSE_H
/* FUSE registers */ struct fuse_regs { @@ -20,4 +20,4 @@ struct fuse_regs { u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ };
-#endif /* ifndef _FUSE_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 427af25032bc..ba996d1801da 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -16,9 +16,9 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> #include "../apb_misc.h" +#include "../fuse.h" #include "crypto.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra}/fuse.h | 8 ++++---- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/fuse.h (83%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/gpu.c | 6 +++--- arch/arm/{include/asm/arch-tegra => mach-tegra}/gpu.h | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/gpu.h (80%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 3ee65ee3f921..35ae69fbbe29 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -22,7 +22,6 @@ #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/warmboot.h> -#include <asm/arch-tegra/gpu.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif @@ -38,6 +37,7 @@ #include <i2c.h> #include <spi.h> #include "emc.h" +#include "gpu.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 74b64a620c5f..0da681bfe927 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -7,11 +7,11 @@ /* Tegra vpr routines */
#include <common.h> +#include <fdt_support.h> #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/mc.h> - -#include <fdt_support.h> +#include "gpu.h"
static bool _configured;
diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/mach-tegra/gpu.h similarity index 80% rename from arch/arm/include/asm/arch-tegra/gpu.h rename to arch/arm/mach-tegra/gpu.h index 6be9f6157b36..12f0c6a2bf3e 100644 --- a/arch/arm/include/asm/arch-tegra/gpu.h +++ b/arch/arm/mach-tegra/gpu.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2015 + * (C) Copyright 2015-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __ASM_ARCH_TEGRA_GPU_H -#define __ASM_ARCH_TEGRA_GPU_H +#ifndef _TEGRA_GPU_H +#define _TEGRA_GPU_H
#if defined(CONFIG_TEGRA_GPU)
@@ -33,4 +33,4 @@ static inline int tegra_gpu_enable_node(void *blob, const char *compat)
#endif /* CONFIG_OF_LIBFDT */
-#endif /* __ASM_ARCH_TEGRA_GPU_H */ +#endif
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/gpu.c | 6 +++--- arch/arm/{include/asm/arch-tegra => mach-tegra}/gpu.h | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/gpu.h (80%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/clock.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 4 ++-- arch/arm/mach-tegra/cpu.c | 4 ++-- arch/arm/{include/asm/arch-tegra => mach-tegra}/pmc.h | 6 +++--- arch/arm/mach-tegra/tegra114/cpu.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/psci.c | 2 +- arch/arm/mach-tegra/tegra20/cpu.c | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 1 - 15 files changed, 20 insertions(+), 21 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/pmc.h (99%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index d226d546a1e5..94cc124979c6 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -13,12 +13,12 @@ #include <asm/arch/gp_padctrl.h> #include <asm/arch/mc.h> #include <asm/arch-tegra/clock.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/scu.h> #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> #include "cpu.h" #include "fuse.h" +#include "pmc.h"
int tegra_get_chip(void) { diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 098547ab1e88..2f80e2e0c696 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -15,9 +15,9 @@ #include <asm/arch/mc.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/warmboot.h> +#include "pmc.h"
void save_boot_params_ret(void);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 35ae69fbbe29..c630fd18fdfe 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -19,7 +19,6 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/warmboot.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING @@ -38,6 +37,7 @@ #include <spi.h> #include "emc.h" #include "gpu.h" +#include "pmc.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 80d6fccf2551..1a6fc0151a60 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -12,9 +12,9 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <div64.h> #include <fdtdec.h> +#include "pmc.h"
/* * This is our record of the current clock rate of each clock. We don't diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index a94ec93e7be1..d5205c39ab79 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2016, NVIDIA CORPORATION. All rights reserved. * * Derived from code (arch/arm/lib/reset.c) that is: * @@ -27,7 +27,7 @@
#include <common.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/pmc.h> +#include "pmc.h"
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index a3ebb57f20b2..09d15974dd9b 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,9 +11,9 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/scu.h> #include "cpu.h" +#include "pmc.h"
int get_num_cpus(void) { diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h similarity index 99% rename from arch/arm/include/asm/arch-tegra/pmc.h rename to arch/arm/mach-tegra/pmc.h index 9c9b67448985..be38f007bc94 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _PMC_H_ -#define _PMC_H_ +#ifndef _TEGRA_PMC_H +#define _TEGRA_PMC_H
/* Power Management Controller (APBDEV_PMC_) registers */ struct pmc_ctlr { @@ -374,4 +374,4 @@ struct pmc_ctlr { /* APBDEV_PMC_CNTRL2_0 0x440 */ #define HOLD_CKE_LOW_EN (1 << 12)
-#endif /* PMC_H */ +#endif diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 272a2ea281ee..41e337fcfb57 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2014 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -12,8 +12,8 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include "../cpu.h" +#include "../pmc.h"
/* Tegra114-specific CPU init code */ static void enable_cpu_power_rail(void) diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index be31cb4ac881..e8c8c507c404 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -12,8 +12,8 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include "../cpu.h" +#include "../pmc.h"
/* Tegra124-specific CPU init code */
diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index 08225e32dbd4..739cf352676e 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -11,8 +11,8 @@ #include <asm/psci.h> #include <asm/arch/flow.h> #include <asm/arch/powergate.h> -#include <asm/arch-tegra/pmc.h> #include "../cpu.h" +#include "../pmc.h"
static void park_cpu(void) { diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 7fbc2e28655c..10205dca5e53 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/pmc.h> #include "../cpu.h" +#include "../pmc.h"
static void enable_cpu_power_rail(void) { diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index ba996d1801da..5a0390b72a4a 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -15,10 +15,10 @@ #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> #include "../apb_misc.h" #include "../fuse.h" +#include "../pmc.h" #include "crypto.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 0ae401c569b6..d7f03c29df86 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -12,10 +12,10 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> #include "../apb_misc.h" #include "../cpu.h" +#include "../pmc.h" #include "warmboot_avp.h"
#define DEBUG_RESET_CORESIGHT diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 774207354064..392c8d3bb76e 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -10,9 +10,9 @@ #include <asm/arch/flow.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <mach/tegra_i2c.h> #include "../cpu.h" +#include "../pmc.h"
/* Tegra30-specific CPU init code */
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 64d98f59a4c7..efd3c18ba740 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -16,7 +16,6 @@ #include <asm/arch/clock.h> #include <asm/arch/mc.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/pmc.h> #include <mach/tegra_gpio.h> #include "pinmux-config-nyan-big.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/clock.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 4 ++-- arch/arm/mach-tegra/cpu.c | 4 ++-- arch/arm/{include/asm/arch-tegra => mach-tegra}/pmc.h | 6 +++--- arch/arm/mach-tegra/tegra114/cpu.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/psci.c | 2 +- arch/arm/mach-tegra/tegra20/cpu.c | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 1 - 15 files changed, 20 insertions(+), 21 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/pmc.h (99%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/cpu.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra}/scu.h | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/scu.h (91%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 94cc124979c6..386ca72707e8 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -13,12 +13,12 @@ #include <asm/arch/gp_padctrl.h> #include <asm/arch/mc.h> #include <asm/arch-tegra/clock.h> -#include <asm/arch-tegra/scu.h> #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> #include "cpu.h" #include "fuse.h" #include "pmc.h" +#include "scu.h"
int tegra_get_chip(void) { diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 09d15974dd9b..3562a2d2188a 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -11,9 +11,9 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/scu.h> #include "cpu.h" #include "pmc.h" +#include "scu.h"
int get_num_cpus(void) { diff --git a/arch/arm/include/asm/arch-tegra/scu.h b/arch/arm/mach-tegra/scu.h similarity index 91% rename from arch/arm/include/asm/arch-tegra/scu.h rename to arch/arm/mach-tegra/scu.h index 987c16ff45f9..b13c2d9d2061 100644 --- a/arch/arm/include/asm/arch-tegra/scu.h +++ b/arch/arm/mach-tegra/scu.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _SCU_H_ -#define _SCU_H_ +#ifndef _TEGRA_SCU_H +#define _TEGRA_SCU_H
/* ARM Snoop Control Unit (SCU) registers */ struct scu_ctlr { @@ -24,4 +24,4 @@ struct scu_ctlr {
#define SCU_CTRL_ENABLE (1 << 0)
-#endif /* SCU_H */ +#endif
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/cpu.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra}/scu.h | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra}/scu.h (91%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 1 - arch/arm/mach-tegra/board.c | 1 - arch/arm/mach-tegra/board2.c | 4 +++- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/warmboot.h | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/warmboot.h (98%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 386ca72707e8..4cb6367cd0a4 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -14,7 +14,6 @@ #include <asm/arch/mc.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/tegra.h> -#include <asm/arch-tegra/warmboot.h> #include "cpu.h" #include "fuse.h" #include "pmc.h" diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 2f80e2e0c696..cf65ece060dd 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -16,7 +16,6 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/warmboot.h> #include "pmc.h"
void save_boot_params_ret(void); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index c630fd18fdfe..b1db5febd199 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -20,7 +20,6 @@ #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/warmboot.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif @@ -38,6 +37,9 @@ #include "emc.h" #include "gpu.h" #include "pmc.h" +#ifdef CONFIG_TEGRA_LP0 +#include "tegra20/warmboot.h" +#endif
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5a0390b72a4a..956eb96f027f 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -15,11 +15,11 @@ #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/warmboot.h> #include "../apb_misc.h" #include "../fuse.h" #include "../pmc.h" #include "crypto.h" +#include "warmboot.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/mach-tegra/tegra20/warmboot.h similarity index 98% rename from arch/arm/include/asm/arch-tegra/warmboot.h rename to arch/arm/mach-tegra/tegra20/warmboot.h index b6326c8f7b11..5651d28ad487 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/mach-tegra/tegra20/warmboot.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _WARM_BOOT_H_ -#define _WARM_BOOT_H_ +#ifndef _TEGRA20_WARMBOOT_H +#define _TEGRA20_WARMBOOT_H
#define STRAP_OPT_A_RAM_CODE_SHIFT 4 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index d7f03c29df86..f204582b99b8 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -12,10 +12,10 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/warmboot.h> #include "../apb_misc.h" #include "../cpu.h" #include "../pmc.h" +#include "warmboot.h" #include "warmboot_avp.h"
#define DEBUG_RESET_CORESIGHT
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 1 - arch/arm/mach-tegra/board.c | 1 - arch/arm/mach-tegra/board2.c | 4 +++- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/warmboot.h | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/tegra20}/warmboot.h (98%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra => mach-tegra/include/mach}/xusb-padctl.h | 4 ++-- arch/arm/mach-tegra/xusb-padctl-common.h | 9 ++++----- arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++-- drivers/pci/pci_tegra.c | 5 +++-- 5 files changed, 12 insertions(+), 12 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/xusb-padctl.h (92%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index b1db5febd199..9d970c483e0e 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -30,7 +30,7 @@ #ifdef CONFIG_TEGRA_MMC #include <mach/tegra_mmc.h> #endif -#include <asm/arch-tegra/xusb-padctl.h> +#include <mach/xusb-padctl.h> #include <power/as3722.h> #include <i2c.h> #include <spi.h> diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/mach-tegra/include/mach/xusb-padctl.h similarity index 92% rename from arch/arm/include/asm/arch-tegra/xusb-padctl.h rename to arch/arm/mach-tegra/include/mach/xusb-padctl.h index b4b4c8ba4d10..ab277123be51 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/mach-tegra/include/mach/xusb-padctl.h @@ -1,5 +1,5 @@ -#ifndef _TEGRA_XUSB_PADCTL_H_ -#define _TEGRA_XUSB_PADCTL_H_ +#ifndef _MACH_XUSB_PADCTL_H +#define _MACH_XUSB_PADCTL_H
struct tegra_xusb_phy;
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index f44790a65004..b63b2faaa1c6 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -1,17 +1,16 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
-#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ -#define _TEGRA_XUSB_PADCTL_COMMON_H_ +#ifndef _TEGRA_XUSB_PADCTL_COMMON_H +#define _TEGRA_XUSB_PADCTL_COMMON_H
#include <common.h> #include <fdtdec.h> - #include <asm/io.h> -#include <asm/arch-tegra/xusb-padctl.h> +#include <mach/xusb-padctl.h>
struct tegra_xusb_padctl_lane { const char *name; diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 65f8d2ea967a..779ee97d1482 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -7,7 +7,7 @@ #include <common.h> #include <errno.h>
-#include <asm/arch-tegra/xusb-padctl.h> +#include <mach/xusb-padctl.h>
struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) { diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 5dadf6fa62a7..5e0f9c50aef3 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -5,7 +5,7 @@ * Based on NVIDIA PCIe driver * Copyright (c) 2008-2009, NVIDIA Corporation. * - * Copyright (c) 2013-2014, NVIDIA Corporation. + * Copyright (c) 2013-2016, NVIDIA Corporation. * * SPDX-License-Identifier: GPL-2.0 */ @@ -24,7 +24,8 @@
#include <asm/arch/clock.h> #include <asm/arch/powergate.h> -#include <asm/arch-tegra/xusb-padctl.h> + +#include <mach/xusb-padctl.h>
#include <linux/list.h>
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 2 +- .../asm/arch-tegra => mach-tegra/include/mach}/xusb-padctl.h | 4 ++-- arch/arm/mach-tegra/xusb-padctl-common.h | 9 ++++----- arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++-- drivers/pci/pci_tegra.c | 5 +++-- 5 files changed, 12 insertions(+), 12 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/xusb-padctl.h (92%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Both board and sys_proto.h served the same purpose; a place to prototype functions implemented by the board and called by code in mach-tegra/. Merge them into a single file to reduce the number of headers.
board_init_uart_f() is private to code in mach-tegra/ so remove its prototype from the public <mach/> header. cpu.h isn't a great place for it, but other functions implemented in the same C file are prototyped there, so it'll do for now. When the C files are all refactored for Tegra186, this should be cleaned up.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/sys_proto.h | 33 ---------------------- arch/arm/mach-tegra/board.c | 3 +- arch/arm/mach-tegra/board2.c | 4 +-- arch/arm/mach-tegra/cpu.h | 2 ++ arch/arm/mach-tegra/emc.c | 1 - .../arch-tegra => mach-tegra/include/mach}/board.h | 33 +++++++++++++++++----- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 1 - board/avionic-design/common/tamonten.c | 3 +- board/nvidia/seaboard/seaboard.c | 2 +- board/toradex/colibri_t20/colibri_t20.c | 2 +- 11 files changed, 35 insertions(+), 51 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/sys_proto.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/board.h (63%)
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h deleted file mode 100644 index 8c2f94b578fe..000000000000 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -/** - * tegra_board_id() - Get the board iD - * - * @return a board ID, or -ve on error - */ -int tegra_board_id(void); - -/** - * tegra_lcd_pmic_init() - Set up the PMIC for a board - * - * @board_id: Board ID which may be used to select LCD type - * @return 0 if OK, -ve on error - */ -int tegra_lcd_pmic_init(int board_id); - -/** - * nvidia_board_init() - perform any board-specific init - * - * @return 0 if OK, -ve on error - */ -int nvidia_board_init(void); - -#endif diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index cf65ece060dd..87a9b5266804 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -14,8 +14,7 @@ #include <asm/arch/funcmux.h> #include <asm/arch/mc.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> -#include <asm/arch-tegra/sys_proto.h> +#include <mach/board.h> #include "pmc.h"
void save_boot_params_ret(void); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 9d970c483e0e..ce865be250e0 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -17,9 +17,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/sys_proto.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif @@ -27,6 +25,7 @@ #ifdef CONFIG_USB_EHCI_TEGRA #include <usb.h> #endif +#include <mach/board.h> #ifdef CONFIG_TEGRA_MMC #include <mach/tegra_mmc.h> #endif @@ -34,6 +33,7 @@ #include <power/as3722.h> #include <i2c.h> #include <spi.h> +#include "cpu.h" #include "emc.h" #include "gpu.h" #include "pmc.h" diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index c0284ce03787..88ffb29d18e1 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -84,3 +84,5 @@ void config_cache(void); #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) bool tegra_cpu_is_non_secure(void); #endif +/* Set up early UART output */ +void board_init_uart_f(void); diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 70aec7fc1b3d..25150bcc3e80 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -12,7 +12,6 @@ #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/sys_proto.h> #include "emc.h" #include "cpu.h"
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/mach-tegra/include/mach/board.h similarity index 63% rename from arch/arm/include/asm/arch-tegra/board.h rename to arch/arm/mach-tegra/include/mach/board.h index 783bb3c0fa12..f6688ef761e7 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/mach-tegra/include/mach/board.h @@ -1,19 +1,16 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_BOARD_H_ -#define _TEGRA_BOARD_H_ +#ifndef _MACH_BOARD_H +#define _MACH_BOARD_H
/* Set up pinmux to make UART usable */ void gpio_early_init_uart(void);
-/* Set up early UART output */ -void board_init_uart_f(void); - /* Set up any early GPIOs the board might need for proper operation */ void gpio_early_init(void); /* overrideable GPIO config */
@@ -31,4 +28,26 @@ void pin_mux_nand(void); /* overridable NAND pinmux setup */ void pin_mux_mmc(void); /* overridable mmc pinmux setup */ void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
+/** + * tegra_lcd_pmic_init() - Set up the PMIC for a board + * + * @board_id: Board ID which may be used to select LCD type + * @return 0 if OK, -ve on error + */ +int tegra_lcd_pmic_init(int board_id); + +/** + * tegra_board_id() - Get the board iD + * + * @return a board ID, or -ve on error + */ +int tegra_board_id(void); + +/** + * nvidia_board_init() - perform any board-specific init + * + * @return 0 if OK, -ve on error + */ +int nvidia_board_init(void); + #endif diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index ad13ad5ba5fb..e793700b243e 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -13,8 +13,8 @@ #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> #include <asm/spl.h> +#include <mach/board.h> #include "apb_misc.h" #include "cpu.h"
diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 8488d97d5cde..2ebcfaf2695e 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -10,7 +10,6 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/sys_proto.h> #include <mach/tegra_i2c.h> #include "../cpu.h"
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index c05113c1c36c..c369d13e7f50 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -16,9 +16,8 @@ #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/sys_proto.h> +#include <mach/board.h>
#ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 9c92fc2e29e2..913679e888d3 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -13,7 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/board.h> +#include <mach/board.h>
/* TODO: Remove this code when the SPI switch is working */ #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index e47565fa6389..2505104b78fe 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -13,8 +13,8 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/board.h> #include <asm/arch-tegra/tegra.h> +#include <mach/board.h>
#define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Both board and sys_proto.h served the same purpose; a place to prototype functions implemented by the board and called by code in mach-tegra/. Merge them into a single file to reduce the number of headers.
board_init_uart_f() is private to code in mach-tegra/ so remove its prototype from the public <mach/> header. cpu.h isn't a great place for it, but other functions implemented in the same C file are prototyped there, so it'll do for now. When the C files are all refactored for Tegra186, this should be cleaned up.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/sys_proto.h | 33 ---------------------- arch/arm/mach-tegra/board.c | 3 +- arch/arm/mach-tegra/board2.c | 4 +-- arch/arm/mach-tegra/cpu.h | 2 ++ arch/arm/mach-tegra/emc.c | 1 - .../arch-tegra => mach-tegra/include/mach}/board.h | 33 +++++++++++++++++----- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 1 - board/avionic-design/common/tamonten.c | 3 +- board/nvidia/seaboard/seaboard.c | 2 +- board/toradex/colibri_t20/colibri_t20.c | 2 +- 11 files changed, 35 insertions(+), 51 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/sys_proto.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/board.h (63%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
... and add one missing set of include guards.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/cpu.h | 6 ++++++ arch/arm/mach-tegra/emc.h | 6 +++--- arch/arm/mach-tegra/tegra20/crypto.h | 6 +++--- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 4 ++-- 4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 88ffb29d18e1..e6dcfe25dfe3 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -4,6 +4,10 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _TEGRA_CPU_H +#define _TEGRA_CPU_H + #include <asm/types.h>
/* Stabilization delays, in usec */ @@ -86,3 +90,5 @@ bool tegra_cpu_is_non_secure(void); #endif /* Set up early UART output */ void board_init_uart_f(void); + +#endif diff --git a/arch/arm/mach-tegra/emc.h b/arch/arm/mach-tegra/emc.h index 4095235179f5..46e1260585a1 100644 --- a/arch/arm/mach-tegra/emc.h +++ b/arch/arm/mach-tegra/emc.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _NVIDIA_EMC_H_ -#define _NVIDIA_EMC_H_ +#ifndef _TEGRA_EMC_H +#define _TEGRA_EMC_H
int board_emc_init(void);
diff --git a/arch/arm/mach-tegra/tegra20/crypto.h b/arch/arm/mach-tegra/tegra20/crypto.h index f59b92768a44..55f7bb44cdee 100644 --- a/arch/arm/mach-tegra/tegra20/crypto.h +++ b/arch/arm/mach-tegra/tegra20/crypto.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _CRYPTO_H_ -#define _CRYPTO_H_ +#ifndef _TEGRA20_CRYPTO_H +#define _TEGRA20_CRYPTO_H
/** * Sign a block of data diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 85892b023fad..2e5f8d016faa 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _WARMBOOT_AVP_H_ -#define _WARMBOOT_AVP_H_ +#ifndef _TEGRA20_WARMBOOT_AVP_H_ +#define _TEGRA20_WARMBOOT_AVP_H_
#define TEGRA_DEV_L 0 #define TEGRA_DEV_H 1
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
... and add one missing set of include guards.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/cpu.h | 6 ++++++ arch/arm/mach-tegra/emc.h | 6 +++--- arch/arm/mach-tegra/tegra20/crypto.h | 6 +++--- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 4 ++-- 4 files changed, 14 insertions(+), 8 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
These headers aren't included by anything, so can be deleted.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra210/ahb.h | 80 -------------------------------- 1 file changed, 80 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h deleted file mode 100644 index 2e676a436e3d..000000000000 --- a/arch/arm/include/asm/arch-tegra210/ahb.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_AHB_H_ -#define _TEGRA210_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#endif /* _TEGRA210_AHB_H_ */
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
These headers aren't included by anything, so can be deleted.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra210/ahb.h | 80 -------------------------------- 1 file changed, 80 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
tegra_set_emc() is moved between two emc.h so that mach-tegra/emc.h defines fairly public interfaces to the EMC functionality, and emc_priv.h contains internal register details.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 3 --- arch/arm/mach-tegra/emc.c | 1 - arch/arm/mach-tegra/emc.h | 14 ++++++++++++++ arch/arm/mach-tegra/tegra20/emc.c | 3 ++- .../emc.h => mach-tegra/tegra20/emc_priv.h} | 17 +++-------------- arch/arm/mach-tegra/tegra20/warmboot.c | 3 ++- 6 files changed, 21 insertions(+), 20 deletions(-) rename arch/arm/{include/asm/arch-tegra20/emc.h => mach-tegra/tegra20/emc_priv.h} (83%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index ce865be250e0..269afdf7a6e5 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -18,9 +18,6 @@ #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#ifdef CONFIG_TEGRA_CLOCK_SCALING -#include <asm/arch/emc.h> -#endif #include "../../../drivers/usb/host/ehci-tegra-priv.h" #ifdef CONFIG_USB_EHCI_TEGRA #include <usb.h> diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 25150bcc3e80..945bdedaf82d 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/emc.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> diff --git a/arch/arm/mach-tegra/emc.h b/arch/arm/mach-tegra/emc.h index 46e1260585a1..19527b67031e 100644 --- a/arch/arm/mach-tegra/emc.h +++ b/arch/arm/mach-tegra/emc.h @@ -8,6 +8,20 @@ #ifndef _TEGRA_EMC_H #define _TEGRA_EMC_H
+/* Implemented in SoC-agnostic EMC code, called by core board code */ int board_emc_init(void);
+/** + * Set up the EMC for the given rate. The timing parameters are retrieved + * from the device tree "nvidia,tegra20-emc" node and its + * "nvidia,tegra20-emc-table" sub-nodes. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @return 0 if ok, else -ve error code (look in emc.c to decode it) + * + * Implemented by SoC-specific code. + */ +int tegra_set_emc(const void *blob, unsigned rate); + #endif diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index ace5fb5aa758..c2569418ba9f 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -9,9 +9,10 @@ #include <fdtdec.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/emc.h> #include <asm/arch/tegra.h> #include "../apb_misc.h" +#include "../emc.h" +#include "emc_priv.h"
/* * The EMC registers have shadow registers. When the EMC clock is updated diff --git a/arch/arm/include/asm/arch-tegra20/emc.h b/arch/arm/mach-tegra/tegra20/emc_priv.h similarity index 83% rename from arch/arm/include/asm/arch-tegra20/emc.h rename to arch/arm/mach-tegra/tegra20/emc_priv.h index a85f4c3d823d..108e8aa62576 100644 --- a/arch/arm/include/asm/arch-tegra20/emc.h +++ b/arch/arm/mach-tegra/tegra20/emc_priv.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _ARCH_EMC_H_ -#define _ARCH_EMC_H_ +#ifndef _TEGRA20_EMC_PRIV_H +#define _TEGRA20_EMC_PRIV_H
#include <asm/types.h>
@@ -76,17 +76,6 @@ struct emc_ctlr { };
/** - * Set up the EMC for the given rate. The timing parameters are retrieved - * from the device tree "nvidia,tegra20-emc" node and its - * "nvidia,tegra20-emc-table" sub-nodes. - * - * @param blob Device tree blob - * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) - * @return 0 if ok, else -ve error code (look in emc.c to decode it) - */ -int tegra_set_emc(const void *blob, unsigned rate); - -/** * Get a pointer to the EMC controller from the device tree. * * @param blob Device tree blob diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 956eb96f027f..94298907c084 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -9,16 +9,17 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/clock.h> -#include <asm/arch/emc.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../apb_misc.h" +#include "../emc.h" #include "../fuse.h" #include "../pmc.h" #include "crypto.h" +#include "emc_priv.h" #include "warmboot.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
tegra_set_emc() is moved between two emc.h so that mach-tegra/emc.h defines fairly public interfaces to the EMC functionality, and emc_priv.h contains internal register details.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 3 --- arch/arm/mach-tegra/emc.c | 1 - arch/arm/mach-tegra/emc.h | 14 ++++++++++++++ arch/arm/mach-tegra/tegra20/emc.c | 3 ++- .../emc.h => mach-tegra/tegra20/emc_priv.h} | 17 +++-------------- arch/arm/mach-tegra/tegra20/warmboot.c | 3 ++- 6 files changed, 21 insertions(+), 20 deletions(-) rename arch/arm/{include/asm/arch-tegra20/emc.h => mach-tegra/tegra20/emc_priv.h} (83%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com --- .../{include/asm/arch-tegra20 => mach-tegra/tegra20}/sdram_param.h | 6 +++--- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/sdram_param.h (96%)
diff --git a/arch/arm/include/asm/arch-tegra20/sdram_param.h b/arch/arm/mach-tegra/tegra20/sdram_param.h similarity index 96% rename from arch/arm/include/asm/arch-tegra20/sdram_param.h rename to arch/arm/mach-tegra/tegra20/sdram_param.h index aaf05084e96f..19cb5ab2f47a 100644 --- a/arch/arm/include/asm/arch-tegra20/sdram_param.h +++ b/arch/arm/mach-tegra/tegra20/sdram_param.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _SDRAM_PARAM_H_ -#define _SDRAM_PARAM_H_ +#ifndef _TEGRA20_SDRAM_PARAM_H +#define _TEGRA20_SDRAM_PARAM_H
/* * Defines the number of 32-bit words provided in each set of SDRAM parameters diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 94298907c084..9d67bdef494a 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -11,7 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> -#include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../apb_misc.h" @@ -20,6 +19,7 @@ #include "../pmc.h" #include "crypto.h" #include "emc_priv.h" +#include "sdram_param.h" #include "warmboot.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path.
Signed-off-by: Stephen Warren swarren@nvidia.com
.../{include/asm/arch-tegra20 => mach-tegra/tegra20}/sdram_param.h | 6 +++--- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/sdram_param.h (96%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path. Also, unify the 3 identical copies of the file into one.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra124/sysctr.h | 26 ---------------------- arch/arm/include/asm/arch-tegra210/sysctr.h | 26 ---------------------- .../asm/arch-tegra114 => mach-tegra}/sysctr.h | 8 +++---- arch/arm/mach-tegra/tegra114/clock.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 2 +- 6 files changed, 7 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra124/sysctr.h delete mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h rename arch/arm/{include/asm/arch-tegra114 => mach-tegra}/sysctr.h (81%)
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h deleted file mode 100644 index 3f0309b78fae..000000000000 --- a/arch/arm/include/asm/arch-tegra124/sysctr.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_SYSCTR_H_ -#define _TEGRA124_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h deleted file mode 100644 index e8a13b502a6d..000000000000 --- a/arch/arm/include/asm/arch-tegra210/sysctr.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_SYSCTR_H_ -#define _TEGRA210_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA210_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/mach-tegra/sysctr.h similarity index 81% rename from arch/arm/include/asm/arch-tegra114/sysctr.h rename to arch/arm/mach-tegra/sysctr.h index 38220aac8eed..27930d1c3240 100644 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ b/arch/arm/mach-tegra/sysctr.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
-#ifndef _TEGRA114_SYSCTR_H_ -#define _TEGRA114_SYSCTR_H_ +#ifndef _TEGRA_SYSCTR_H +#define _TEGRA_SYSCTR_H
struct sysctr_ctlr { u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ @@ -22,4 +22,4 @@ struct sysctr_ctlr { #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
-#endif /* _TEGRA114_SYSCTR_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 7a73e159a7cd..155353d44c52 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -10,11 +10,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include "../sysctr.h"
/* * Clock types that we can use as a source. The Tegra114 has muxes for the diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 1219b6413844..dc060a6db569 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -10,11 +10,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include "../sysctr.h"
/* * Clock types that we can use as a source. The Tegra124 has muxes for the diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index b025711acf09..d2d517b2c711 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -11,11 +11,11 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include "../sysctr.h"
/* * Clock types that we can use as a source. The Tegra210 has muxes for the
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there to avoid polluting the global include path. Also, unify the 3 identical copies of the file into one.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra124/sysctr.h | 26 ---------------------- arch/arm/include/asm/arch-tegra210/sysctr.h | 26 ---------------------- .../asm/arch-tegra114 => mach-tegra}/sysctr.h | 8 +++---- arch/arm/mach-tegra/tegra114/clock.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 2 +- 6 files changed, 7 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra124/sysctr.h delete mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h rename arch/arm/{include/asm/arch-tegra114 => mach-tegra}/sysctr.h (81%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is duplicated many times, and does nothing but prototype a single function that's used solely by mach-tegra code. Move the proto- type of mach-tegra/cpu.h. That's not an awesome location for it, but other similar functions like pmic_enable_cpu_vdd() are already there.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra114/pmu.h | 13 ------------- arch/arm/include/asm/arch-tegra124/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra20/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra210/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra30/pmu.h | 13 ------------- arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/cpu.h | 2 ++ arch/arm/mach-tegra/emc.c | 1 - 8 files changed, 2 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h
diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h deleted file mode 100644 index 3104a1b855b8..000000000000 --- a/arch/arm/include/asm/arch-tegra114/pmu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA114_PMU_H_ -#define _TEGRA114_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA114_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h deleted file mode 100644 index b10100a63671..000000000000 --- a/arch/arm/include/asm/arch-tegra124/pmu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_PMU_H_ -#define _TEGRA124_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA124_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/pmu.h b/arch/arm/include/asm/arch-tegra20/pmu.h deleted file mode 100644 index 46effb47e18d..000000000000 --- a/arch/arm/include/asm/arch-tegra20/pmu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ARCH_PMU_H_ -#define _ARCH_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _ARCH_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h deleted file mode 100644 index 1e5f3886c675..000000000000 --- a/arch/arm/include/asm/arch-tegra210/pmu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_PMU_H_ -#define _TEGRA210_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA210_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h deleted file mode 100644 index f01c37ed673b..000000000000 --- a/arch/arm/include/asm/arch-tegra30/pmu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA30_PMU_H_ -#define _TEGRA30_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA30_PMU_H_ */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 269afdf7a6e5..684d4a5ad853 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -15,7 +15,6 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/pmu.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index e6dcfe25dfe3..f1f5b179c198 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -82,6 +82,8 @@ int tegra_get_sku_info(void); */ int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); void pmic_enable_cpu_vdd(void); /* Do any chip-specific cache config */ void config_cache(void); diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 945bdedaf82d..86aba51e398e 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pmu.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "emc.h"
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is duplicated many times, and does nothing but prototype a single function that's used solely by mach-tegra code. Move the proto- type of mach-tegra/cpu.h. That's not an awesome location for it, but other similar functions like pmic_enable_cpu_vdd() are already there.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra114/pmu.h | 13 ------------- arch/arm/include/asm/arch-tegra124/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra20/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra210/pmu.h | 14 -------------- arch/arm/include/asm/arch-tegra30/pmu.h | 13 ------------- arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/cpu.h | 2 ++ arch/arm/mach-tegra/emc.c | 1 - 8 files changed, 2 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra20/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h
Reviewed-by: Simon Glass sjg@chromium.org
I wonder if it would be better to retain the header name and move pmic_enable_cpu_vdd()?
- Simon
On 04/22/2016 12:32 PM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is duplicated many times, and does nothing but prototype a single function that's used solely by mach-tegra code. Move the proto- type of mach-tegra/cpu.h. That's not an awesome location for it, but other similar functions like pmic_enable_cpu_vdd() are already there.
Reviewed-by: Simon Glass sjg@chromium.org
I wonder if it would be better to retain the header name and move pmic_enable_cpu_vdd()?
I think that pmu_set_nominal() (the function moved into cpu.h by this patch) and pmic_enable_cpu_vdd() serve essentially the same semantic purpose, but are used on different sets of SoCs via ifdefs or weak functions. I expect that early in the part 2 series, I'll get rid of more code in board2.c's board_init() and put it into something like tegra_board_init_soc(), prototyped in board_init.h or soc_init.h.
Or put another way, I expect I'll clean up the "not a great location" issue mentioned in this patch description pretty soon.
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them. This change also removes multiple useless empty wrappers for this header.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra114/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra124/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra20/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra210/powergate.h | 12 ------------ arch/arm/include/asm/arch-tegra30/powergate.h | 6 ------ .../asm/arch-tegra => mach-tegra/include/mach}/powergate.h | 10 ++++++++-- arch/arm/mach-tegra/powergate.c | 4 ++-- arch/arm/mach-tegra/tegra124/psci.c | 2 +- drivers/pci/pci_tegra.c | 2 +- 9 files changed, 12 insertions(+), 42 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/powergate.h (83%)
diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h deleted file mode 100644 index 260ea801b81b..000000000000 --- a/arch/arm/include/asm/arch-tegra114/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA114_POWERGATE_H_ -#define _TEGRA114_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA114_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h deleted file mode 100644 index 8a0cfbaf9665..000000000000 --- a/arch/arm/include/asm/arch-tegra124/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA124_POWERGATE_H_ -#define _TEGRA124_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA124_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h deleted file mode 100644 index 439d88b7022a..000000000000 --- a/arch/arm/include/asm/arch-tegra20/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA20_POWERGATE_H_ -#define _TEGRA20_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA20_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h deleted file mode 100644 index df6f91dece64..000000000000 --- a/arch/arm/include/asm/arch-tegra210/powergate.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_POWERGATE_H_ -#define _TEGRA210_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA210_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h deleted file mode 100644 index c70e44b6216d..000000000000 --- a/arch/arm/include/asm/arch-tegra30/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA30_POWERGATE_H_ -#define _TEGRA30_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA30_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h similarity index 83% rename from arch/arm/include/asm/arch-tegra/powergate.h rename to arch/arm/mach-tegra/include/mach/powergate.h index 2e491f19005a..3ac9c9b092b1 100644 --- a/arch/arm/include/asm/arch-tegra/powergate.h +++ b/arch/arm/mach-tegra/include/mach/powergate.h @@ -1,5 +1,11 @@ -#ifndef _TEGRA_POWERGATE_H_ -#define _TEGRA_POWERGATE_H_ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MACH_POWERGATE_H +#define _MACH_POWERGATE_H
#include <asm/arch/clock.h>
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 30ae036bff05..49723e88cc56 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -10,8 +10,8 @@ #include <asm/io.h> #include <asm/types.h> #include <asm/arch/flow.h> -#include <asm/arch/powergate.h> #include <asm/arch/tegra.h> +#include <mach/powergate.h>
#define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index 739cf352676e..b6d99c7740c7 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -10,7 +10,7 @@ #include <asm/io.h> #include <asm/psci.h> #include <asm/arch/flow.h> -#include <asm/arch/powergate.h> +#include <mach/powergate.h> #include "../cpu.h" #include "../pmc.h"
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 5e0f9c50aef3..392ebde1e05c 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -23,8 +23,8 @@ #include <asm/gpio.h>
#include <asm/arch/clock.h> -#include <asm/arch/powergate.h>
+#include <mach/powergate.h> #include <mach/xusb-padctl.h>
#include <linux/list.h>
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them. This change also removes multiple useless empty wrappers for this header.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra114/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra124/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra20/powergate.h | 6 ------ arch/arm/include/asm/arch-tegra210/powergate.h | 12 ------------ arch/arm/include/asm/arch-tegra30/powergate.h | 6 ------ .../asm/arch-tegra => mach-tegra/include/mach}/powergate.h | 10 ++++++++-- arch/arm/mach-tegra/powergate.c | 4 ++-- arch/arm/mach-tegra/tegra124/psci.c | 2 +- drivers/pci/pci_tegra.c | 2 +- 9 files changed, 12 insertions(+), 42 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h delete mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/powergate.h (83%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Add arch/arm/mach-tegra/tegraNNN/include. We'll use this to house headers that must vary between SoCs (e.g. clock lists, register layouts that aren't static across chip versions, etc.) in a <soc/> name-space. This will allow code in mach-tegra/ to access those register definitions without polluting the more public <asm/> or <mach/> namespaces or the directories they map to.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/config.mk | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/mach-tegra/config.mk
diff --git a/arch/arm/mach-tegra/config.mk b/arch/arm/mach-tegra/config.mk new file mode 100644 index 000000000000..cc16451987e9 --- /dev/null +++ b/arch/arm/mach-tegra/config.mk @@ -0,0 +1,13 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +socdirs-$(CONFIG_TEGRA20) += tegra20 +socdirs-$(CONFIG_TEGRA30) += tegra30 +socdirs-$(CONFIG_TEGRA114) += tegra114 +socdirs-$(CONFIG_TEGRA124) += tegra124 +socdirs-$(CONFIG_TEGRA210) += tegra210 + +#$(warning PLATFORM_CPPFLAGS pre $(PLATFORM_CPPFLAGS)) +PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/arch/arm/mach-tegra/%/include,$(socdirs-y)) +#$(warning PLATFORM_CPPFLAGS post $(PLATFORM_CPPFLAGS))
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Add arch/arm/mach-tegra/tegraNNN/include. We'll use this to house headers that must vary between SoCs (e.g. clock lists, register layouts that aren't static across chip versions, etc.) in a <soc/> name-space. This will allow code in mach-tegra/ to access those register definitions without polluting the more public <asm/> or <mach/> namespaces or the directories they map to.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/config.mk | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/mach-tegra/config.mk
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
According to the TRM, Tegra20's flow controller has a xrq_events field too. Suspend/resume (via LP0) does still work after this fix, implying the write to halt_cpu1_events in warmboot_avp.c isn't actually necessary, since this patch causes it to access a different register.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra20/flow.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-tegra20/flow.h b/arch/arm/include/asm/arch-tegra20/flow.h index 8a6a78311452..e7df5bbb906c 100644 --- a/arch/arm/include/asm/arch-tegra20/flow.h +++ b/arch/arm/include/asm/arch-tegra20/flow.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,6 +13,7 @@ struct flow_ctlr { u32 halt_cop_events; u32 cpu_csr; u32 cop_csr; + u32 xrq_events; u32 halt_cpu1_events; u32 cpu1_csr; };
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
According to the TRM, Tegra20's flow controller has a xrq_events field too. Suspend/resume (via LP0) does still work after this fix, implying the write to halt_cpu1_events in warmboot_avp.c isn't actually necessary, since this patch causes it to access a different register.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra20/flow.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there. Since the definitions are used by code in mach-tegra/ itself, not just in SoC-specific mach-tegra/tegraNNN/, and the content varies per SoC, we need to put it in the (somewhat isolated) <soc/> include directory rather than in mach-tegra/ directly.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/tegra114/cpu.c | 2 +- .../asm/arch-tegra30 => mach-tegra/tegra114/include/soc}/flow.h | 8 ++++---- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- .../asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/flow.h | 6 +++--- arch/arm/mach-tegra/tegra124/psci.c | 2 +- .../asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/flow.h | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- .../asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/flow.h | 6 +++--- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- .../asm/arch-tegra114 => mach-tegra/tegra30/include/soc}/flow.h | 8 ++++---- 11 files changed, 22 insertions(+), 22 deletions(-) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra114/include/soc}/flow.h (67%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/flow.h (93%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/flow.h (85%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/flow.h (90%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra30/include/soc}/flow.h (67%)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 49723e88cc56..04205bb10cbb 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -9,9 +9,9 @@
#include <asm/io.h> #include <asm/types.h> -#include <asm/arch/flow.h> #include <asm/arch/tegra.h> #include <mach/powergate.h> +#include <soc/flow.h>
#define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 41e337fcfb57..c06e632bb36a 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -8,10 +8,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> +#include <soc/flow.h> #include "../cpu.h" #include "../pmc.h"
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/mach-tegra/tegra114/include/soc/flow.h similarity index 67% rename from arch/arm/include/asm/arch-tegra30/flow.h rename to arch/arm/mach-tegra/tegra114/include/soc/flow.h index 73cb0eecdcdc..781ac57516ff 100644 --- a/arch/arm/include/asm/arch-tegra30/flow.h +++ b/arch/arm/mach-tegra/tegra114/include/soc/flow.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
-#ifndef _TEGRA30_FLOW_H_ -#define _TEGRA30_FLOW_H_ +#ifndef _TEGRA114_FLOW_H +#define _TEGRA114_FLOW_H
struct flow_ctlr { u32 halt_cpu_events; @@ -22,4 +22,4 @@ struct flow_ctlr { u32 cluster_control; };
-#endif /* _TEGRA30_FLOW_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index e8c8c507c404..527c4a186e68 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -8,10 +8,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> +#include <soc/flow.h> #include "../cpu.h" #include "../pmc.h"
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/mach-tegra/tegra124/include/soc/flow.h similarity index 93% rename from arch/arm/include/asm/arch-tegra124/flow.h rename to arch/arm/mach-tegra/tegra124/include/soc/flow.h index 3f70fb190527..a96eeb9217aa 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/mach-tegra/tegra124/include/soc/flow.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA124_FLOW_H_ -#define _TEGRA124_FLOW_H_ +#ifndef _TEGRA124_FLOW_H +#define _TEGRA124_FLOW_H
struct flow_ctlr { u32 halt_cpu_events; /* offset 0x00 */ @@ -49,4 +49,4 @@ enum { RAM_REPAIR_STS = 0x1 << 1, };
-#endif /* _TEGRA124_FLOW_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index b6d99c7740c7..27f9e60e1372 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -9,8 +9,8 @@ #include <common.h> #include <asm/io.h> #include <asm/psci.h> -#include <asm/arch/flow.h> #include <mach/powergate.h> +#include <soc/flow.h> #include "../cpu.h" #include "../pmc.h"
diff --git a/arch/arm/include/asm/arch-tegra20/flow.h b/arch/arm/mach-tegra/tegra20/include/soc/flow.h similarity index 85% rename from arch/arm/include/asm/arch-tegra20/flow.h rename to arch/arm/mach-tegra/tegra20/include/soc/flow.h index e7df5bbb906c..b8c55b8317f5 100644 --- a/arch/arm/include/asm/arch-tegra20/flow.h +++ b/arch/arm/mach-tegra/tegra20/include/soc/flow.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _FLOW_H_ -#define _FLOW_H_ +#ifndef _TEGRA20_FLOW_H +#define _TEGRA20_FLOW_H
struct flow_ctlr { u32 halt_cpu_events; diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index f204582b99b8..ace6e8d4f59b 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -8,10 +8,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> +#include <soc/flow.h> #include "../apb_misc.h" #include "../cpu.h" #include "../pmc.h" diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/mach-tegra/tegra210/include/soc/flow.h similarity index 90% rename from arch/arm/include/asm/arch-tegra210/flow.h rename to arch/arm/mach-tegra/tegra210/include/soc/flow.h index e4ede6a81500..b3b188fe7399 100644 --- a/arch/arm/include/asm/arch-tegra210/flow.h +++ b/arch/arm/mach-tegra/tegra210/include/soc/flow.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA210_FLOW_H_ -#define _TEGRA210_FLOW_H_ +#ifndef _TEGRA210_FLOW_H +#define _TEGRA210_FLOW_H
struct flow_ctlr { u32 halt_cpu_events; /* offset 0x00 */ @@ -28,4 +28,4 @@ struct flow_ctlr { u32 ram_repair; /* offset 0x40 */ };
-#endif /* _TEGRA210_FLOW_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 392c8d3bb76e..f7cffb7d5106 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -7,10 +7,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/flow.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_i2c.h> +#include <soc/flow.h> #include "../cpu.h" #include "../pmc.h"
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/mach-tegra/tegra30/include/soc/flow.h similarity index 67% rename from arch/arm/include/asm/arch-tegra114/flow.h rename to arch/arm/mach-tegra/tegra30/include/soc/flow.h index 2e4045fc72d4..a51fd171fc61 100644 --- a/arch/arm/include/asm/arch-tegra114/flow.h +++ b/arch/arm/mach-tegra/tegra30/include/soc/flow.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
-#ifndef _TEGRA114_FLOW_H_ -#define _TEGRA114_FLOW_H_ +#ifndef _TEGRA30_FLOW_H +#define _TEGRA30_FLOW_H
struct flow_ctlr { u32 halt_cpu_events; @@ -22,4 +22,4 @@ struct flow_ctlr { u32 cluster_control; };
-#endif /* _TEGRA114_FLOW_H_ */ +#endif
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there. Since the definitions are used by code in mach-tegra/ itself, not just in SoC-specific mach-tegra/tegraNNN/, and the content varies per SoC, we need to put it in the (somewhat isolated) <soc/> include directory rather than in mach-tegra/ directly.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/tegra114/cpu.c | 2 +- .../asm/arch-tegra30 => mach-tegra/tegra114/include/soc}/flow.h | 8 ++++---- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- .../asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/flow.h | 6 +++--- arch/arm/mach-tegra/tegra124/psci.c | 2 +- .../asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/flow.h | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- .../asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/flow.h | 6 +++--- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- .../asm/arch-tegra114 => mach-tegra/tegra30/include/soc}/flow.h | 8 ++++---- 11 files changed, 22 insertions(+), 22 deletions(-) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra114/include/soc}/flow.h (67%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/flow.h (93%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/flow.h (85%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/flow.h (90%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra30/include/soc}/flow.h (67%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Equivalent code is already present in the core Tegra board file, so there's no point repeating it here. This removes the only use of <asm/arch/mc.h> from outside arch/arm/mach-tegra/.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/gpu.c | 1 + board/nvidia/nyan-big/nyan-big.c | 13 ------------- 2 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 0da681bfe927..172514204b1d 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -20,6 +20,7 @@ void tegra_gpu_config(void) struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
/* Turn VPR off */ + writel(0, &mc->mc_video_protect_bom); writel(0, &mc->mc_video_protect_size_mb); writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, &mc->mc_video_protect_reg_ctrl); diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index efd3c18ba740..db2874ed93ac 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/arch/pinmux.h> #include <asm/arch/clock.h> -#include <asm/arch/mc.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_gpio.h> #include "pinmux-config-nyan-big.h" @@ -65,17 +64,6 @@ int tegra_lcd_pmic_init(int board_id) return 0; }
-/* Setup required information for Linux kernel */ -static void setup_kernel_info(void) -{ - struct mc_ctlr *mc = (void *)NV_PA_MC_BASE; - - /* The kernel graphics driver needs this region locked down */ - writel(0, &mc->mc_video_protect_bom); - writel(0, &mc->mc_video_protect_size_mb); - writel(1, &mc->mc_video_protect_reg_ctrl); -} - /* * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF, * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks. @@ -123,7 +111,6 @@ int nvidia_board_init(void)
/* For external MAX98090 audio codec */ clock_external_output(1); - setup_kernel_info(); enable_required_clocks();
return 0;
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Equivalent code is already present in the core Tegra board file, so there's no point repeating it here. This removes the only use of <asm/arch/mc.h> from outside arch/arm/mach-tegra/.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/gpu.c | 1 + board/nvidia/nyan-big/nyan-big.c | 13 ------------- 2 files changed, 1 insertion(+), 13 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there. Since the definitions are used by code in mach-tegra/ itself, not just in SoC-specific mach-tegra/tegraNNN/, and the content varies per SoC, we need to put it in the (somewhat isolated) <soc/> include directory rather than in mach-tegra/ directly.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/gpu.c | 2 +- .../{include/asm/arch-tegra114 => mach-tegra/tegra114/include/soc}/mc.h | 2 +- .../{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/mc.h | 0 .../{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/mc.h | 2 +- .../{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/mc.h | 0 .../{include/asm/arch-tegra30 => mach-tegra/tegra30/include/soc}/mc.h | 2 +- 8 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/soc}/mc.h (97%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/mc.h (100%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/mc.h (97%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/mc.h (100%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/soc}/mc.h (97%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 4cb6367cd0a4..a200010e2937 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -11,9 +11,9 @@ #include <linux/bug.h> #include <asm/io.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/mc.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/tegra.h> +#include <soc/mc.h> #include "cpu.h" #include "fuse.h" #include "pmc.h" diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 87a9b5266804..71eb1a5d1b63 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -12,9 +12,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/mc.h> #include <asm/arch/tegra.h> #include <mach/board.h> +#include <soc/mc.h> #include "pmc.h"
void save_boot_params_ret(void); diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 172514204b1d..36204f54e4c9 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -10,7 +10,7 @@ #include <fdt_support.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch/mc.h> +#include <soc/mc.h> #include "gpu.h"
static bool _configured; diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/mach-tegra/tegra114/include/soc/mc.h similarity index 97% rename from arch/arm/include/asm/arch-tegra114/mc.h rename to arch/arm/mach-tegra/tegra114/include/soc/mc.h index 044b1e0b3990..6690f0435a95 100644 --- a/arch/arm/include/asm/arch-tegra114/mc.h +++ b/arch/arm/mach-tegra/tegra114/include/soc/mc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/mach-tegra/tegra124/include/soc/mc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra124/mc.h rename to arch/arm/mach-tegra/tegra124/include/soc/mc.h diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/mach-tegra/tegra20/include/soc/mc.h similarity index 97% rename from arch/arm/include/asm/arch-tegra20/mc.h rename to arch/arm/mach-tegra/tegra20/include/soc/mc.h index 9c6e3ffb6f44..d85ceb6b20d7 100644 --- a/arch/arm/include/asm/arch-tegra20/mc.h +++ b/arch/arm/mach-tegra/tegra20/include/soc/mc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/mach-tegra/tegra210/include/soc/mc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra210/mc.h rename to arch/arm/mach-tegra/tegra210/include/soc/mc.h diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/mach-tegra/tegra30/include/soc/mc.h similarity index 97% rename from arch/arm/include/asm/arch-tegra30/mc.h rename to arch/arm/mach-tegra/tegra30/include/soc/mc.h index 242a1fc64b9b..99ea0f22125d 100644 --- a/arch/arm/include/asm/arch-tegra30/mc.h +++ b/arch/arm/mach-tegra/tegra30/include/soc/mc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This header is only needed by code local to mach-tegra, so move it there. Since the definitions are used by code in mach-tegra/ itself, not just in SoC-specific mach-tegra/tegraNNN/, and the content varies per SoC, we need to put it in the (somewhat isolated) <soc/> include directory rather than in mach-tegra/ directly.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/gpu.c | 2 +- .../{include/asm/arch-tegra114 => mach-tegra/tegra114/include/soc}/mc.h | 2 +- .../{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/mc.h | 0 .../{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/mc.h | 2 +- .../{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/mc.h | 0 .../{include/asm/arch-tegra30 => mach-tegra/tegra30/include/soc}/mc.h | 2 +- 8 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/soc}/mc.h (97%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/soc}/mc.h (100%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/soc}/mc.h (97%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/soc}/mc.h (100%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/soc}/mc.h (97%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
These defines are used with APIs in pinmux.h, so it makes sense to put them into the same header. It also allows all includes of gp_padctrl.h to be removed from code outside arch/arm/mach-tegra/.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra114/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra124/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra210/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra30/pinmux.h | 8 +++++++- board/avionic-design/common/tamonten-ng.c | 1 - board/nvidia/cardhu/cardhu.c | 1 - board/nvidia/dalmore/dalmore.c | 3 +-- board/toradex/apalis_t30/apalis_t30.c | 1 - 12 files changed, 33 insertions(+), 37 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 21fa4f2d4233..24416f4a5c52 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -64,10 +64,4 @@ struct apb_misc_gp_ctlr { u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ };
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - #endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 38d8b9cf4d03..c96fd096695b 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -313,6 +313,12 @@ enum pmux_func { PMUX_FUNC_COUNT, };
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h index 440cbbfa3ed3..406edd0d7ea6 100644 --- a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2013 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -65,10 +65,4 @@ struct apb_misc_gp_ctlr { u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ };
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - #endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 9fcbb0f80b4b..31b921f4ae71 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -342,6 +342,12 @@ enum pmux_func { PMUX_FUNC_COUNT, };
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h index fb69baf98678..ead620534c7d 100644 --- a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -65,10 +65,4 @@ struct apb_misc_gp_ctlr { u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ };
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - #endif /* _TEGRA210_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h index af3b55f0d7b8..4772d96101c9 100644 --- a/arch/arm/include/asm/arch-tegra210/pinmux.h +++ b/arch/arm/include/asm/arch-tegra210/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -404,6 +404,12 @@ enum pmux_func { PMUX_FUNC_COUNT, };
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h index 1c5017686ce9..5453555d3ea3 100644 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -46,10 +46,4 @@ struct apb_misc_gp_ctlr { u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ };
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -#define SDIOCFG_DRVUP_SLWF 1 -#define SDIOCFG_DRVDN_SLWR 1 -#define SDIOCFG_DRVUP 0x2E -#define SDIOCFG_DRVDN 0x2A - #endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 3358bf7ce386..6f4e2899b963 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -391,6 +391,12 @@ enum pmux_func { PMUX_FUNC_COUNT, };
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define SDIOCFG_DRVUP_SLWF 1 +#define SDIOCFG_DRVDN_SLWR 1 +#define SDIOCFG_DRVUP 0x2E +#define SDIOCFG_DRVDN 0x2A + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index aa1fd0ebce1e..6bff3285c73c 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -12,7 +12,6 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> #include "pinmux-config-tamonten-ng.h"
#define PMU_I2C_ADDRESS 0x2D diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ff46e0cf0419..edfe960428ac 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -11,7 +11,6 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> #include "pinmux-config-cardhu.h"
#define PMU_I2C_ADDRESS 0x2D diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index e4c4bfbc6809..09adc74e0ede 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -7,7 +7,6 @@ #include <common.h> #include <dm.h> #include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> #include "pinmux-config-dalmore.h" #include <i2c.h>
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 8fdee023ee8a..e2a40db1afdd 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -7,7 +7,6 @@ */
#include <common.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h>
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
These defines are used with APIs in pinmux.h, so it makes sense to put them into the same header. It also allows all includes of gp_padctrl.h to be removed from code outside arch/arm/mach-tegra/.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra114/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra124/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra210/pinmux.h | 8 +++++++- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 8 +------- arch/arm/include/asm/arch-tegra30/pinmux.h | 8 +++++++- board/avionic-design/common/tamonten-ng.c | 1 - board/nvidia/cardhu/cardhu.c | 1 - board/nvidia/dalmore/dalmore.c | 3 +-- board/toradex/apalis_t30/apalis_t30.c | 1 - 12 files changed, 33 insertions(+), 37 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a200010e2937..a8e3e8b7dfcb 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -10,7 +10,6 @@ #include <common.h> #include <linux/bug.h> #include <asm/io.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/tegra.h> #include <soc/mc.h> @@ -19,23 +18,6 @@ #include "pmc.h" #include "scu.h"
-int tegra_get_chip(void) -{ - int rev; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - /* - * This is undocumented, Chip ID is bits 15:8 of the register - * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, 0x35 for T114, and 0x40 for Tegra124. - */ - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - debug("%s: CHIPID is 0x%02X\n", __func__, rev); - - return rev; -} - int tegra_get_sku_info(void) { int sku_id; @@ -49,74 +31,47 @@ int tegra_get_sku_info(void)
int tegra_get_chip_sku(void) { - uint sku_id, chip_id; +#ifdef CONFIG_TEGRA20 + uint sku_id;
- chip_id = tegra_get_chip(); sku_id = tegra_get_sku_info(); - - switch (chip_id) { - case CHIPID_TEGRA20: - switch (sku_id) { - case SKU_ID_T20_7: - case SKU_ID_T20: - return TEGRA_SOC_T20; - case SKU_ID_T25SE: - case SKU_ID_AP25: - case SKU_ID_T25: - case SKU_ID_AP25E: - case SKU_ID_T25E: - return TEGRA_SOC_T25; - } - break; - case CHIPID_TEGRA30: - switch (sku_id) { - case SKU_ID_T33: - case SKU_ID_T30: - case SKU_ID_TM30MQS_P_A3: - default: - return TEGRA_SOC_T30; - } - break; - case CHIPID_TEGRA114: - switch (sku_id) { - case SKU_ID_T114_ENG: - case SKU_ID_T114_1: - default: - return TEGRA_SOC_T114; - } - break; - case CHIPID_TEGRA124: - switch (sku_id) { - case SKU_ID_T124_ENG: - default: - return TEGRA_SOC_T124; - } - break; - case CHIPID_TEGRA210: - switch (sku_id) { - case SKU_ID_T210_ENG: - default: - return TEGRA_SOC_T210; - } - break; + switch (sku_id) { + case SKU_ID_T20_7: + case SKU_ID_T20: + return TEGRA_SOC_T20; + case SKU_ID_T25SE: + case SKU_ID_AP25: + case SKU_ID_T25: + case SKU_ID_AP25E: + case SKU_ID_T25E: + return TEGRA_SOC_T25; + default: + /* unknown chip/sku id */ + printf("ERROR: UNKNOWN SKU ID 0x%02X\n", sku_id); + return TEGRA_SOC_UNKNOWN; } - - /* unknown chip/sku id */ - printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", - __func__, chip_id, sku_id); - return TEGRA_SOC_UNKNOWN; +#endif +#ifdef CONFIG_TEGRA30 + return TEGRA_SOC_T30; +#endif +#ifdef CONFIG_TEGRA114 + return TEGRA_SOC_T114; +#endif +#ifdef CONFIG_TEGRA124 + return TEGRA_SOC_T124; +#endif +#ifdef CONFIG_TEGRA210 + return TEGRA_SOC_T210; +#endif }
#ifndef CONFIG_ARM64 static void enable_scu(void) { +#ifdef CONFIG_TEGRA20 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; u32 reg;
- /* Only enable the SCU on T20/T25 */ - if (tegra_get_chip() != CHIPID_TEGRA20) - return; - /* If SCU already setup/enabled, return */ if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) return; @@ -128,6 +83,7 @@ static void enable_scu(void) reg = readl(&scu->scu_ctrl); reg |= SCU_CTRL_ENABLE; writel(reg, &scu->scu_ctrl); +#endif }
static u32 get_odmdata(void) diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index b93814fcb96b..a41a7b9e2868 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -8,31 +8,29 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/gp_padctrl.h> #include "cpu.h"
#ifndef CONFIG_ARM64 void config_cache(void) { - u32 reg = 0; - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ - if (tegra_get_chip() < CHIPID_TEGRA114) - return; - +#if defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) /* * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. */ - asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); - reg &= ~7; - reg |= 2; - asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + { + u32 reg; + asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + } +#endif } #endif diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 3562a2d2188a..cc60908677a1 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -172,7 +172,6 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; - int chip = tegra_get_chip(); u32 reg; debug("%s entry\n", __func__);
@@ -189,11 +188,12 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); writel(reg, &pll->pll_base);
+ reg = 0; + +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) /* Set cpcon to PLLX_MISC */ - if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) - reg = (cpcon << pllinfo->kcp_shift); - else - reg = 0; + reg |= (cpcon << pllinfo->kcp_shift); +#endif
/* * TODO(twarren@nvidia.com) Check which SoCs use DCCON @@ -230,15 +230,11 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int soc_type, sku_info, chip_sku; + int sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("%s entry\n", __func__);
- /* get SOC (chip) type */ - soc_type = tegra_get_chip(); - debug("%s: SoC = 0x%02X\n", __func__, soc_type); - /* get SKU info */ sku_info = tegra_get_sku_info(); debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index f1f5b179c198..ee4f7868baf7 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -64,12 +64,6 @@ void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); /** - * Returns the pure SOC (chip ID) from the HIDREV register - * - * @return SOC ID - see CHIPID_TEGRAxx... - */ -int tegra_get_chip(void); -/** * Returns the SKU ID from the sku_info register * * @return SKU ID - see SKU_ID_Txx... diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 9d67bdef494a..1159f05a5dc3 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -242,22 +242,12 @@ static int ap20_is_production_mode(void)
static enum fuse_operating_mode fuse_get_operation_mode(void) { - u32 chip_id; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> - HIDREV_CHIPID_SHIFT; - if (chip_id == CHIPID_TEGRA20) { - if (ap20_is_odm_production_mode()) { - printf("!! odm_production_mode is not supported !!\n"); - return MODE_UNDEFINED; - } else - if (ap20_is_production_mode()) - return MODE_PRODUCTION; - else - return MODE_UNDEFINED; + if (ap20_is_odm_production_mode()) { + printf("!! odm_production_mode is not supported !!\n"); + return MODE_UNDEFINED; } + if (ap20_is_production_mode()) + return MODE_PRODUCTION; return MODE_UNDEFINED; }
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support? Shouldn't we head towards that rather than making it harder?
Regards, Simon
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
Shouldn't we head towards that rather than making it harder?
I don't see any need for that, no.
U-Boot is built for a specific board (or in some cases a set of extremely closely related set of boards, such as the RPI A/B/A+/B+). There's no need to determine almost anything at run-time since almost all information is known at compile time, with exceptions such as standardized enumerable buses such as USB, PCIe. If we support multiple HW in a single binary, it gets bloated with code that simply isn't going to be used, since all the extra code is either for a platform that the build won't be installed on (e.g. clock/pinmux tables), or is overhead to add runtime detection of which block of code to use, which simply isn't needed in the current model.
In my opinion, firmware/bootloaders run on a single specific board, whereas full-featured operating systems support multiple systems.
As an aside, I've wondered whether U-Boot should be split into multiple parts; one HW-specific binary providing various drivers (e.g. via DM-related APIs?) and the other containing just high-level user-interface code such as the shell, high-level USB/... protocols, which would only call into those APIs. Still, I don't think we're anywhere close to that, and I'm not aware that it's a goal of the project at the moment.
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Shouldn't we head towards that rather than making it harder?
I don't see any need for that, no.
U-Boot is built for a specific board (or in some cases a set of extremely closely related set of boards, such as the RPI A/B/A+/B+). There's no need to determine almost anything at run-time since almost all information is known at compile time, with exceptions such as standardized enumerable buses such as USB, PCIe. If we support multiple HW in a single binary, it gets bloated with code that simply isn't going to be used, since all the extra code is either for a platform that the build won't be installed on (e.g. clock/pinmux tables), or is overhead to add runtime detection of which block of code to use, which simply isn't needed in the current model.
It's not so much that. Presumably a build for a particular board would not include support for and SoC it doesn't have. But it is still useful to build the code. For example it would be nice to have an overall Tegra build that enables all SoCs to avoid building every board.
So it is a serious question. I suspect the main impediment may be moving the clock and other core stuff to driver model.
In my opinion, firmware/bootloaders run on a single specific board, whereas full-featured operating systems support multiple systems.
Except when the boards are pretty similar. Also, doesn't barebox have only one build for Tegra?
As an aside, I've wondered whether U-Boot should be split into multiple parts; one HW-specific binary providing various drivers (e.g. via DM-related APIs?) and the other containing just high-level user-interface code such as the shell, high-level USB/... protocols, which would only call into those APIs. Still, I don't think we're anywhere close to that, and I'm not aware that it's a goal of the project at the moment.
Well it gets built as one binary, but there's a pretty clear separation in the code, at least with driver model. What's the purpose of this?
Regards, Simon
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
Shouldn't we head towards that rather than making it harder?
I don't see any need for that, no.
U-Boot is built for a specific board (or in some cases a set of extremely closely related set of boards, such as the RPI A/B/A+/B+). There's no need to determine almost anything at run-time since almost all information is known at compile time, with exceptions such as standardized enumerable buses such as USB, PCIe. If we support multiple HW in a single binary, it gets bloated with code that simply isn't going to be used, since all the extra code is either for a platform that the build won't be installed on (e.g. clock/pinmux tables), or is overhead to add runtime detection of which block of code to use, which simply isn't needed in the current model.
It's not so much that. Presumably a build for a particular board would not include support for and SoC it doesn't have. But it is still useful to build the code. For example it would be nice to have an overall Tegra build that enables all SoCs to avoid building every board.
So it is a serious question. I suspect the main impediment may be moving the clock and other core stuff to driver model.
Yes, everything is a bit too tightly coupled at the moment, and in many cases each SoC-specific implementation exposes the same global symbols which clients use. DM or similar conversions may well solve a lot of this.
In my opinion, firmware/bootloaders run on a single specific board, whereas full-featured operating systems support multiple systems.
Except when the boards are pretty similar. Also, doesn't barebox have only one build for Tegra?
I haven't looked at Barebox much. IIRC it only supports Tegra20 and not later SoCs which could simplify things. Besides, I'm not arguing that it's impossible to make a unified binary, simply that I don't see any need to do so, except perhaps your compile-coverage suggestion.
As an aside, I've wondered whether U-Boot should be split into multiple parts; one HW-specific binary providing various drivers (e.g. via DM-related APIs?) and the other containing just high-level user-interface code such as the shell, high-level USB/... protocols, which would only call into those APIs. Still, I don't think we're anywhere close to that, and I'm not aware that it's a goal of the project at the moment.
Well it gets built as one binary, but there's a pretty clear separation in the code, at least with driver model. What's the purpose of this?
It would allow the HW-agnostic portion to be compiled once (or once for a CPU ISA) and re-used with any of the HW-/board-specific "driver" blobs. It'd get use to "single binary" for the generic stuff, but without requiring the for HW-specific code. Perhaps the generic portion could even run on top of other driver stacks if they implemented the API it needed! However, this does ignore potential feature differences in the common binary, e.g. someone might want dfu/ums commands, but someone else might not need them and hence consider them bloat. Still, those configurations would be differentiated by feature more than HW, so it might still be useful.
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
Shouldn't we head towards that rather than making it harder?
I don't see any need for that, no.
U-Boot is built for a specific board (or in some cases a set of extremely closely related set of boards, such as the RPI A/B/A+/B+). There's no need to determine almost anything at run-time since almost all information is known at compile time, with exceptions such as standardized enumerable buses such as USB, PCIe. If we support multiple HW in a single binary, it gets bloated with code that simply isn't going to be used, since all the extra code is either for a platform that the build won't be installed on (e.g. clock/pinmux tables), or is overhead to add runtime detection of which block of code to use, which simply isn't needed in the current model.
It's not so much that. Presumably a build for a particular board would not include support for and SoC it doesn't have. But it is still useful to build the code. For example it would be nice to have an overall Tegra build that enables all SoCs to avoid building every board.
So it is a serious question. I suspect the main impediment may be moving the clock and other core stuff to driver model.
Yes, everything is a bit too tightly coupled at the moment, and in many cases each SoC-specific implementation exposes the same global symbols which clients use. DM or similar conversions may well solve a lot of this.
With a suitable API (even it if is pretty basic) the coupling can often go away. The current driver-model pinctrl/clock APIs are pretty simple, but they are effective in this regard for the SoCs I've tried.
In my opinion, firmware/bootloaders run on a single specific board, whereas full-featured operating systems support multiple systems.
Except when the boards are pretty similar. Also, doesn't barebox have only one build for Tegra?
I haven't looked at Barebox much. IIRC it only supports Tegra20 and not later SoCs which could simplify things. Besides, I'm not arguing that it's impossible to make a unified binary, simply that I don't see any need to do so, except perhaps your compile-coverage suggestion.
Sure. I think it might help push the APIs along though. I recall creating a clock API for tegra20 some years ago. I think if we go to the next level (clock drivers for each SoC) the SoC differences start to look a lot less. It's mostly this core code that is the problem and much of it should move to drivers IMO.
As an aside, I've wondered whether U-Boot should be split into multiple parts; one HW-specific binary providing various drivers (e.g. via DM-related APIs?) and the other containing just high-level user-interface code such as the shell, high-level USB/... protocols, which would only call into those APIs. Still, I don't think we're anywhere close to that, and I'm not aware that it's a goal of the project at the moment.
Well it gets built as one binary, but there's a pretty clear separation in the code, at least with driver model. What's the purpose of this?
It would allow the HW-agnostic portion to be compiled once (or once for a CPU ISA) and re-used with any of the HW-/board-specific "driver" blobs. It'd get use to "single binary" for the generic stuff, but without requiring the for HW-specific code. Perhaps the generic portion could even run on top of other driver stacks if they implemented the API it needed! However, this does ignore potential feature differences in the common binary, e.g. someone might want dfu/ums commands, but someone else might not need them and hence consider them bloat. Still, those configurations would be differentiated by feature more than HW, so it might still be useful.
Sounds cool. It would certainly tidy up the U-Boot API a lot, I suppose. You could have a micro-module approach where every little feature is its own loadable module. But really, what is the benefit?
Regards, Simon
On 04/29/2016 08:02 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on SoC ID. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 106 ++++++++++----------------------- arch/arm/mach-tegra/cache.c | 20 +++---- arch/arm/mach-tegra/cpu.c | 16 ++--- arch/arm/mach-tegra/cpu.h | 6 -- arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- 5 files changed, 51 insertions(+), 117 deletions(-)What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
I'm not sure if you still object to this patch for now, or would be happy giving it an ack?
Hi Stephen,
On 29 April 2016 at 10:27, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/29/2016 08:02 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote: > > > > From: Stephen Warren swarren@nvidia.com > > U-Boot is compiled for a single board, which in turn uses a specific > SoC. > There's no need to make runtime decisions based on SoC ID. While > there's > certainly an argument for making the code support different SoCs at > run-time, the Tegra code is so far from that possible ideal that the > existing runtime code is an anomaly. If this changes in the future, > all > runtime decisions should likely be based on DT anyway. > > Signed-off-by: Stephen Warren swarren@nvidia.com > --- > arch/arm/mach-tegra/ap.c | 106 > ++++++++++----------------------- > arch/arm/mach-tegra/cache.c | 20 +++---- > arch/arm/mach-tegra/cpu.c | 16 ++--- > arch/arm/mach-tegra/cpu.h | 6 -- > arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- > 5 files changed, 51 insertions(+), 117 deletions(-)
What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
I'm not sure if you still object to this patch for now, or would be happy giving it an ack?
Sorry, I still feel this is going in the wrong direction...CONFIG_TEGRA124 should mean that the code supports it, rather than the code exclusively supports it.
In your commit message you say:
"While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway."
Or even build time.... That statement seems like saying that everything is so terrible that we might as well give up.
What's your plan to move code into drivers? I am happy to help move things over and get towards the goal rather than further away. But really that should happen first.
Also, the model that seems to be emerging is that SPL detects the platform and passes the correct DT to U-Boot proper.
Specifically I think the end state should be: - Most SoC code is in drivers using driver model - It is possible to build most of the tegra code without building each SoC (just by having a 'tegra' board which enables all drivers) - If someone wanted to support multiple SoCs it would not be impossible to do so (even if mainline doesn't make it) - New SoCs are supported mostly by adding new drivers (although there is always of course some core/start-up code)
Do you agree with that?
Regards, Simon
Hi Stephen,
On 29 April 2016 at 10:53, Simon Glass sjg@chromium.org wrote:
Hi Stephen,
On 29 April 2016 at 10:27, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/29/2016 08:02 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/23/2016 11:14 AM, Simon Glass wrote: > > > > Hi Stephen, > > On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org > wrote: >> >> >> >> From: Stephen Warren swarren@nvidia.com >> >> U-Boot is compiled for a single board, which in turn uses a specific >> SoC. >> There's no need to make runtime decisions based on SoC ID. While >> there's >> certainly an argument for making the code support different SoCs at >> run-time, the Tegra code is so far from that possible ideal that the >> existing runtime code is an anomaly. If this changes in the future, >> all >> runtime decisions should likely be based on DT anyway. >> >> Signed-off-by: Stephen Warren swarren@nvidia.com >> --- >> arch/arm/mach-tegra/ap.c | 106 >> ++++++++++----------------------- >> arch/arm/mach-tegra/cache.c | 20 +++---- >> arch/arm/mach-tegra/cpu.c | 16 ++--- >> arch/arm/mach-tegra/cpu.h | 6 -- >> arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- >> 5 files changed, 51 insertions(+), 117 deletions(-) > > > > What exactly is missing to prevent multi-arch support?
In a word: everything:-)
Pretty much all decisions in core architecture code, core Tegra code, drivers, and even board files are currently made at compile time. For example, consider drivers where the register layouts are different between different SoCs; not just new fields added, but existing fields moved to different offsets. Right now, we handle this by changing the register struct definition at compile time. To support multiple chips, we'd have to either (a) link in n copies of the driver, one per register layout, or (b) rework the driver to use #defines and runtime calculations for register offsets, like the Linux kernel drivers do. Tegra USB is one example. The pinmux and clock drivers have a significantly different sets of pins/clocks/resets/... per SoC, and enums/tables describing those sets are currently configured at compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured at compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
I'm not sure if you still object to this patch for now, or would be happy giving it an ack?
And just to be clear, I'm always keen to move things forward and I can see you have put a lot of work into this series. It would be easier to just apply it as is. What I am looking for is how we might get closer to the goal, perhaps after this series. This series has exposed this which is why I have brought it up.
Sorry, I still feel this is going in the wrong direction...CONFIG_TEGRA124 should mean that the code supports it, rather than the code exclusively supports it.
In your commit message you say:
"While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway."
Or even build time.... That statement seems like saying that everything is so terrible that we might as well give up.
What's your plan to move code into drivers? I am happy to help move things over and get towards the goal rather than further away. But really that should happen first.
Also, the model that seems to be emerging is that SPL detects the platform and passes the correct DT to U-Boot proper.
Specifically I think the end state should be:
- Most SoC code is in drivers using driver model
- It is possible to build most of the tegra code without building each
SoC (just by having a 'tegra' board which enables all drivers)
- If someone wanted to support multiple SoCs it would not be
impossible to do so (even if mainline doesn't make it)
- New SoCs are supported mostly by adding new drivers (although there
is always of course some core/start-up code)
Do you agree with that?
Regards, Simon
Regards, Simon
On 04/29/2016 11:42 AM, Simon Glass wrote:
Hi Stephen,
On 29 April 2016 at 10:53, Simon Glass sjg@chromium.org wrote:
Hi Stephen,
On 29 April 2016 at 10:27, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/29/2016 08:02 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote:
Hi Stephen,
On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org wrote: > > > On 04/23/2016 11:14 AM, Simon Glass wrote: >> >> >> >> Hi Stephen, >> >> On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org >> wrote: >>> >>> >>> >>> From: Stephen Warren swarren@nvidia.com >>> >>> U-Boot is compiled for a single board, which in turn uses a specific >>> SoC. >>> There's no need to make runtime decisions based on SoC ID. While >>> there's >>> certainly an argument for making the code support different SoCs at >>> run-time, the Tegra code is so far from that possible ideal that the >>> existing runtime code is an anomaly. If this changes in the future, >>> all >>> runtime decisions should likely be based on DT anyway. >>> >>> Signed-off-by: Stephen Warren swarren@nvidia.com >>> --- >>> arch/arm/mach-tegra/ap.c | 106 >>> ++++++++++----------------------- >>> arch/arm/mach-tegra/cache.c | 20 +++---- >>> arch/arm/mach-tegra/cpu.c | 16 ++--- >>> arch/arm/mach-tegra/cpu.h | 6 -- >>> arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- >>> 5 files changed, 51 insertions(+), 117 deletions(-) >> >> >> >> What exactly is missing to prevent multi-arch support? > > > In a word: everything:-) > > Pretty much all decisions in core architecture code, core Tegra code, > drivers, and even board files are currently made at compile time. For > example, consider drivers where the register layouts are different > between > different SoCs; not just new fields added, but existing fields moved to > different offsets. Right now, we handle this by changing the register > struct > definition at compile time. To support multiple chips, we'd have to > either > (a) link in n copies of the driver, one per register layout, or (b) > rework > the driver to use #defines and runtime calculations for register > offsets, > like the Linux kernel drivers do. Tegra USB is one example. The pinmux > and > clock drivers have a significantly different sets of > pins/clocks/resets/... > per SoC, and enums/tables describing those sets are currently > configured at > compile time. Some PMIC constants (e.g. vdd_cpu voltage) are configured > at > compile-time, and even differ per board.
I wonder how far we would get by converting clock, pinctrl, reset to driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
I'm not sure if you still object to this patch for now, or would be happy giving it an ack?
And just to be clear, I'm always keen to move things forward and I can see you have put a lot of work into this series. It would be easier to just apply it as is. What I am looking for is how we might get closer to the goal, perhaps after this series. This series has exposed this which is why I have brought it up.
So, just to be clear: TomW can apply this (once I post V2) even if you're not giving an ack?
Sorry, I still feel this is going in the wrong direction...CONFIG_TEGRA124 should mean that the code supports it, rather than the code exclusively supports it.
That's certainly not what it means right now, and my intention in this series was not to address any short-comings in the current meanings of Kconfig.
No matter what, if we do drive all this core SoC code from DT eventually, I don't imagine tegra_get_chip() will be the way code gets dispatched between multiple chips in the future, so removing it now shouldn't hurt any later conversion to runtime multi-chip support.
In practice in a DT-driven world, I'd expect:
- The code in enable_scu() to be part of some Tegra20-specific "SoC driver" or similar, and hence not need any runtime support restored.
- The code in cache.c to be part of some specific cache drivers, which would only be instantiated on Tegra20, and hence not need any runtime support restored.
- The code in cpu.c to be moved into a clock driver, and base on some per-SoC table in the clock driver, and hence not need any runtime special-casing.
As such, I don't see reverting any of this patch being reverted later, and I don't believe leaving in these runtime calls would make it any easier to refactor the code into drivers later.
In your commit message you say:
"While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway."
Or even build time.... That statement seems like saying that everything is so terrible that we might as well give up.
I'm just being practical. Please note in particular the comment about basing such decisions on DT; that and refactoring the code into DT-instantiated drivers would leave it so different that the tiny number of current runtime switches doesn't help anything.
What's your plan to move code into drivers? I am happy to help move things over and get towards the goal rather than further away. But really that should happen first.
I don't have a plan for anything besides the clock and reset drivers at the moment. I /think/ that most of the rest of the code in arch/arm/mach-tegra simply won't be needed on Tegra186. We'll see; I only have UART and GPIO working right now, well and a very hacked-up MMC to avoid clock/reset access. There is a large amount of work left that I haven't started looking at yet.
Also, the model that seems to be emerging is that SPL detects the platform and passes the correct DT to U-Boot proper.
There is no SPL on Tegra210 or later. It would be a pity to have to introduce one just to do runtime DT selection when there's no need to have runtime DT selection.
Specifically I think the end state should be:
- Most SoC code is in drivers using driver model
That is fine in many cases. There's plenty of low-level bootstrap code where I'm not sure that it's worth it. Equally, given that you have stated DM==DT, I worry about the implications of that statement if universally applied, rather than selectively/pragmatically applied.
- It is possible to build most of the tegra code without building each
SoC (just by having a 'tegra' board which enables all drivers)
I'm not convinced this is worth it universally.
For the purposes of actually running a binary on a device, I believe there is zero need for this.
For compile coverage it might be nice, especially for driver code, although running buildman on one Tegra board for each SoC generation doesn't take much time.
Even for drivers that solely use generic (non-SoC-version-specific) APIs, this would be difficult in some cases. This plays back into my earlier comments elsewhere about structs-vs-defines for register address calculations. Register layouts of some devices vary incompatibly between Tegra SoC generations. With a define-based driver, this can all be handled at run-time. With a struct-based driver, one must compile the code once per register layout. Rather than invest in making a "compile test" build that does this, which would require various build system work, it's much simpler to just compile the driver multiple times as part of a set of board builds, which already works today. The result is still compiling the code n times, so there wouldn't be much time saving wrapping everything into one build.
- If someone wanted to support multiple SoCs it would not be
impossible to do so (even if mainline doesn't make it)
I don't think it's a good idea to support features that mainline doesn't use. They'll bit-rot and not work anyway. I also can't see any use-case for such a build.
- New SoCs are supported mostly by adding new drivers (although there
is always of course some core/start-up code)
Yes, it certainly makes sense to use drivers for functionality which other pieces of the code must interact with in a generic way. For example, calls from I2C/MMC drivers to clock/reset APIs.
I expect some debate over what code is core/start-up code though. For example, static pinmux setup fits that category for me, since there's no generic code that needs to interface with it.
Hi Stephen,
On 29 April 2016 at 13:21, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/29/2016 11:42 AM, Simon Glass wrote:
Hi Stephen,
On 29 April 2016 at 10:53, Simon Glass sjg@chromium.org wrote:
Hi Stephen,
On 29 April 2016 at 10:27, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/29/2016 08:02 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:13, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 08:50 AM, Simon Glass wrote: > > > > Hi Stephen, > > On 25 April 2016 at 13:25, Stephen Warren swarren@wwwdotorg.org > wrote: >> >> >> >> On 04/23/2016 11:14 AM, Simon Glass wrote: >>> >>> >>> >>> >>> Hi Stephen, >>> >>> On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org >>> wrote: >>>> >>>> >>>> >>>> >>>> From: Stephen Warren swarren@nvidia.com >>>> >>>> U-Boot is compiled for a single board, which in turn uses a >>>> specific >>>> SoC. >>>> There's no need to make runtime decisions based on SoC ID. While >>>> there's >>>> certainly an argument for making the code support different SoCs >>>> at >>>> run-time, the Tegra code is so far from that possible ideal that >>>> the >>>> existing runtime code is an anomaly. If this changes in the >>>> future, >>>> all >>>> runtime decisions should likely be based on DT anyway. >>>> >>>> Signed-off-by: Stephen Warren swarren@nvidia.com >>>> --- >>>> arch/arm/mach-tegra/ap.c | 106 >>>> ++++++++++----------------------- >>>> arch/arm/mach-tegra/cache.c | 20 +++---- >>>> arch/arm/mach-tegra/cpu.c | 16 ++--- >>>> arch/arm/mach-tegra/cpu.h | 6 -- >>>> arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++----- >>>> 5 files changed, 51 insertions(+), 117 deletions(-) >>> >>> >>> >>> >>> What exactly is missing to prevent multi-arch support? >> >> >> >> In a word: everything:-) >> >> Pretty much all decisions in core architecture code, core Tegra >> code, >> drivers, and even board files are currently made at compile time. >> For >> example, consider drivers where the register layouts are different >> between >> different SoCs; not just new fields added, but existing fields moved >> to >> different offsets. Right now, we handle this by changing the >> register >> struct >> definition at compile time. To support multiple chips, we'd have to >> either >> (a) link in n copies of the driver, one per register layout, or (b) >> rework >> the driver to use #defines and runtime calculations for register >> offsets, >> like the Linux kernel drivers do. Tegra USB is one example. The >> pinmux >> and >> clock drivers have a significantly different sets of >> pins/clocks/resets/... >> per SoC, and enums/tables describing those sets are currently >> configured at >> compile time. Some PMIC constants (e.g. vdd_cpu voltage) are >> configured >> at >> compile-time, and even differ per board. > > > > I wonder how far we would get by converting clock, pinctrl, reset to > driver model drivers?
Well, I expect we'll find out soon. The next SoC has radically different clock/reset mechanisms, so we'll need to switch to standardized APIs for clock/reset on Tegra to isolate drivers from those differences, and I imagine that conversion would also involve conversion to DM since any standard APIs probably assume use of DM. I haven't investigated this in detail yet though.
That sounds like a good move.
I'm not sure if you still object to this patch for now, or would be happy giving it an ack?
And just to be clear, I'm always keen to move things forward and I can see you have put a lot of work into this series. It would be easier to just apply it as is. What I am looking for is how we might get closer to the goal, perhaps after this series. This series has exposed this which is why I have brought it up.
So, just to be clear: TomW can apply this (once I post V2) even if you're not giving an ack?
Provided you are OK with using drivers for clock, pinctrl etc. with your new Tegra work. I'd really like to move away from all this code in arch/arm, private APIs, etc..
Sorry, I still feel this is going in the wrong direction...CONFIG_TEGRA124 should mean that the code supports it, rather than the code exclusively supports it.
That's certainly not what it means right now, and my intention in this series was not to address any short-comings in the current meanings of
Kconfig.
Well it means that in quite a few places - e.g. this one that you are removing.
No matter what, if we do drive all this core SoC code from DT eventually, I don't imagine tegra_get_chip() will be the way code gets dispatched between multiple chips in the future, so removing it now shouldn't hurt any later conversion to runtime multi-chip support.
In practice in a DT-driven world, I'd expect:
- The code in enable_scu() to be part of some Tegra20-specific "SoC driver"
or similar, and hence not need any runtime support restored.
- The code in cache.c to be part of some specific cache drivers, which would
only be instantiated on Tegra20, and hence not need any runtime support restored.
- The code in cpu.c to be moved into a clock driver, and base on some
per-SoC table in the clock driver, and hence not need any runtime special-casing.
As such, I don't see reverting any of this patch being reverted later, and I don't believe leaving in these runtime calls would make it any easier to refactor the code into drivers later.
Sounds reasonable. So long as we are agreed on using drivers then I am OK with it as a means to an end.
In your commit message you say:
"While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway."
Or even build time.... That statement seems like saying that everything is so terrible that we might as well give up.
I'm just being practical. Please note in particular the comment about basing such decisions on DT; that and refactoring the code into DT-instantiated drivers would leave it so different that the tiny number of current runtime switches doesn't help anything.
Right, but you are actually removing functions that detect the SoC. That is surely heading the wrong way.
What's your plan to move code into drivers? I am happy to help move things over and get towards the goal rather than further away. But really that should happen first.
I don't have a plan for anything besides the clock and reset drivers at the moment. I /think/ that most of the rest of the code in arch/arm/mach-tegra simply won't be needed on Tegra186. We'll see; I only have UART and GPIO working right now, well and a very hacked-up MMC to avoid clock/reset access. There is a large amount of work left that I haven't started looking at yet.
OK good.
Also, the model that seems to be emerging is that SPL detects the platform and passes the correct DT to U-Boot proper.
There is no SPL on Tegra210 or later. It would be a pity to have to introduce one just to do runtime DT selection when there's no need to have runtime DT selection.
How does the platform start up? Does it use BCT and then jump straight into U-Boot?
Specifically I think the end state should be:
- Most SoC code is in drivers using driver model
That is fine in many cases. There's plenty of low-level bootstrap code where I'm not sure that it's worth it. Equally, given that you have stated DM==DT, I worry about the implications of that statement if universally applied, rather than selectively/pragmatically applied.
I have not stated that DM==DT. Where there are reasons to use platform data we can do that. See this comment in the driver-model README:
*** Note: platform data is the old way of doing things. It is *** basically a C structure which is passed to drivers to tell them about *** platform-specific settings like the address of its registers, bus *** speed, etc. Device tree is now the preferred way of handling this. *** Unless you have a good reason not to use device tree (the main one *** being you need serial support in SPL and don't have enough SRAM for *** the cut-down device tree and libfdt libraries) you should stay away *** from platform data.
This is a boot loader. We need to be pragmatic. This is why I push back on core driver-model code bloat.
- It is possible to build most of the tegra code without building each
SoC (just by having a 'tegra' board which enables all drivers)
I'm not convinced this is worth it universally.
For the purposes of actually running a binary on a device, I believe there is zero need for this.
For compile coverage it might be nice, especially for driver code, although running buildman on one Tegra board for each SoC generation doesn't take much time.
Even for drivers that solely use generic (non-SoC-version-specific) APIs, this would be difficult in some cases. This plays back into my earlier comments elsewhere about structs-vs-defines for register address calculations. Register layouts of some devices vary incompatibly between Tegra SoC generations. With a define-based driver, this can all be handled at run-time. With a struct-based driver, one must compile the code once per register layout. Rather than invest in making a "compile test" build that does this, which would require various build system work, it's much simpler to just compile the driver multiple times as part of a set of board builds, which already works today. The result is still compiling the code n times, so there wouldn't be much time saving wrapping everything into one build.
Well your hardware guys really should make up their mind. Is there any code review? And s/w people should have a system (with serial driver) running before tape-out and catch this stuff.
But in any case, struct-based stuff is not a requirement now. I believe a lot of people prefer it (including me) but in the case you raise it isn't practical. See ns16550 for how this can be done badly.
- If someone wanted to support multiple SoCs it would not be
impossible to do so (even if mainline doesn't make it)
I don't think it's a good idea to support features that mainline doesn't use. They'll bit-rot and not work anyway. I also can't see any use-case for such a build.
While SoC vendors think of the SoC as a the most important factor in the platform, we are starting to see similar devices using different SoCs, or at least different variants. From a user point of view I'd rather not worry about which Raspberry Pi I have, for example, so long as I can build something that boots.
- New SoCs are supported mostly by adding new drivers (although there
is always of course some core/start-up code)
Yes, it certainly makes sense to use drivers for functionality which other pieces of the code must interact with in a generic way. For example, calls from I2C/MMC drivers to clock/reset APIs.
I expect some debate over what code is core/start-up code though. For example, static pinmux setup fits that category for me, since there's no generic code that needs to interface with it.
So please put your pinmux code in a pinctrl driver, even it is just in the probe() method.
Also I have a Tegra124 platform now. Once the smoke has cleared with your work I'd like to take a look at how to improve things.
Regards, Simon
From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on CPU count. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/cpu.c | 31 +++---------------------------- 1 file changed, 3 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index cc60908677a1..30964dde8b19 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> @@ -15,29 +14,6 @@ #include "pmc.h" #include "scu.h"
-int get_num_cpus(void) -{ - struct apb_misc_gp_ctlr *gp; - uint rev; - debug("%s entry\n", __func__); - - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - - switch (rev) { - case CHIPID_TEGRA20: - return 2; - break; - case CHIPID_TEGRA30: - case CHIPID_TEGRA114: - case CHIPID_TEGRA124: - case CHIPID_TEGRA210: - default: - return 4; - break; - } -} - /* * Timing tables for each SOC for all four oscillator options. */ @@ -283,7 +259,7 @@ void enable_cpu_clock(int enable) */ clk = readl(&clkrst->crc_clk_cpu_cmplx); clk |= 1 << CPU1_CLK_STP_SHIFT; - if (get_num_cpus() == 4) + if (MAX_NUM_CPU == 4) clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
/* Stop/Unstop the CPU clock */ @@ -358,12 +334,11 @@ void reset_A9_cpu(int reset) * are multiple processors in the CPU complex. */ int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug; - int num_cpus = get_num_cpus(); int cpu;
debug("%s entry\n", __func__); /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ - for (cpu = 1; cpu < num_cpus; cpu++) + for (cpu = 1; cpu < MAX_NUM_CPU; cpu++) reset_cmplx_set_enable(cpu, mask, 1); reset_cmplx_set_enable(0, mask, reset);
@@ -393,7 +368,7 @@ void clock_enable_coresight(int enable) rst = CORESIGHT_UNLOCK; writel(rst, CSITE_CPU_DBG0_LAR); writel(rst, CSITE_CPU_DBG1_LAR); - if (get_num_cpus() == 4) { + if (MAX_NUM_CPU == 4) { writel(rst, CSITE_CPU_DBG2_LAR); writel(rst, CSITE_CPU_DBG3_LAR); }
From: Stephen Warren swarren@nvidia.com
The only place this is still used is Tegra20's warmboot.c. Keep the T20 copy around for that use, but remove the other unused duplicates.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/gp_padctrl.h | 24 -------- arch/arm/include/asm/arch-tegra/tegra.h | 1 - arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 67 --------------------- arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 68 ---------------------- arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 68 ---------------------- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 49 ---------------- .../tegra20}/gp_padctrl.h | 13 +++-- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- board/toradex/colibri_t30/colibri_t30.c | 1 - 9 files changed, 9 insertions(+), 284 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra114/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gp_padctrl.h rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/gp_padctrl.h (88%)
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h deleted file mode 100644 index 854966a30f9e..000000000000 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_GP_PADCTRL_H_ -#define _TEGRA_GP_PADCTRL_H_ - -/* bit fields definitions for APB_MISC_GP_HIDREV register */ -#define HIDREV_CHIPID_SHIFT 8 -#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) -#define HIDREV_MAJORPREV_SHIFT 4 -#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) - -/* CHIPID field returned from APB_MISC_GP_HIDREV register */ -#define CHIPID_TEGRA20 0x20 -#define CHIPID_TEGRA30 0x30 -#define CHIPID_TEGRA114 0x35 -#define CHIPID_TEGRA124 0x40 -#define CHIPID_TEGRA210 0x21 - -#endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 4051a7d26630..0de6aedf6b2a 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -18,7 +18,6 @@ #define NV_PA_GPIO_BASE 0x6000D000 #define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 -#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h deleted file mode 100644 index 24416f4a5c52..000000000000 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA114_GP_PADCTRL_H_ -#define _TEGRA114_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -#endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h deleted file mode 100644 index 406edd0d7ea6..000000000000 --- a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_GP_PADCTRL_H_ -#define _TEGRA124_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h deleted file mode 100644 index ead620534c7d..000000000000 --- a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_GP_PADCTRL_H_ -#define _TEGRA210_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -#endif /* _TEGRA210_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h deleted file mode 100644 index 5453555d3ea3..000000000000 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA30_GP_PADCTRL_H_ -#define _TEGRA30_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ - u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ - u32 reserved1[7]; /* 0xD0-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ -}; - -#endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/mach-tegra/tegra20/gp_padctrl.h similarity index 88% rename from arch/arm/include/asm/arch-tegra20/gp_padctrl.h rename to arch/arm/mach-tegra/tegra20/gp_padctrl.h index 6631871ce574..99fc2044f05c 100644 --- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h +++ b/arch/arm/mach-tegra/tegra20/gp_padctrl.h @@ -1,14 +1,14 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA20_GP_PADCTRL_H_ -#define _TEGRA20_GP_PADCTRL_H_ +#ifndef _TEGRA20_GP_PADCTRL_H +#define _TEGRA20_GP_PADCTRL_H
-#include <asm/arch-tegra/gp_padctrl.h> +#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
/* APB_MISC_GP and padctrl registers */ struct apb_misc_gp_ctlr { @@ -47,4 +47,7 @@ struct apb_misc_gp_ctlr { u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ };
-#endif /* _TEGRA20_GP_PADCTRL_H_ */ +#define HIDREV_MAJORPREV_SHIFT 4 +#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) + +#endif diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 1159f05a5dc3..dd3da116faef 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -9,7 +9,6 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/clock.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> @@ -19,6 +18,7 @@ #include "../pmc.h" #include "crypto.h" #include "emc_priv.h" +#include "gp_padctrl.h" #include "sdram_param.h" #include "warmboot.h"
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 4312f79f2d00..e0e7deef579a 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -11,7 +11,6 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> #include "pinmux-config-colibri_t30.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
The only place this is still used is Tegra20's warmboot.c. Keep the T20 copy around for that use, but remove the other unused duplicates.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 24 -------- arch/arm/include/asm/arch-tegra/tegra.h | 1 - arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 67 --------------------- arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 68 ---------------------- arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 68 ---------------------- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 49 ---------------- .../tegra20}/gp_padctrl.h | 13 +++-- arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- board/toradex/colibri_t30/colibri_t30.c | 1 - 9 files changed, 9 insertions(+), 284 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra114/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h delete mode 100644 arch/arm/include/asm/arch-tegra30/gp_padctrl.h rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/gp_padctrl.h (88%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This is part of the internal implementation of tegra_get_chip_sku().
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 14 +++----------- arch/arm/mach-tegra/cpu.c | 5 +---- arch/arm/mach-tegra/cpu.h | 6 ------ 3 files changed, 4 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a8e3e8b7dfcb..f354f7d87b14 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -18,23 +18,15 @@ #include "pmc.h" #include "scu.h"
-int tegra_get_sku_info(void) +int tegra_get_chip_sku(void) { - int sku_id; +#ifdef CONFIG_TEGRA20 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + uint sku_id;
sku_id = readl(&fuse->sku_info) & 0xff; debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
- return sku_id; -} - -int tegra_get_chip_sku(void) -{ -#ifdef CONFIG_TEGRA20 - uint sku_id; - - sku_id = tegra_get_sku_info(); switch (sku_id) { case SKU_ID_T20_7: case SKU_ID_T20: diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 30964dde8b19..f7285eb0de8c 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -206,15 +206,12 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int sku_info, chip_sku; + int chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("%s entry\n", __func__);
/* get SKU info */ - sku_info = tegra_get_sku_info(); - debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); - /* get chip SKU, combo of the above info */ chip_sku = tegra_get_chip_sku(); debug("%s: Chip SKU = %d\n", __func__, chip_sku); diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index ee4f7868baf7..9e5bf39ebfd7 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -64,12 +64,6 @@ void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); /** - * Returns the SKU ID from the sku_info register - * - * @return SKU ID - see SKU_ID_Txx... - */ -int tegra_get_sku_info(void); -/** * Works out the SOC/SKU type used for clocks settings * * @return SOC type - see TEGRA_SOC...
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This is part of the internal implementation of tegra_get_chip_sku().
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 14 +++----------- arch/arm/mach-tegra/cpu.c | 5 +---- arch/arm/mach-tegra/cpu.h | 6 ------ 3 files changed, 4 insertions(+), 21 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
EMC scaling is specific to Tegra20. Move the code into tegra20/ to isolate it. If it becomes more generic in the future, it should likely be moved somewhere in drivers/, but at the least be reworked to have a leaner and cleaner interface to its caller (i.e. fewer dependencies, interactions).
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/board2.c | 6 ++++-- arch/arm/mach-tegra/emc.c | 36 ---------------------------------- arch/arm/mach-tegra/emc.h | 27 ------------------------- arch/arm/mach-tegra/tegra20/Makefile | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 34 +++++++++++++++++++++++++++++++- arch/arm/mach-tegra/tegra20/emc.h | 14 +++++++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 4 ++-- include/configs/seaboard.h | 4 ++-- 9 files changed, 57 insertions(+), 73 deletions(-) delete mode 100644 arch/arm/mach-tegra/emc.c delete mode 100644 arch/arm/mach-tegra/emc.h create mode 100644 arch/arm/mach-tegra/tegra20/emc.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 197bdfeadd57..f1c1f84fc933 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -25,7 +25,6 @@ obj-y += powergate.o obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_SPL_BUILD) += i2c_early.o
ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 684d4a5ad853..c3e6fbf2a5a4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -30,9 +30,11 @@ #include <i2c.h> #include <spi.h> #include "cpu.h" -#include "emc.h" #include "gpu.h" #include "pmc.h" +#ifdef CONFIG_TEGRA20_CLOCK_SCALING +#include "tegra20/emc.h" +#endif #ifdef CONFIG_TEGRA_LP0 #include "tegra20/warmboot.h" #endif @@ -136,7 +138,7 @@ int board_init(void) # ifdef CONFIG_TEGRA_PMU if (pmu_set_nominal()) debug("Failed to select nominal voltages\n"); -# ifdef CONFIG_TEGRA_CLOCK_SCALING +# ifdef CONFIG_TEGRA20_CLOCK_SCALING err = board_emc_init(); if (err) debug("Memory controller init failed: %d\n", err); diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c deleted file mode 100644 index 86aba51e398e..000000000000 --- a/arch/arm/mach-tegra/emc.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/tegra.h> -#include <asm/arch-tegra/clk_rst.h> -#include "emc.h" -#include "cpu.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* These rates are hard-coded for now, until fdt provides them */ -#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) -#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) - -int board_emc_init(void) -{ - unsigned rate; - - switch (tegra_get_chip_sku()) { - default: - case TEGRA_SOC_T20: - rate = EMC_SDRAM_RATE_T20; - break; - case TEGRA_SOC_T25: - rate = EMC_SDRAM_RATE_T25; - break; - } - return tegra_set_emc(gd->fdt_blob, rate); -} diff --git a/arch/arm/mach-tegra/emc.h b/arch/arm/mach-tegra/emc.h deleted file mode 100644 index 19527b67031e..000000000000 --- a/arch/arm/mach-tegra/emc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_EMC_H -#define _TEGRA_EMC_H - -/* Implemented in SoC-agnostic EMC code, called by core board code */ -int board_emc_init(void); - -/** - * Set up the EMC for the given rate. The timing parameters are retrieved - * from the device tree "nvidia,tegra20-emc" node and its - * "nvidia,tegra20-emc-table" sub-nodes. - * - * @param blob Device tree blob - * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) - * @return 0 if ok, else -ve error code (look in emc.c to decode it) - * - * Implemented by SoC-specific code. - */ -int tegra_set_emc(const void *blob, unsigned rate); - -#endif diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 17c19900e216..3cf1e7f113ce 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2010,2011 Nvidia Corporation. +# (C) Copyright 2010-2016 Nvidia Corporation. # # SPDX-License-Identifier: GPL-2.0+ # @@ -14,5 +14,5 @@ CFLAGS_warmboot_avp.o += -march=armv4t
obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_TEGRA20_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index c2569418ba9f..242defde00a6 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -11,9 +11,12 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include "../apb_misc.h" +#include "../cpu.h" #include "../emc.h" #include "emc_priv.h"
+DECLARE_GLOBAL_DATA_PTR; + /* * The EMC registers have shadow registers. When the EMC clock is updated * in the clock controller, the shadow registers are copied to the active @@ -239,7 +242,16 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, return 0; }
-int tegra_set_emc(const void *blob, unsigned rate) +/** + * Set up the EMC for the given rate. The timing parameters are retrieved + * from the device tree "nvidia,tegra20-emc" node and its + * "nvidia,tegra20-emc-table" sub-nodes. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @return 0 if ok, else -ve error code (look in emc.c to decode it) + */ +static int tegra_set_emc(const void *blob, unsigned rate) { struct emc_ctlr *emc; const u32 *table = NULL; @@ -269,3 +281,23 @@ int tegra_set_emc(const void *blob, unsigned rate)
return 0; } + +/* These rates are hard-coded for now, until fdt provides them */ +#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) +#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) + +int board_emc_init(void) +{ + unsigned rate; + + switch (tegra_get_chip_sku()) { + default: + case TEGRA_SOC_T20: + rate = EMC_SDRAM_RATE_T20; + break; + case TEGRA_SOC_T25: + rate = EMC_SDRAM_RATE_T25; + break; + } + return tegra_set_emc(gd->fdt_blob, rate); +} diff --git a/arch/arm/mach-tegra/tegra20/emc.h b/arch/arm/mach-tegra/tegra20/emc.h new file mode 100644 index 000000000000..f660113e6b0a --- /dev/null +++ b/arch/arm/mach-tegra/tegra20/emc.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA20_EMC_H +#define _TEGRA20_EMC_H + +/* Implemented in SoC-specific EMC code, called by core board code */ +int board_emc_init(void); + +#endif diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index dd3da116faef..d5f7e96eb07e 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -24,8 +24,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" +#ifndef CONFIG_TEGRA20_CLOCK_SCALING +#error "You must enable CONFIG_TEGRA20_CLOCK_SCALING to use CONFIG_TEGRA_LP0" #endif
/* diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 06112139ea8f..09509b45f993 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,7 +15,7 @@ #define CONFIG_AES #define CONFIG_TEGRA_PMU #define CONFIG_TPS6586X_POWER -#define CONFIG_TEGRA_CLOCK_SCALING +#define CONFIG_TEGRA20_CLOCK_SCALING
#include "tegra20-common.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
EMC scaling is specific to Tegra20. Move the code into tegra20/ to isolate it. If it becomes more generic in the future, it should likely be moved somewhere in drivers/, but at the least be reworked to have a leaner and cleaner interface to its caller (i.e. fewer dependencies, interactions).
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/board2.c | 6 ++++-- arch/arm/mach-tegra/emc.c | 36 ---------------------------------- arch/arm/mach-tegra/emc.h | 27 ------------------------- arch/arm/mach-tegra/tegra20/Makefile | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 34 +++++++++++++++++++++++++++++++- arch/arm/mach-tegra/tegra20/emc.h | 14 +++++++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 4 ++-- include/configs/seaboard.h | 4 ++-- 9 files changed, 57 insertions(+), 73 deletions(-) delete mode 100644 arch/arm/mach-tegra/emc.c delete mode 100644 arch/arm/mach-tegra/emc.h create mode 100644 arch/arm/mach-tegra/tegra20/emc.h
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Rather than building a large table of all possible PLLX configurations into U-Boot and having it select the right one at run-time, push the configuration into SoC-specific files, and have the linker pick up the correct one.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/cpu.c | 124 +--------------------------------- arch/arm/mach-tegra/cpu.h | 7 -- arch/arm/mach-tegra/pllx.h | 20 ++++++ arch/arm/mach-tegra/tegra114/Makefile | 3 +- arch/arm/mach-tegra/tegra114/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra124/Makefile | 3 +- arch/arm/mach-tegra/tegra124/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra20/Makefile | 1 + arch/arm/mach-tegra/tegra20/pllx.c | 59 ++++++++++++++++ arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra30/Makefile | 3 +- arch/arm/mach-tegra/tegra30/pllx.c | 34 ++++++++++ 13 files changed, 224 insertions(+), 132 deletions(-) create mode 100644 arch/arm/mach-tegra/pllx.h create mode 100644 arch/arm/mach-tegra/tegra114/pllx.c create mode 100644 arch/arm/mach-tegra/tegra124/pllx.c create mode 100644 arch/arm/mach-tegra/tegra20/pllx.c create mode 100644 arch/arm/mach-tegra/tegra210/pllx.c create mode 100644 arch/arm/mach-tegra/tegra30/pllx.c
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index f7285eb0de8c..e3c27845174a 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -11,122 +11,10 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "cpu.h" +#include "pllx.h" #include "pmc.h" #include "scu.h"
-/* - * Timing tables for each SOC for all four oscillator options. - */ -struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* - * T20: 1 GHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ - { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ - { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T25: 1.2 GHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ - { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ - { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T30: 600 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T114: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 23:20 4 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - - /* - * T124: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 23:20 4 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - - /* - * T210: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 24:20 5 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ - { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ - { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ - }, -}; - static inline void pllx_set_iddq(void) { #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) @@ -206,22 +94,16 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_sku; enum clock_osc_freq osc; - struct clk_pll_table *sel; + const struct clk_pll_table *sel; debug("%s entry\n", __func__);
- /* get SKU info */ - /* get chip SKU, combo of the above info */ - chip_sku = tegra_get_chip_sku(); - debug("%s: Chip SKU = %d\n", __func__, chip_sku); - /* get osc freq */ osc = clock_get_osc_freq(); debug("%s: osc = %d\n", __func__, osc);
/* set pllx */ - sel = &tegra_pll_x_table[chip_sku][osc]; + sel = tegra_get_pllx_table(); pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); }
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 9e5bf39ebfd7..e17ccefb663b 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -49,13 +49,6 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-struct clk_pll_table { - u16 n; - u16 m; - u8 p; - u8 cpcon; -}; - void clock_enable_coresight(int enable); void enable_cpu_clock(int enable); void halt_avp(void) __attribute__ ((noreturn)); diff --git a/arch/arm/mach-tegra/pllx.h b/arch/arm/mach-tegra/pllx.h new file mode 100644 index 000000000000..5a68b65b89d5 --- /dev/null +++ b/arch/arm/mach-tegra/pllx.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_PLLX_H +#define _TEGRA_PLLX_H + +struct clk_pll_table { + u16 n; + u16 m; + u8 p; + u8 cpcon; +}; + +const struct clk_pll_table *tegra_get_pllx_table(void); + +#endif diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index ea7f7b717a51..fd56b6a02f6e 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. # # SPDX-License-Identifier: GPL-2.0 # @@ -7,3 +7,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra114/pllx.c b/arch/arm/mach-tegra/tegra114/pllx.c new file mode 100644 index 000000000000..4c4e8f74f973 --- /dev/null +++ b/arch/arm/mach-tegra/tegra114/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra114_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra114_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index c00de6151e2d..e9554ccc966a 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2013-2014 +# (C) Copyright 2013-2016 # NVIDIA Corporation <www.nvidia.com> # # SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,7 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pllx.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra124/pllx.c b/arch/arm/mach-tegra/tegra124/pllx.c new file mode 100644 index 000000000000..c19f1df6014b --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra124_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T124: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra124_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 3cf1e7f113ce..0c2b5d51c73f 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -13,6 +13,7 @@ endif CFLAGS_warmboot_avp.o += -march=armv4t
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o obj-$(CONFIG_TEGRA20_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/pllx.c b/arch/arm/mach-tegra/tegra20/pllx.c new file mode 100644 index 000000000000..f094f06d7fed --- /dev/null +++ b/arch/arm/mach-tegra/tegra20/pllx.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra20_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +static const struct clk_pll_table tegra25_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + int chip_sku; + + chip_sku = tegra_get_chip_sku(); + if (chip_sku == TEGRA_SOC_T25) + return tegra25_pll_x_table; + else + return tegra20_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index b6012fc7baac..dfc0a9b8e702 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2013-2015 +# (C) Copyright 2013-2016 # NVIDIA Corporation <www.nvidia.com> # # SPDX-License-Identifier: GPL-2.0+ @@ -8,5 +8,6 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pllx.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/pllx.c b/arch/arm/mach-tegra/tegra210/pllx.c new file mode 100644 index 000000000000..9c6f0e0013da --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra210_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T210: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 24:20 5 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ + { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ + { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra210_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index d3d3b6e7c4fd..fd56b6a02f6e 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. # # SPDX-License-Identifier: GPL-2.0 # @@ -7,3 +7,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra30/pllx.c b/arch/arm/mach-tegra/tegra30/pllx.c new file mode 100644 index 000000000000..7c4f0ab67f1c --- /dev/null +++ b/arch/arm/mach-tegra/tegra30/pllx.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra30_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T30: 600 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra30_pll_x_table; +}
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Rather than building a large table of all possible PLLX configurations into U-Boot and having it select the right one at run-time, push the configuration into SoC-specific files, and have the linker pick up the correct one.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/cpu.c | 124 +--------------------------------- arch/arm/mach-tegra/cpu.h | 7 -- arch/arm/mach-tegra/pllx.h | 20 ++++++ arch/arm/mach-tegra/tegra114/Makefile | 3 +- arch/arm/mach-tegra/tegra114/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra124/Makefile | 3 +- arch/arm/mach-tegra/tegra124/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra20/Makefile | 1 + arch/arm/mach-tegra/tegra20/pllx.c | 59 ++++++++++++++++ arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra30/Makefile | 3 +- arch/arm/mach-tegra/tegra30/pllx.c | 34 ++++++++++ 13 files changed, 224 insertions(+), 132 deletions(-) create mode 100644 arch/arm/mach-tegra/pllx.h create mode 100644 arch/arm/mach-tegra/tegra114/pllx.c create mode 100644 arch/arm/mach-tegra/tegra124/pllx.c create mode 100644 arch/arm/mach-tegra/tegra20/pllx.c create mode 100644 arch/arm/mach-tegra/tegra210/pllx.c create mode 100644 arch/arm/mach-tegra/tegra30/pllx.c
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
This is now only used by some Tegra20-specific code, and only to select between T20/T25 code paths. Introduce a simpler function for that case, and isolate it to the tegra20/ directory.
If we need SoC differentiation in the future, we should isolate the SKU- specific logic to the SoC-specific directories, and provide a higher level interface that the SoC-agnostic code can use; similar to pllx.h in the previous commit.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/tegra.h | 38 ---------------------------- arch/arm/mach-tegra/ap.c | 40 ----------------------------- arch/arm/mach-tegra/cpu.h | 6 ----- arch/arm/mach-tegra/tegra20/Makefile | 1 + arch/arm/mach-tegra/tegra20/emc.c | 15 ++++------- arch/arm/mach-tegra/{ => tegra20}/fuse.h | 4 +-- arch/arm/mach-tegra/tegra20/pllx.c | 7 ++---- arch/arm/mach-tegra/tegra20/pmu.c | 16 ++++-------- arch/arm/mach-tegra/tegra20/sku.c | 43 ++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra20/sku.h | 12 +++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 11 files changed, 71 insertions(+), 113 deletions(-) rename arch/arm/mach-tegra/{ => tegra20}/fuse.h (91%) create mode 100644 arch/arm/mach-tegra/tegra20/sku.c create mode 100644 arch/arm/mach-tegra/tegra20/sku.h
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 0de6aedf6b2a..71c9374c7ae0 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -36,7 +36,6 @@ #define PG_UP_TAG_0 0x0 #define PG_UP_TAG_AVP 0xAAAAAAAA
-#ifndef __ASSEMBLY__ /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define NV_WB_RUN_ADDRESS 0x40020000
@@ -45,43 +44,6 @@ #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-/* These are the available SKUs (product types) for Tegra */ -enum { - SKU_ID_T20_7 = 0x7, - SKU_ID_T20 = 0x8, - SKU_ID_T25SE = 0x14, - SKU_ID_AP25 = 0x17, - SKU_ID_T25 = 0x18, - SKU_ID_AP25E = 0x1b, - SKU_ID_T25E = 0x1c, - SKU_ID_T33 = 0x80, - SKU_ID_T30 = 0x81, /* Cardhu value */ - SKU_ID_TM30MQS_P_A3 = 0xb1, - SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ - SKU_ID_T114_1 = 0x01, - SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ - SKU_ID_T210_ENG = 0x00, /* unfused value TBD */ -}; - -/* - * These are used to distinguish SOC types for setting up clocks. Mostly - * we can tell the clocking required by looking at the SOC sku_id, but - * for T30 it is a user option as to whether to run PLLP in fast or slow - * mode, so we have two options there. - */ -enum { - TEGRA_SOC_T20, - TEGRA_SOC_T25, - TEGRA_SOC_T30, - TEGRA_SOC_T114, - TEGRA_SOC_T124, - TEGRA_SOC_T210, - - TEGRA_SOC_CNT, - TEGRA_SOC_UNKNOWN = -1, -}; -#endif - #define PRM_RSTCTRL NV_PA_PMC_BASE
#endif /* TEGRA_H */ diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index f354f7d87b14..3406e0efe4cb 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -14,49 +14,9 @@ #include <asm/arch-tegra/tegra.h> #include <soc/mc.h> #include "cpu.h" -#include "fuse.h" #include "pmc.h" #include "scu.h"
-int tegra_get_chip_sku(void) -{ -#ifdef CONFIG_TEGRA20 - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint sku_id; - - sku_id = readl(&fuse->sku_info) & 0xff; - debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); - - switch (sku_id) { - case SKU_ID_T20_7: - case SKU_ID_T20: - return TEGRA_SOC_T20; - case SKU_ID_T25SE: - case SKU_ID_AP25: - case SKU_ID_T25: - case SKU_ID_AP25E: - case SKU_ID_T25E: - return TEGRA_SOC_T25; - default: - /* unknown chip/sku id */ - printf("ERROR: UNKNOWN SKU ID 0x%02X\n", sku_id); - return TEGRA_SOC_UNKNOWN; - } -#endif -#ifdef CONFIG_TEGRA30 - return TEGRA_SOC_T30; -#endif -#ifdef CONFIG_TEGRA114 - return TEGRA_SOC_T114; -#endif -#ifdef CONFIG_TEGRA124 - return TEGRA_SOC_T124; -#endif -#ifdef CONFIG_TEGRA210 - return TEGRA_SOC_T210; -#endif -} - #ifndef CONFIG_ARM64 static void enable_scu(void) { diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index e17ccefb663b..4cb0b43b3723 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -56,12 +56,6 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); -/** - * Works out the SOC/SKU type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); /* Set core and CPU voltages to nominal levels */ int pmu_set_nominal(void); diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 0c2b5d51c73f..105f6ffa820c 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -14,6 +14,7 @@ CFLAGS_warmboot_avp.o += -march=armv4t
obj-y += clock.o funcmux.o pinmux.o obj-y += pllx.o +obj-y += sku.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o obj-$(CONFIG_TEGRA20_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index 242defde00a6..fa694d1fda84 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -11,9 +11,9 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include "../apb_misc.h" -#include "../cpu.h" #include "../emc.h" #include "emc_priv.h" +#include "sku.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -290,14 +290,9 @@ int board_emc_init(void) { unsigned rate;
- switch (tegra_get_chip_sku()) { - default: - case TEGRA_SOC_T20: - rate = EMC_SDRAM_RATE_T20; - break; - case TEGRA_SOC_T25: - rate = EMC_SDRAM_RATE_T25; - break; - } + if (soc_is_tegra25()) + rate = EMC_SDRAM_RATE_T25; + else + rate = EMC_SDRAM_RATE_T20; return tegra_set_emc(gd->fdt_blob, rate); } diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/tegra20/fuse.h similarity index 91% rename from arch/arm/mach-tegra/fuse.h rename to arch/arm/mach-tegra/tegra20/fuse.h index 448cf0869cde..f0bbfa275bf8 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/tegra20/fuse.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_FUSE_H -#define _TEGRA_FUSE_H +#ifndef _TEGRA20_FUSE_H +#define _TEGRA20_FUSE_H
/* FUSE registers */ struct fuse_regs { diff --git a/arch/arm/mach-tegra/tegra20/pllx.c b/arch/arm/mach-tegra/tegra20/pllx.c index f094f06d7fed..1e0127313c4f 100644 --- a/arch/arm/mach-tegra/tegra20/pllx.c +++ b/arch/arm/mach-tegra/tegra20/pllx.c @@ -6,8 +6,8 @@
#include <common.h> #include <asm/arch-tegra/clock.h> -#include "../cpu.h" #include "../pllx.h" +#include "sku.h"
static const struct clk_pll_table tegra20_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { /* @@ -49,10 +49,7 @@ static const struct clk_pll_table tegra25_pll_x_table[CLOCK_OSC_FREQ_COUNT] = {
const struct clk_pll_table *tegra_get_pllx_table(void) { - int chip_sku; - - chip_sku = tegra_get_chip_sku(); - if (chip_sku == TEGRA_SOC_T25) + if (soc_is_tegra25()) return tegra25_pll_x_table; else return tegra20_pll_x_table; diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 2ebcfaf2695e..ac24c6b3ac1d 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -11,7 +11,7 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <mach/tegra_i2c.h> -#include "../cpu.h" +#include "sku.h"
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */ @@ -32,18 +32,12 @@ int pmu_set_nominal(void) int ret;
/* by default, the table has been filled with T25 settings */ - switch (tegra_get_chip_sku()) { - case TEGRA_SOC_T20: - core = VDD_CORE_NOMINAL_T20; - cpu = VDD_CPU_NOMINAL_T20; - break; - case TEGRA_SOC_T25: + if (soc_is_tegra25()) { core = VDD_CORE_NOMINAL_T25; cpu = VDD_CPU_NOMINAL_T25; - break; - default: - debug("%s: Unknown SKU id\n", __func__); - return -1; + } else { + core = VDD_CORE_NOMINAL_T20; + cpu = VDD_CPU_NOMINAL_T20; }
ret = tegra_i2c_get_dvc_bus(&bus); diff --git a/arch/arm/mach-tegra/tegra20/sku.c b/arch/arm/mach-tegra/tegra20/sku.c new file mode 100644 index 000000000000..56c9e97e2454 --- /dev/null +++ b/arch/arm/mach-tegra/tegra20/sku.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include "fuse.h" + +/* These are the available SKUs (product types) for Tegra20 */ +#define SKU_ID_T20_7 0x7 +#define SKU_ID_T20 0x8 +#define SKU_ID_T25SE 0x14 +#define SKU_ID_AP25 0x17 +#define SKU_ID_T25 0x18 +#define SKU_ID_AP25E 0x1b +#define SKU_ID_T25E 0x1c + +bool soc_is_tegra25(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + uint sku_id; + + sku_id = readl(&fuse->sku_info) & 0xff; + debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + + switch (sku_id) { + case SKU_ID_T20_7: + case SKU_ID_T20: + return false; + case SKU_ID_T25SE: + case SKU_ID_AP25: + case SKU_ID_T25: + case SKU_ID_AP25E: + case SKU_ID_T25E: + return true; + default: + /* unknown chip/sku id */ + printf("ERROR: UNKNOWN SKU ID 0x%02X\n", sku_id); + return false; + } +} diff --git a/arch/arm/mach-tegra/tegra20/sku.h b/arch/arm/mach-tegra/tegra20/sku.h new file mode 100644 index 000000000000..33a2ec863958 --- /dev/null +++ b/arch/arm/mach-tegra/tegra20/sku.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA20_SKU_H +#define _TEGRA20_SKU_H + +bool soc_is_tegra25(void); + +#endif diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index d5f7e96eb07e..dc9727ab3f5f 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -14,10 +14,10 @@ #include <asm/arch-tegra/clk_rst.h> #include "../apb_misc.h" #include "../emc.h" -#include "../fuse.h" #include "../pmc.h" #include "crypto.h" #include "emc_priv.h" +#include "fuse.h" #include "gp_padctrl.h" #include "sdram_param.h" #include "warmboot.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This is now only used by some Tegra20-specific code, and only to select between T20/T25 code paths. Introduce a simpler function for that case, and isolate it to the tegra20/ directory.
If we need SoC differentiation in the future, we should isolate the SKU- specific logic to the SoC-specific directories, and provide a higher level interface that the SoC-agnostic code can use; similar to pllx.h in the previous commit.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/tegra.h | 38 ---------------------------- arch/arm/mach-tegra/ap.c | 40 ----------------------------- arch/arm/mach-tegra/cpu.h | 6 ----- arch/arm/mach-tegra/tegra20/Makefile | 1 + arch/arm/mach-tegra/tegra20/emc.c | 15 ++++------- arch/arm/mach-tegra/{ => tegra20}/fuse.h | 4 +-- arch/arm/mach-tegra/tegra20/pllx.c | 7 ++---- arch/arm/mach-tegra/tegra20/pmu.c | 16 ++++-------- arch/arm/mach-tegra/tegra20/sku.c | 43 ++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra20/sku.h | 12 +++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- 11 files changed, 71 insertions(+), 113 deletions(-) rename arch/arm/mach-tegra/{ => tegra20}/fuse.h (91%) create mode 100644 arch/arm/mach-tegra/tegra20/sku.c create mode 100644 arch/arm/mach-tegra/tegra20/sku.h
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/cpu.c | 1 - .../pinmux.h => mach-tegra/include/mach/pinmux_common.h} | 11 +++++------ arch/arm/mach-tegra/pinmux-common.c | 4 ++-- arch/arm/mach-tegra/spl.c | 1 - arch/arm/mach-tegra/tegra114/cpu.c | 2 +- arch/arm/mach-tegra/tegra114/funcmux.c | 4 ++-- .../tegra114/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra114/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/funcmux.c | 4 ++-- .../tegra124/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra124/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra20/funcmux.c | 3 ++- .../arch-tegra20 => mach-tegra/tegra20/include/mach}/pinmux.h | 10 +++++----- arch/arm/mach-tegra/tegra20/pinmux.c | 3 ++- arch/arm/mach-tegra/tegra20/warmboot.c | 1 - arch/arm/mach-tegra/tegra20/warmboot_avp.c | 1 - arch/arm/mach-tegra/tegra210/funcmux.c | 3 +-- .../tegra210/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra210/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra30/funcmux.c | 4 ++-- .../arch-tegra30 => mach-tegra/tegra30/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra30/pinmux.c | 4 ++-- board/avionic-design/common/tamonten-ng.c | 2 +- board/avionic-design/common/tamonten.c | 2 +- board/compal/paz00/paz00.c | 4 ++-- board/compulab/trimslice/trimslice.c | 4 ++-- board/nvidia/cardhu/cardhu.c | 2 +- board/nvidia/dalmore/dalmore.c | 2 +- board/nvidia/e2220-1170/e2220-1170.c | 2 +- board/nvidia/harmony/harmony.c | 4 ++-- board/nvidia/jetson-tk1/jetson-tk1.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 2 +- board/nvidia/p2371-0000/p2371-0000.c | 2 +- board/nvidia/p2371-2180/p2371-2180.c | 2 +- board/nvidia/p2571/p2571.c | 2 +- board/nvidia/seaboard/seaboard.c | 2 +- board/nvidia/venice2/venice2.c | 2 +- board/nvidia/whistler/whistler.c | 4 ++-- board/toradex/apalis_t30/apalis_t30.c | 2 +- board/toradex/colibri_t20/colibri_t20.c | 2 +- board/toradex/colibri_t30/colibri_t30.c | 2 +- drivers/i2c/tegra_i2c.c | 1 - drivers/spi/tegra20_sflash.c | 4 ++-- drivers/video/tegra.c | 2 +- 46 files changed, 75 insertions(+), 81 deletions(-) rename arch/arm/{include/asm/arch-tegra/pinmux.h => mach-tegra/include/mach/pinmux_common.h} (97%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/pinmux.h (96%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/pinmux.h (98%)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index c3e6fbf2a5a4..2667efe5aa71 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index e3c27845174a..eb9222b2f23d 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "cpu.h" diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux_common.h similarity index 97% rename from arch/arm/include/asm/arch-tegra/pinmux.h rename to arch/arm/mach-tegra/include/mach/pinmux_common.h index 65eb37334e95..6e98ba29eef7 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux_common.h @@ -1,17 +1,16 @@ /* - * (C) Copyright 2010-2014 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_PINMUX_H_ -#define _TEGRA_PINMUX_H_ +#ifndef _TEGRA_PINMUX_COMMON_H +#define _TEGRA_PINMUX_COMMON_H
+#include <config.h> #include <linux/types.h>
-#include <asm/arch/tegra.h> - /* The pullup/pulldown state of a pin group */ enum pmux_pull { PMUX_PULL_NORMAL = 0, @@ -247,4 +246,4 @@ struct pmux_mipipadctrlgrp_desc { extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; #endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
-#endif /* _TEGRA_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 5862c4ac3dc6..faa406e077a4 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011 The Chromium OS Authors. * * SPDX-License-Identifier: GPL-2.0+ @@ -7,7 +7,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
/* return 1 if a pingrp is in range */ #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index e793700b243e..49af4119e927 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -11,7 +11,6 @@
#include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/spl.h> #include <mach/board.h> diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index c06e632bb36a..423ace4a2ebd 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -8,9 +8,9 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> +#include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c index ca9d970abc81..e32b75c8a0b6 100644 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ b/arch/arm/mach-tegra/tegra114/funcmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -9,7 +9,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
int funcmux_select(enum periph_id id, int config) { diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h similarity index 98% rename from arch/arm/include/asm/arch-tegra114/pinmux.h rename to arch/arm/mach-tegra/tegra114/include/mach/pinmux.h index c96fd096695b..af2e4be55fdf 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA114_PINMUX_H_ -#define _TEGRA114_PINMUX_H_ +#ifndef _TEGRA114_PINMUX_H +#define _TEGRA114_PINMUX_H
enum pmux_pingrp { PMUX_PINGRP_ULPI_DATA0_PO1, @@ -330,6 +330,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_OD #define TEGRA_PMX_PINS_HAVE_IO_RESET #define TEGRA_PMX_PINS_HAVE_RCV_SEL -#include <asm/arch-tegra/pinmux.h> +#include <mach/pinmux_common.h>
-#endif /* _TEGRA114_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c index 3e5acb93ce28..e4d768637878 100644 --- a/arch/arm/mach-tegra/tegra114/pinmux.c +++ b/arch/arm/mach-tegra/tegra114/pinmux.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \ { \ diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 527c4a186e68..c01d36c11c4b 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -8,9 +8,9 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> +#include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" diff --git a/arch/arm/mach-tegra/tegra124/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c index cced787e6b6d..cdbe73f319a6 100644 --- a/arch/arm/mach-tegra/tegra124/funcmux.c +++ b/arch/arm/mach-tegra/tegra124/funcmux.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,7 +10,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
int funcmux_select(enum periph_id id, int config) { diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h similarity index 98% rename from arch/arm/include/asm/arch-tegra124/pinmux.h rename to arch/arm/mach-tegra/tegra124/include/mach/pinmux.h index 31b921f4ae71..4b4424460e5e 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA124_PINMUX_H_ -#define _TEGRA124_PINMUX_H_ +#ifndef _TEGRA124_PINMUX_H +#define _TEGRA124_PINMUX_H
enum pmux_pingrp { PMUX_PINGRP_ULPI_DATA0_PO1, @@ -361,6 +361,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_OD #define TEGRA_PMX_PINS_HAVE_IO_RESET #define TEGRA_PMX_PINS_HAVE_RCV_SEL -#include <asm/arch-tegra/pinmux.h> +#include <mach/pinmux_common.h>
-#endif /* _TEGRA124_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index 4629b4676c4a..d5b4cdb9a686 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \ { \ diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 44a85c5f1dc9..348507aee2d6 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
/* * The PINMUX macro is used to set up pinmux tables. diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h similarity index 96% rename from arch/arm/include/asm/arch-tegra20/pinmux.h rename to arch/arm/mach-tegra/tegra20/include/mach/pinmux.h index bf35d50ba316..f05e993b34cc 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h @@ -1,12 +1,12 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA20_PINMUX_H_ -#define _TEGRA20_PINMUX_H_ +#ifndef _TEGRA20_PINMUX_H +#define _TEGRA20_PINMUX_H
/* * Pin groups which we adjust. There are three basic attributes of each pin @@ -234,6 +234,6 @@ enum pmux_func { };
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 -#include <asm/arch-tegra/pinmux.h> +#include <mach/pinmux_common.h>
-#endif /* _TEGRA20_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra20/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c index e484f991bf81..bfcef743a998 100644 --- a/arch/arm/mach-tegra/tegra20/pinmux.c +++ b/arch/arm/mach-tegra/tegra20/pinmux.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
/* * This defines the order of the pin mux control bits in the registers. For diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index dc9727ab3f5f..26db8a1477a5 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -9,7 +9,6 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../apb_misc.h" diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index ace6e8d4f59b..07aa542c11b0 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <soc/flow.h> diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c index 618d2282e6aa..bd7c2521caf3 100644 --- a/arch/arm/mach-tegra/tegra210/funcmux.c +++ b/arch/arm/mach-tegra/tegra210/funcmux.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,7 +10,6 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config) { diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/mach-tegra/tegra210/include/mach/pinmux.h similarity index 98% rename from arch/arm/include/asm/arch-tegra210/pinmux.h rename to arch/arm/mach-tegra/tegra210/include/mach/pinmux.h index 4772d96101c9..59144bfa388b 100644 --- a/arch/arm/include/asm/arch-tegra210/pinmux.h +++ b/arch/arm/mach-tegra/tegra210/include/mach/pinmux.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA210_PINMUX_H_ -#define _TEGRA210_PINMUX_H_ +#ifndef _TEGRA210_PINMUX_H +#define _TEGRA210_PINMUX_H
enum pmux_pingrp { PMUX_PINGRP_SDMMC1_CLK_PM0, @@ -417,6 +417,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_LOCK #define TEGRA_PMX_PINS_HAVE_OD #define TEGRA_PMX_PINS_HAVE_E_IO_HV -#include <asm/arch-tegra/pinmux.h> +#include <mach/pinmux_common.h>
-#endif /* _TEGRA210_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c index a29c76b1fae6..abd4600985d0 100644 --- a/arch/arm/mach-tegra/tegra210/pinmux.c +++ b/arch/arm/mach-tegra/tegra210/pinmux.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \ { \ diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c index 8c6833904378..c627574d61de 100644 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ b/arch/arm/mach-tegra/tegra30/funcmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -9,7 +9,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
int funcmux_select(enum periph_id id, int config) { diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h similarity index 98% rename from arch/arm/include/asm/arch-tegra30/pinmux.h rename to arch/arm/mach-tegra/tegra30/include/mach/pinmux.h index 6f4e2899b963..7717370f00eb 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA30_PINMUX_H_ -#define _TEGRA30_PINMUX_H_ +#ifndef _TEGRA30_PINMUX_H +#define _TEGRA30_PINMUX_H
enum pmux_pingrp { PMUX_PINGRP_ULPI_DATA0_PO1, @@ -406,6 +406,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_LOCK #define TEGRA_PMX_PINS_HAVE_OD #define TEGRA_PMX_PINS_HAVE_IO_RESET -#include <asm/arch-tegra/pinmux.h> +#include <mach/pinmux_common.h>
-#endif /* _TEGRA30_PINMUX_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra30/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c index 7eb05743b4bc..fd1f9464a014 100644 --- a/arch/arm/mach-tegra/tegra30/pinmux.c +++ b/arch/arm/mach-tegra/tegra30/pinmux.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \ { \ diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 6bff3285c73c..9955af3f6bbb 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -11,7 +11,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include "pinmux-config-tamonten-ng.h"
#define PMU_I2C_ADDRESS 0x2D diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index c369d13e7f50..7d3a5e72bc19 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -14,10 +14,10 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/board.h> +#include <mach/pinmux.h>
#ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 43931b0653a3..8ae07d396474 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -10,8 +10,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch/pinmux.h> #include <asm/gpio.h> +#include <mach/pinmux.h>
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 723293fef35a..a1f4f2213dc8 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,8 +10,8 @@ #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/gpio.h> +#include <mach/pinmux.h> #include <i2c.h>
void pin_mux_usb(void) diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index edfe960428ac..b78d2bf46d24 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -10,7 +10,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include "pinmux-config-cardhu.h"
#define PMU_I2C_ADDRESS 0x2D diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 09adc74e0ede..ad9214d1e37a 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -6,7 +6,7 @@
#include <common.h> #include <dm.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include "pinmux-config-dalmore.h" #include <i2c.h>
diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index c2b5e5e09d21..5d2f3589b678 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -9,7 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-e2220-1170.h" diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index c892a25751f9..4f3df8fe9655 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,9 +10,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> +#include <mach/pinmux.h>
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 422a18a4e530..bac2d0c36101 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -9,7 +9,7 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "pinmux-config-jetson-tk1.h"
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index db2874ed93ac..fd9669ba0bb5 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -12,9 +12,9 @@ #include <power/pmic.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "pinmux-config-nyan-big.h"
diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index a23dfc8afaef..a63f95f1f4f1 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -9,7 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-0000.h" diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 3989ab8bde32..c9884bd70335 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -9,7 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h" diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 7faec788f3cf..58e5c56c5b16 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -9,7 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "max77620_init.h" #include "pinmux-config-p2571.h" diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 913679e888d3..cc017554548a 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -12,8 +12,8 @@ #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <mach/board.h> +#include <mach/pinmux.h>
/* TODO: Remove this code when the SPI switch is working */ #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index 5791e0d73522..9b02afd16040 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -8,7 +8,7 @@ #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "pinmux-config-venice2.h"
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 3476f1159fea..b2c71a361afd 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -11,8 +11,8 @@ #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/gpio.h> +#include <mach/pinmux.h> #include <i2c.h>
#ifdef CONFIG_TEGRA_MMC diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index e2a40db1afdd..06fddec6e0fe 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -7,10 +7,10 @@ */
#include <common.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> +#include <mach/pinmux.h> #include <dm.h> #include <i2c.h>
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 2505104b78fe..87dfcd5f3f19 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -12,9 +12,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> #include <mach/board.h> +#include <mach/pinmux.h>
#define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index e0e7deef579a..1be24b86fdc4 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -11,8 +11,8 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/tegra.h> +#include <mach/pinmux.h> #include "pinmux-config-colibri_t30.h"
int arch_misc_init(void) diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index f1b8877be228..4eb68b6e11b5 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_i2c.h> #include "tegra_i2c_priv.h" diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 6888a96139a7..4e51b252e6a2 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013 NVIDIA Corporation + * Copyright (c) 2010-2016 NVIDIA Corporation * With help from the mpc8xxx SPI driver * With more help from omap3_spi SPI driver * @@ -12,8 +12,8 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> +#include <mach/pinmux.h> #include <spi.h> #include <fdtdec.h> #include "tegra_spi.h" diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 45a2876d4030..5b778777619f 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> +#include <mach/pinmux.h> #include "tegra_dc.h"
DECLARE_GLOBAL_DATA_PTR;
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Machine-specific headers should be in this location. Eventually, we'll move all headers from arch/arm/include to arch/arm/mach-tegra/include, or find a way to delete them.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/cpu.c | 1 - .../pinmux.h => mach-tegra/include/mach/pinmux_common.h} | 11 +++++------ arch/arm/mach-tegra/pinmux-common.c | 4 ++-- arch/arm/mach-tegra/spl.c | 1 - arch/arm/mach-tegra/tegra114/cpu.c | 2 +- arch/arm/mach-tegra/tegra114/funcmux.c | 4 ++-- .../tegra114/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra114/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/funcmux.c | 4 ++-- .../tegra124/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra124/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra20/funcmux.c | 3 ++- .../arch-tegra20 => mach-tegra/tegra20/include/mach}/pinmux.h | 10 +++++----- arch/arm/mach-tegra/tegra20/pinmux.c | 3 ++- arch/arm/mach-tegra/tegra20/warmboot.c | 1 - arch/arm/mach-tegra/tegra20/warmboot_avp.c | 1 - arch/arm/mach-tegra/tegra210/funcmux.c | 3 +-- .../tegra210/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra210/pinmux.c | 4 ++-- arch/arm/mach-tegra/tegra30/funcmux.c | 4 ++-- .../arch-tegra30 => mach-tegra/tegra30/include/mach}/pinmux.h | 8 ++++---- arch/arm/mach-tegra/tegra30/pinmux.c | 4 ++-- board/avionic-design/common/tamonten-ng.c | 2 +- board/avionic-design/common/tamonten.c | 2 +- board/compal/paz00/paz00.c | 4 ++-- board/compulab/trimslice/trimslice.c | 4 ++-- board/nvidia/cardhu/cardhu.c | 2 +- board/nvidia/dalmore/dalmore.c | 2 +- board/nvidia/e2220-1170/e2220-1170.c | 2 +- board/nvidia/harmony/harmony.c | 4 ++-- board/nvidia/jetson-tk1/jetson-tk1.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 2 +- board/nvidia/p2371-0000/p2371-0000.c | 2 +- board/nvidia/p2371-2180/p2371-2180.c | 2 +- board/nvidia/p2571/p2571.c | 2 +- board/nvidia/seaboard/seaboard.c | 2 +- board/nvidia/venice2/venice2.c | 2 +- board/nvidia/whistler/whistler.c | 4 ++-- board/toradex/apalis_t30/apalis_t30.c | 2 +- board/toradex/colibri_t20/colibri_t20.c | 2 +- board/toradex/colibri_t30/colibri_t30.c | 2 +- drivers/i2c/tegra_i2c.c | 1 - drivers/spi/tegra20_sflash.c | 4 ++-- drivers/video/tegra.c | 2 +- 46 files changed, 75 insertions(+), 81 deletions(-) rename arch/arm/{include/asm/arch-tegra/pinmux.h => mach-tegra/include/mach/pinmux_common.h} (97%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/pinmux.h (96%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/pinmux.h (98%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/pinmux.h (98%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
The existing funcmux APIs have the disadvantage that clients call a single monolithic/IOCTL-style function which performs different operations based on its parameter. All branches of that function are always compiled into the binary even when they're not used.
Another disadvantage is that funcmux is pinmux functionality, but implemented outside the Tegra pinmux driver.
This patch creates a separate function per operation, and implements them as part of the pinmux driver. Later patches will convert callers to these functions and eventually remove the funcmux files.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra114/include/mach/pinmux.h | 2 + arch/arm/mach-tegra/tegra114/pinmux.c | 18 ++ arch/arm/mach-tegra/tegra124/include/mach/pinmux.h | 3 + arch/arm/mach-tegra/tegra124/pinmux.c | 30 +++ arch/arm/mach-tegra/tegra20/include/mach/pinmux.h | 22 +++ arch/arm/mach-tegra/tegra20/pinmux.c | 208 +++++++++++++++++++++ arch/arm/mach-tegra/tegra30/include/mach/pinmux.h | 2 + arch/arm/mach-tegra/tegra30/pinmux.c | 12 ++ 8 files changed, 297 insertions(+)
diff --git a/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h b/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h index af2e4be55fdf..8cb07ee751c5 100644 --- a/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/tegra114/include/mach/pinmux.h @@ -332,4 +332,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_RCV_SEL #include <mach/pinmux_common.h>
+void tegra114_pinmux_uartd_gmi(void); + #endif diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c index e4d768637878..7fd383d300ce 100644 --- a/arch/arm/mach-tegra/tegra114/pinmux.c +++ b/arch/arm/mach-tegra/tegra114/pinmux.c @@ -291,3 +291,21 @@ static const struct pmux_pingrp_desc tegra114_pingroups[] = { PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups; + +void tegra114_pinmux_uartd_gmi(void) +{ + pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7, PMUX_FUNC_UARTD); + + pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7); +} diff --git a/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h b/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h index 4b4424460e5e..307d3f75b728 100644 --- a/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/tegra124/include/mach/pinmux.h @@ -363,4 +363,7 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_RCV_SEL #include <mach/pinmux_common.h>
+void tegra124_pinmux_uarta_kbc(void); +void tegra124_pinmux_uartd_gpio(void); + #endif diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index d5b4cdb9a686..b27f89e2f5a1 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -321,3 +321,33 @@ static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), }; const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; + +void tegra124_pinmux_uarta_kbc(void) +{ + pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, PMUX_FUNC_UARTA); + + pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); + + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); +} + +void tegra124_pinmux_uartd_gpio(void) +{ + pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); + + pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PMUX_PINGRP_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_PB0); + pinmux_tristate_disable(PMUX_PINGRP_PB1); + pinmux_tristate_disable(PMUX_PINGRP_PK7); +} diff --git a/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h b/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h index f05e993b34cc..642f9d59d588 100644 --- a/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/tegra20/include/mach/pinmux.h @@ -236,4 +236,26 @@ enum pmux_func { #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #include <mach/pinmux_common.h>
+void tegra20_pinmux_disp1_ld0_17(void); +void tegra20_pinmux_dvc_i2c_i2cp(void); +void tegra20_pinmux_i2c1_rm(void); +void tegra20_pinmux_i2c3_dtf(void); +void tegra20_pinmux_kbc_kbca_f(void); +void tegra20_pinmux_ndflash_atc(void); +void tegra20_pinmux_ndflash_kbc_8bit(void); +void tegra20_pinmux_sdmmc1_sdio1_4bit(void); +void tegra20_pinmux_sdmmc2_dta_dtd_8bit(void); +void tegra20_pinmux_sdmmc3_sdb_4bit(void); +void tegra20_pinmux_sdmmc3_sdb_slxa_8bit(void); +void tegra20_pinmux_sdmmc4_atb_gma_4bit(void); +void tegra20_pinmux_sdmmc4_atb_gma_gme_8bit(void); +void tegra20_pinmux_sdmmc4_atc_atd_8bit(void); +void tegra20_pinmux_spi1_gmc_gmd(void); +void tegra20_pinmux_uarta_gpu(void); +void tegra20_pinmux_uarta_irrx_irtx(void); +void tegra20_pinmux_uarta_sdio1(void); +void tegra20_pinmux_uarta_uaa_uab(void); +void tegra20_pinmux_uartd_gmc(void); +void tegra20_pinmux_usb2_ulpi(void); + #endif diff --git a/arch/arm/mach-tegra/tegra20/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c index bfcef743a998..363b72f37880 100644 --- a/arch/arm/mach-tegra/tegra20/pinmux.c +++ b/arch/arm/mach-tegra/tegra20/pinmux.c @@ -424,3 +424,211 @@ static const struct pmux_pingrp_desc tegra20_pingroups[] = { DRVGRP(XM2D), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups; + +#define PINMUX(grp, mux, pupd, tri) \ + {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} + +static const struct pmux_pingrp_config disp1_default[] = { + PINMUX(LDI, DISPA, NORMAL, NORMAL), + PINMUX(LHP0, DISPA, NORMAL, NORMAL), + PINMUX(LHP1, DISPA, NORMAL, NORMAL), + PINMUX(LHP2, DISPA, NORMAL, NORMAL), + PINMUX(LHS, DISPA, NORMAL, NORMAL), + PINMUX(LM0, RSVD4, NORMAL, NORMAL), + PINMUX(LPP, DISPA, NORMAL, NORMAL), + PINMUX(LPW0, DISPA, NORMAL, NORMAL), + PINMUX(LPW2, DISPA, NORMAL, NORMAL), + PINMUX(LSC0, DISPA, NORMAL, NORMAL), + PINMUX(LSPI, DISPA, NORMAL, NORMAL), + PINMUX(LVP1, DISPA, NORMAL, NORMAL), + PINMUX(LVS, DISPA, NORMAL, NORMAL), + PINMUX(SLXD, SPDIF, NORMAL, NORMAL), +}; + +void tegra20_pinmux_disp1_ld0_17(void) +{ + int i; + + for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) { + pinmux_set_func(i, PMUX_FUNC_DISPA); + pinmux_tristate_disable(i); + pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); + } + pinmux_config_pingrp_table(disp1_default, ARRAY_SIZE(disp1_default)); +} + +void tegra20_pinmux_dvc_i2c_i2cp(void) +{ + pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C); + pinmux_tristate_disable(PMUX_PINGRP_I2CP); +} + +void tegra20_pinmux_i2c1_rm(void) +{ + pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C); + pinmux_tristate_disable(PMUX_PINGRP_RM); +} + +void tegra20_pinmux_i2c3_dtf(void) +{ + pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3); + pinmux_tristate_disable(PMUX_PINGRP_DTF); +} + +void tegra20_pinmux_kbc_kbca_f(void) +{ + enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, PMUX_PINGRP_KBCB, + PMUX_PINGRP_KBCC, PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE, + PMUX_PINGRP_KBCF}; + int i; + + for (i = 0; i < ARRAY_SIZE(grp); i++) { + pinmux_tristate_disable(grp[i]); + pinmux_set_func(grp[i], PMUX_FUNC_KBC); + pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); + } +} + +void tegra20_pinmux_ndflash_atc(void) +{ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND); + pinmux_tristate_disable(PMUX_PINGRP_ATC); +} + +void tegra20_pinmux_ndflash_kbc_8bit(void) +{ + pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); + pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); + pinmux_tristate_disable(PMUX_PINGRP_KBCC); + pinmux_tristate_disable(PMUX_PINGRP_KBCD); + pinmux_tristate_disable(PMUX_PINGRP_KBCE); + pinmux_tristate_disable(PMUX_PINGRP_KBCF); +} + +void tegra20_pinmux_sdmmc1_sdio1_4bit(void) +{ + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); +} + +void tegra20_pinmux_sdmmc2_dta_dtd_8bit(void) +{ + pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2); + pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2); + pinmux_tristate_disable(PMUX_PINGRP_DTA); + pinmux_tristate_disable(PMUX_PINGRP_DTD); +} + +void tegra20_pinmux_sdmmc3_sdb_4bit(void) +{ + pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3); + pinmux_tristate_disable(PMUX_PINGRP_SDB); + pinmux_tristate_disable(PMUX_PINGRP_SDC); + pinmux_tristate_disable(PMUX_PINGRP_SDD); +} + +void tegra20_pinmux_sdmmc3_sdb_slxa_8bit(void) +{ + pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3); + pinmux_tristate_disable(PMUX_PINGRP_SLXA); + pinmux_tristate_disable(PMUX_PINGRP_SLXC); + pinmux_tristate_disable(PMUX_PINGRP_SLXD); + pinmux_tristate_disable(PMUX_PINGRP_SLXK); + tegra20_pinmux_sdmmc3_sdb_4bit(); +} + +void tegra20_pinmux_sdmmc4_atb_gma_4bit(void) +{ + pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_tristate_disable(PMUX_PINGRP_ATB); + pinmux_tristate_disable(PMUX_PINGRP_GMA); +} + +void tegra20_pinmux_sdmmc4_atb_gma_gme_8bit(void) +{ + pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); + pinmux_tristate_disable(PMUX_PINGRP_GME); + tegra20_pinmux_sdmmc4_atb_gma_4bit(); +} + +void tegra20_pinmux_sdmmc4_atc_atd_8bit(void) +{ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4); + pinmux_tristate_disable(PMUX_PINGRP_ATC); + pinmux_tristate_disable(PMUX_PINGRP_ATD); +} + +void tegra20_pinmux_spi1_gmc_gmd(void) +{ + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); + pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_tristate_disable(PMUX_PINGRP_GMC); + pinmux_tristate_disable(PMUX_PINGRP_GMD); +} + +static void tegra20_pinmux_uarta_fix_sdb_conflict(void) +{ + pinmux_tristate_enable(PMUX_PINGRP_SDB); + pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); +} + +void tegra20_pinmux_uarta_gpu(void) +{ + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_GPU); + tegra20_pinmux_uarta_fix_sdb_conflict(); +} + +void tegra20_pinmux_uarta_irrx_irtx(void) +{ + pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_IRRX); + pinmux_tristate_disable(PMUX_PINGRP_IRTX); + tegra20_pinmux_uarta_fix_sdb_conflict(); +} + +void tegra20_pinmux_uarta_sdio1(void) +{ + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); + tegra20_pinmux_uarta_fix_sdb_conflict(); +} + +void tegra20_pinmux_uarta_uaa_uab(void) +{ + pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_UAA); + pinmux_tristate_disable(PMUX_PINGRP_UAB); + tegra20_pinmux_uarta_fix_sdb_conflict(); +} + +void tegra20_pinmux_uartd_gmc(void) +{ + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD); + pinmux_tristate_disable(PMUX_PINGRP_GMC); +} + +void tegra20_pinmux_usb2_ulpi(void) +{ + pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI); + pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI); + pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI); + pinmux_tristate_disable(PMUX_PINGRP_UAA); + pinmux_tristate_disable(PMUX_PINGRP_UAB); + pinmux_tristate_disable(PMUX_PINGRP_UDA); +} diff --git a/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h b/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h index 7717370f00eb..2588a38336be 100644 --- a/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/tegra30/include/mach/pinmux.h @@ -408,4 +408,6 @@ enum pmux_func { #define TEGRA_PMX_PINS_HAVE_IO_RESET #include <mach/pinmux_common.h>
+void tegra30_pinmux_uarta_ulpi(void); + #endif diff --git a/arch/arm/mach-tegra/tegra30/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c index fd1f9464a014..2331d2bcdd52 100644 --- a/arch/arm/mach-tegra/tegra30/pinmux.c +++ b/arch/arm/mach-tegra/tegra30/pinmux.c @@ -274,3 +274,15 @@ static const struct pmux_pingrp_desc tegra30_pingroups[] = { PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups; + +void tegra30_pinmux_uarta_ulpi(void) +{ + pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); +}
Hi Stephen.
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
The existing funcmux APIs have the disadvantage that clients call a single monolithic/IOCTL-style function which performs different operations based on its parameter. All branches of that function are always compiled into the binary even when they're not used.
Another disadvantage is that funcmux is pinmux functionality, but implemented outside the Tegra pinmux driver.
This patch creates a separate function per operation, and implements them as part of the pinmux driver. Later patches will convert callers to these functions and eventually remove the funcmux files.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/tegra114/include/mach/pinmux.h | 2 + arch/arm/mach-tegra/tegra114/pinmux.c | 18 ++ arch/arm/mach-tegra/tegra124/include/mach/pinmux.h | 3 + arch/arm/mach-tegra/tegra124/pinmux.c | 30 +++ arch/arm/mach-tegra/tegra20/include/mach/pinmux.h | 22 +++ arch/arm/mach-tegra/tegra20/pinmux.c | 208 +++++++++++++++++++++ arch/arm/mach-tegra/tegra30/include/mach/pinmux.h | 2 + arch/arm/mach-tegra/tegra30/pinmux.c | 12 ++ 8 files changed, 297 insertions(+)
This should go in a pinctrl driver for each SoC.
Regards, Simon
From: Stephen Warren swarren@nvidia.com
Currently, SPL console initialization on Tegra suffers from two problems:
1) It's a monolithic function that knows about all possibilities using tables and ifdefs set by board config.h, and contained in core files that are always built into U-Boot. Some of the code can't be ported to future SoCs since the clock APIs will be different. Equally, future SoCs don't need the code since earlier boot FW will always initialized the UART.
2) It's unnecessarily invoked twice, once by SPL and once by the main U-Boot binary.
This patch adds simpler APIs to initialize the UART from SPL. This code can be omitted from non-SPL builds.
A future patch will add the code to the Makefile when board files are converted. Adding it now would cause duplicate symbols for the UART device itself which will cause the link to fail. Even if that were resolved by changing the symbol name, duplicate UART devices would be registered, which would likely cause runtime problems.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/include/mach/spl_uart.h | 20 +++++++++++++++ arch/arm/mach-tegra/spl_uart.c | 39 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-tegra/include/mach/spl_uart.h create mode 100644 arch/arm/mach-tegra/spl_uart.c
diff --git a/arch/arm/mach-tegra/include/mach/spl_uart.h b/arch/arm/mach-tegra/include/mach/spl_uart.h new file mode 100644 index 000000000000..28b14acce93b --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/spl_uart.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MACH_SPL_UART_H +#define _MACH_SPL_UART_H + +enum tegra_spl_uart { + TEGRA_SPL_UART_A, + TEGRA_SPL_UART_B, + TEGRA_SPL_UART_C, + TEGRA_SPL_UART_D, + TEGRA_SPL_UART_E, +}; + +void tegra_spl_setup_uart(enum tegra_spl_uart uart_id); + +#endif diff --git a/arch/arm/mach-tegra/spl_uart.c b/arch/arm/mach-tegra/spl_uart.c new file mode 100644 index 000000000000..2c1d237174fd --- /dev/null +++ b/arch/arm/mach-tegra/spl_uart.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <ns16550.h> +#include <asm/arch/clock.h> +#include <mach/spl_uart.h> + +static struct ns16550_platdata ns16550_com1_pdata = { + .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_com1) = { + "ns16550_serial", &ns16550_com1_pdata +}; + +static const struct { + unsigned long addr; + enum periph_id periph_id; +} uart_info[] = { + { NV_PA_APB_UARTA_BASE, PERIPH_ID_UART1, }, + { NV_PA_APB_UARTB_BASE, PERIPH_ID_UART2, }, + { NV_PA_APB_UARTC_BASE, PERIPH_ID_UART3, }, + { NV_PA_APB_UARTD_BASE, PERIPH_ID_UART4, }, + { NV_PA_APB_UARTE_BASE, PERIPH_ID_UART5, }, +}; + +void tegra_spl_setup_uart(unsigned int uart_id) +{ + if (uart_id >= ARRAY_SIZE(uart_info)) + return; + clock_ll_start_uart(uart_info[uart_id].periph_id); + ns16550_com1_pdata.base = uart_info[uart_id].addr; +}
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Currently, SPL console initialization on Tegra suffers from two problems:
- It's a monolithic function that knows about all possibilities using
tables and ifdefs set by board config.h, and contained in core files that are always built into U-Boot. Some of the code can't be ported to future SoCs since the clock APIs will be different. Equally, future SoCs don't need the code since earlier boot FW will always initialized the UART.
- It's unnecessarily invoked twice, once by SPL and once by the main
U-Boot binary.
This patch adds simpler APIs to initialize the UART from SPL. This code can be omitted from non-SPL builds.
A future patch will add the code to the Makefile when board files are converted. Adding it now would cause duplicate symbols for the UART device itself which will cause the link to fail. Even if that were resolved by changing the symbol name, duplicate UART devices would be registered, which would likely cause runtime problems.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/include/mach/spl_uart.h | 20 +++++++++++++++ arch/arm/mach-tegra/spl_uart.c | 39 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-tegra/include/mach/spl_uart.h create mode 100644 arch/arm/mach-tegra/spl_uart.c
Reviewed-by: Simon Glass sjg@chromium.org
One thought below.
diff --git a/arch/arm/mach-tegra/include/mach/spl_uart.h b/arch/arm/mach-tegra/include/mach/spl_uart.h new file mode 100644 index 000000000000..28b14acce93b --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/spl_uart.h @@ -0,0 +1,20 @@ +/*
- Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0
- */
+#ifndef _MACH_SPL_UART_H +#define _MACH_SPL_UART_H
+enum tegra_spl_uart {
TEGRA_SPL_UART_A,TEGRA_SPL_UART_B,TEGRA_SPL_UART_C,TEGRA_SPL_UART_D,TEGRA_SPL_UART_E,+};
+void tegra_spl_setup_uart(enum tegra_spl_uart uart_id);
+#endif diff --git a/arch/arm/mach-tegra/spl_uart.c b/arch/arm/mach-tegra/spl_uart.c new file mode 100644 index 000000000000..2c1d237174fd --- /dev/null +++ b/arch/arm/mach-tegra/spl_uart.c @@ -0,0 +1,39 @@ +/*
- Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0
- */
+#include <common.h> +#include <dm.h> +#include <ns16550.h> +#include <asm/arch/clock.h> +#include <mach/spl_uart.h>
+static struct ns16550_platdata ns16550_com1_pdata = {
.reg_shift = 2,.clock = CONFIG_SYS_NS16550_CLK,+};
+U_BOOT_DEVICE(ns16550_com1) = {
"ns16550_serial", &ns16550_com1_pdata+};
+static const struct {
unsigned long addr;enum periph_id periph_id;+} uart_info[] = {
{ NV_PA_APB_UARTA_BASE, PERIPH_ID_UART1, },{ NV_PA_APB_UARTB_BASE, PERIPH_ID_UART2, },{ NV_PA_APB_UARTC_BASE, PERIPH_ID_UART3, },{ NV_PA_APB_UARTD_BASE, PERIPH_ID_UART4, },{ NV_PA_APB_UARTE_BASE, PERIPH_ID_UART5, },+};
+void tegra_spl_setup_uart(unsigned int uart_id)
I wonder whether we could eliminate the uart_id concept at some point?
+{
if (uart_id >= ARRAY_SIZE(uart_info))return;clock_ll_start_uart(uart_info[uart_id].periph_id);ns16550_com1_pdata.base = uart_info[uart_id].addr;+}
2.8.1
Regards, Simon
From: Stephen Warren swarren@nvidia.com
Tegra's board2.c and spl.c implement the core U-Boot board initialization hooks, and call a variety of other functions to initialize the system, some of which are implemented by board-specific code. board2.c and spl.c currently call a large variety of "hook" functions that boards can customize, one per type of action that might be performed by a board. This isn't very scalable, and leads to a lot of ifdefs in board2.c. This patch creates yet more functions that board2.c ans spl.c will call, with the aim that all other functionality will be migrated into those functions.
The new functions are added to a new header file to make it more obvious which are "the new way" and which will eventually go away (board.h).
Two simple one-off cases are immediately converted to the new functions, and the old functions removed. Other functions require a bit more work and will be converted by separate patches.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 17 +++++++++++------ arch/arm/mach-tegra/include/mach/board.h | 7 ------- arch/arm/mach-tegra/include/mach/board_init.h | 15 +++++++++++++++ arch/arm/mach-tegra/spl.c | 4 ++++ board/nvidia/nyan-big/nyan-big.c | 2 +- board/nvidia/p2571/p2571.c | 7 ++----- 6 files changed, 33 insertions(+), 19 deletions(-) create mode 100644 arch/arm/mach-tegra/include/mach/board_init.h
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 2667efe5aa71..cf17f709d480 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -21,6 +21,7 @@ #include <usb.h> #endif #include <mach/board.h> +#include <mach/board_init.h> #ifdef CONFIG_TEGRA_MMC #include <mach/tegra_mmc.h> #endif @@ -52,7 +53,6 @@ __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} __weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {} -__weak void start_cpu_fan(void) {}
#if defined(CONFIG_TEGRA_NAND) __weak void pin_mux_nand(void) @@ -100,7 +100,7 @@ __weak int tegra_lcd_pmic_init(int board_it) return 0; }
-__weak int nvidia_board_init(void) +__weak int tegra_board_init(void) { return 0; } @@ -174,16 +174,17 @@ int board_init(void) /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif - return nvidia_board_init(); + return tegra_board_init(); }
-#ifdef CONFIG_BOARD_EARLY_INIT_F static void __gpio_early_init(void) { }
void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
+__weak void tegra_board_early_init_f(void) {} + int board_early_init_f(void) { #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) @@ -200,6 +201,8 @@ int board_early_init_f(void) #endif arch_timer_init();
+ tegra_board_early_init_f(); + pinmux_init(); board_init_uart_f();
@@ -209,7 +212,8 @@ int board_early_init_f(void)
return 0; } -#endif /* EARLY_INIT */ + +__weak void tegra_board_late_init(void) {}
int board_late_init(void) { @@ -221,7 +225,8 @@ int board_late_init(void) setenv("cpu_ns_mode", ""); } #endif - start_cpu_fan(); + + tegra_board_late_init();
return 0; } diff --git a/arch/arm/mach-tegra/include/mach/board.h b/arch/arm/mach-tegra/include/mach/board.h index f6688ef761e7..b12ec7eed25e 100644 --- a/arch/arm/mach-tegra/include/mach/board.h +++ b/arch/arm/mach-tegra/include/mach/board.h @@ -43,11 +43,4 @@ int tegra_lcd_pmic_init(int board_id); */ int tegra_board_id(void);
-/** - * nvidia_board_init() - perform any board-specific init - * - * @return 0 if OK, -ve on error - */ -int nvidia_board_init(void); - #endif diff --git a/arch/arm/mach-tegra/include/mach/board_init.h b/arch/arm/mach-tegra/include/mach/board_init.h new file mode 100644 index 000000000000..fe13b8e9439b --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/board_init.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MACH_BOARD_INIT_H +#define _MACH_BOARD_INIT_H + +void tegra_spl_board_init(void); +void tegra_board_early_init_f(void); +int tegra_board_init(void); +void tegra_board_late_init(void); + +#endif diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 49af4119e927..35b538f0f614 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -14,9 +14,12 @@ #include <asm/arch/tegra.h> #include <asm/spl.h> #include <mach/board.h> +#include <mach/board_init.h> #include "apb_misc.h" #include "cpu.h"
+__weak void tegra_spl_board_init(void) {} + void spl_board_init(void) { struct apb_misc_pp_ctlr *apb_misc = @@ -31,6 +34,7 @@ void spl_board_init(void) gpio_early_init_uart();
clock_early_init(); + tegra_spl_board_init(); preloader_console_init(); }
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index fd9669ba0bb5..1af7f535f6d4 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -104,7 +104,7 @@ static void enable_required_clocks(void) reset_set_enable(ids[i], 0); }
-int nvidia_board_init(void) +int tegra_board_init(void) { clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 58e5c56c5b16..ae9b6aa2e54c 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -52,12 +52,9 @@ void pinmux_init(void) ARRAY_SIZE(p2571_drvgrps)); }
-/* - * Routine: start_cpu_fan - * Description: Enable/start PWM CPU fan on P2571 - */ -void start_cpu_fan(void) +void tegra_board_late_init(void) { + /* Enable/start PWM CPU fan */ /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD"); gpio_direction_output(TEGRA_GPIO(E, 4), 1);
From: Stephen Warren swarren@nvidia.com
Implementations of the following functions are converted to use the new standardized hooks: gpio_early_init, gpio_early_init_uart, pinmux_init, board_init_uart_f. This simplifies the core board files.
SPL UART configuration is moved out of config headers and into board code. This removes logic from the board configuration files.
The now-unused board_init_uart_f() implementation is deleted, simplifying the core board files and removing code that's hard to port to future SoCs.
Whitespace was removed from tegra_board_early_init_f() to save space and be consistent between boards.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/board.c | 114 ------------------------------ arch/arm/mach-tegra/board2.c | 15 ---- arch/arm/mach-tegra/cpu.h | 2 - arch/arm/mach-tegra/include/mach/board.h | 7 -- arch/arm/mach-tegra/spl.c | 5 -- board/avionic-design/common/tamonten-ng.c | 22 ++++-- board/avionic-design/common/tamonten.c | 12 +++- board/compal/paz00/paz00.c | 8 +++ board/compulab/trimslice/trimslice.c | 10 ++- board/nvidia/cardhu/cardhu.c | 18 ++--- board/nvidia/dalmore/dalmore.c | 21 +++--- board/nvidia/e2220-1170/e2220-1170.c | 10 +-- board/nvidia/harmony/harmony.c | 8 +++ board/nvidia/jetson-tk1/jetson-tk1.c | 21 +++--- board/nvidia/nyan-big/nyan-big.c | 14 ++-- board/nvidia/p2371-0000/p2371-0000.c | 10 +-- board/nvidia/p2371-2180/p2371-2180.c | 10 +-- board/nvidia/p2571/p2571.c | 10 +-- board/nvidia/seaboard/seaboard.c | 12 ++-- board/nvidia/venice2/venice2.c | 14 ++-- board/nvidia/whistler/whistler.c | 10 ++- board/toradex/apalis_t30/apalis_t30.c | 20 +++--- board/toradex/colibri_t20/colibri_t20.c | 8 +++ board/toradex/colibri_t30/colibri_t30.c | 14 ++-- include/configs/apalis_t30.h | 5 +- include/configs/cardhu.h | 6 +- include/configs/colibri_t20.h | 6 +- include/configs/colibri_t30.h | 5 +- include/configs/dalmore.h | 6 +- include/configs/e2220-1170.h | 5 +- include/configs/harmony.h | 12 +--- include/configs/jetson-tk1.h | 6 +- include/configs/nyan-big.h | 6 +- include/configs/p2371-0000.h | 5 +- include/configs/p2371-2180.h | 5 +- include/configs/p2571.h | 6 +- include/configs/paz00.h | 6 +- include/configs/seaboard.h | 4 -- include/configs/tec-ng.h | 5 +- include/configs/tec.h | 6 +- include/configs/trimslice.h | 7 +- include/configs/venice2.h | 6 +- include/configs/whistler.h | 7 +- 44 files changed, 174 insertions(+), 336 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f1c1f84fc933..55086c9ddfef 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -26,6 +26,7 @@ obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_SPL_BUILD) += i2c_early.o +obj-$(CONFIG_SPL_BUILD) += spl_uart.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 71eb1a5d1b63..a5ee5a3572b1 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -6,8 +6,6 @@ */
#include <common.h> -#include <dm.h> -#include <ns16550.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -21,16 +19,6 @@ void save_boot_params_ret(void);
DECLARE_GLOBAL_DATA_PTR;
-enum { - /* UARTs which we can enable */ - UARTA = 1 << 0, - UARTB = 1 << 1, - UARTC = 1 << 2, - UARTD = 1 << 3, - UARTE = 1 << 4, - UART_COUNT = 5, -}; - static bool from_spl __attribute__ ((section(".data")));
#ifndef CONFIG_SPL_BUILD @@ -121,108 +109,6 @@ int dram_init(void) return 0; }
-static int uart_configs[] = { -#if defined(CONFIG_TEGRA20) - #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) - FUNCMUX_UART1_UAA_UAB, - #elif defined(CONFIG_TEGRA_UARTA_GPU) - FUNCMUX_UART1_GPU, - #elif defined(CONFIG_TEGRA_UARTA_SDIO1) - FUNCMUX_UART1_SDIO1, - #else - FUNCMUX_UART1_IRRX_IRTX, -#endif - FUNCMUX_UART2_UAD, - -1, - FUNCMUX_UART4_GMC, - -1, -#elif defined(CONFIG_TEGRA30) - FUNCMUX_UART1_ULPI, /* UARTA */ - -1, - -1, - -1, - -1, -#elif defined(CONFIG_TEGRA114) - -1, - -1, - -1, - FUNCMUX_UART4_GMI, /* UARTD */ - -1, -#elif defined(CONFIG_TEGRA124) - FUNCMUX_UART1_KBC, /* UARTA */ - -1, - -1, - FUNCMUX_UART4_GPIO, /* UARTD */ - -1, -#else /* Tegra210 */ - FUNCMUX_UART1_UART1, /* UARTA */ - -1, - -1, - FUNCMUX_UART4_UART4, /* UARTD */ - -1, -#endif -}; - -/** - * Set up the specified uarts - * - * @param uarts_ids Mask containing UARTs to init (UARTx) - */ -static void setup_uarts(int uart_ids) -{ - static enum periph_id id_for_uart[] = { - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - }; - size_t i; - - for (i = 0; i < UART_COUNT; i++) { - if (uart_ids & (1 << i)) { - enum periph_id id = id_for_uart[i]; - - funcmux_select(id, uart_configs[i]); - clock_ll_start_uart(id); - } - } -} - -void board_init_uart_f(void) -{ - int uart_ids = 0; /* bit mask of which UART ids to enable */ - -#ifdef CONFIG_TEGRA_ENABLE_UARTA - uart_ids |= UARTA; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTB - uart_ids |= UARTB; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTC - uart_ids |= UARTC; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTD - uart_ids |= UARTD; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTE - uart_ids |= UARTE; -#endif - setup_uarts(uart_ids); -} - -#if !CONFIG_IS_ENABLED(OF_CONTROL) -static struct ns16550_platdata ns16550_com1_pdata = { - .base = CONFIG_SYS_NS16550_COM1, - .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, -}; - -U_BOOT_DEVICE(ns16550_com1) = { - "ns16550_serial", &ns16550_com1_pdata -}; -#endif - #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index cf17f709d480..91965cbc3176 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -48,10 +48,8 @@ U_BOOT_DEVICE(tegra_gpios) = { }; #endif
-__weak void pinmux_init(void) {} __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} -__weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {}
#if defined(CONFIG_TEGRA_NAND) @@ -177,12 +175,6 @@ int board_init(void) return tegra_board_init(); }
-static void __gpio_early_init(void) -{ -} - -void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); - __weak void tegra_board_early_init_f(void) {}
int board_early_init_f(void) @@ -203,13 +195,6 @@ int board_early_init_f(void)
tegra_board_early_init_f();
- pinmux_init(); - board_init_uart_f(); - - /* Initialize periph GPIOs */ - gpio_early_init(); - gpio_early_init_uart(); - return 0; }
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 4cb0b43b3723..ecc627c5c09d 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -65,7 +65,5 @@ void config_cache(void); #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) bool tegra_cpu_is_non_secure(void); #endif -/* Set up early UART output */ -void board_init_uart_f(void);
#endif diff --git a/arch/arm/mach-tegra/include/mach/board.h b/arch/arm/mach-tegra/include/mach/board.h index b12ec7eed25e..a621f37aa38a 100644 --- a/arch/arm/mach-tegra/include/mach/board.h +++ b/arch/arm/mach-tegra/include/mach/board.h @@ -8,12 +8,6 @@ #ifndef _MACH_BOARD_H #define _MACH_BOARD_H
-/* Set up pinmux to make UART usable */ -void gpio_early_init_uart(void); - -/* Set up any early GPIOs the board might need for proper operation */ -void gpio_early_init(void); /* overrideable GPIO config */ - /* * Hooks to allow boards to set up the pinmux for a specific function. * Has to be implemented in the board files as we don't yet support pinmux @@ -21,7 +15,6 @@ void gpio_early_init(void); /* overrideable GPIO config */ * an empty stub function will be called. */
-void pinmux_init(void); /* overridable general pinmux setup */ void pin_mux_usb(void); /* overridable USB pinmux setup */ void pin_mux_spi(void); /* overridable SPI pinmux setup */ void pin_mux_nand(void); /* overridable NAND pinmux setup */ diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 35b538f0f614..1c01f6c93c46 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -28,11 +28,6 @@ void spl_board_init(void) /* enable JTAG */ writel(0xC0, &apb_misc->cfg_ctl);
- board_init_uart_f(); - - /* Initialize periph GPIOs */ - gpio_early_init_uart(); - clock_early_init(); tegra_spl_board_init(); preloader_console_init(); diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 9955af3f6bbb..695d0e714461 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -11,7 +11,9 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> #include "pinmux-config-tamonten-ng.h"
#define PMU_I2C_ADDRESS 0x2D @@ -27,7 +29,20 @@
#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV)
-void pinmux_init(void) +void tegra_spl_board_init(void) +{ +#if 0 + /* + * The funcmux call that used to be in arch/arm/mach-tegra/board.c + * setup_uarts() for Tegra30 UARTD triggered an error and so did + * nothing. Do nothing here too. + */ + tegra30_pinmux_uartd_missing(); +#endif + tegra_spl_setup_uart(TEGRA_SPL_UART_D); +} + +void tegra_board_early_init_f(void) { pinmux_config_pingrp_table(tamonten_ng_pinmux_common, ARRAY_SIZE(tamonten_ng_pinmux_common)); @@ -37,10 +52,7 @@ void pinmux_init(void) /* Initialize any non-default pad configs (APB_MISC_GP regs) */ pinmux_config_drvgrp_table(tamonten_ng_padctrl, ARRAY_SIZE(tamonten_ng_padctrl)); -}
-void gpio_early_init(void) -{ /* Turn on the alive signal */ gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); gpio_direction_output(TEGRA_GPIO(V, 2), 1); @@ -85,7 +97,7 @@ void pin_mux_mmc(void) { /* * NOTE: We don't do mmc-specific pin muxes here. - * They were done globally in pinmux_init(). + * They were done globally in tegra_board_early_init_f(). */
/* Bring up the SDIO1 power rail */ diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 7d3a5e72bc19..0b1ed37c8b52 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -17,15 +17,21 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/board.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h>
-#ifdef CONFIG_BOARD_EARLY_INIT_F -void gpio_early_init(void) +void tegra_spl_board_init(void) +{ + tegra20_pinmux_uartd_gmc(); + tegra_spl_setup_uart(TEGRA_SPL_UART_D); +} + +void tegra_board_early_init_f(void) { gpio_request(TEGRA_GPIO(I, 4), NULL); gpio_direction_output(TEGRA_GPIO(I, 4), 1); } -#endif
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 8ae07d396474..e591af4f7b78 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -11,7 +11,15 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> + +void tegra_spl_board_init(void) +{ + tegra20_pinmux_uarta_irrx_irtx(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +}
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index a1f4f2213dc8..3fd10b2be4aa 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -6,13 +6,21 @@ */
#include <common.h> +#include <i2c.h> #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> -#include <i2c.h> +#include <mach/spl_uart.h> + +void tegra_spl_board_init(void) +{ + tegra20_pinmux_uarta_gpu(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +}
void pin_mux_usb(void) { diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index b78d2bf46d24..f5c04b45664f 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -10,24 +10,26 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> #include "pinmux-config-cardhu.h"
#define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra30_pinmux_uarta_ulpi(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + +void tegra_board_early_init_f(void) { pinmux_config_pingrp_table(tegra3_pinmux_common, ARRAY_SIZE(tegra3_pinmux_common)); - pinmux_config_pingrp_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); - /* Initialize any non-default pad configs (APB_MISC_GP regs) */ pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); } @@ -77,7 +79,7 @@ void pin_mux_mmc(void) { /* * NOTE: We don't do mmc-specific pin muxes here. - * They were done globally in pinmux_init(). + * They were done globally in tegra_board_early_init_f(). */
/* Bring up the SDIO1 power rail */ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index ad9214d1e37a..3af42fa79ff2 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -6,28 +6,29 @@
#include <common.h> #include <dm.h> +#include <i2c.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> #include "pinmux-config-dalmore.h" -#include <i2c.h>
#define BAT_I2C_ADDRESS 0x48 /* TPS65090 charger */ #define PMU_I2C_ADDRESS 0x58 /* TPS65913 PMU */
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra114_pinmux_uartd_gmi(); + tegra_spl_setup_uart(TEGRA_SPL_UART_D); +} + +void tegra_board_early_init_f(void) { pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate, ARRAY_SIZE(tegra114_pinmux_set_nontristate)); - pinmux_config_pingrp_table(tegra114_pinmux_common, ARRAY_SIZE(tegra114_pinmux_common)); - pinmux_config_pingrp_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); - /* Initialize any non-default pad configs (APB_MISC_GP regs) */ pinmux_config_drvgrp_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); @@ -91,7 +92,7 @@ void pin_mux_mmc(void) { /* * NOTE: We don't do mmc-specific pin muxes here. - * They were done globally in pinmux_init(). + * They were done globally in tegra_board_early_init_f(). */
/* Bring up the SDIO3 power rail */ diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index 5d2f3589b678..9ccdc28b0b32 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" @@ -34,20 +35,13 @@ void pin_mux_mmc(void) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_board_early_init_f(void) { pinmux_clear_tristate_input_clamping(); - gpio_config_table(e2220_1170_gpio_inits, ARRAY_SIZE(e2220_1170_gpio_inits)); - pinmux_config_pingrp_table(e2220_1170_pingrps, ARRAY_SIZE(e2220_1170_pingrps)); - pinmux_config_drvgrp_table(e2220_1170_drvgrps, ARRAY_SIZE(e2220_1170_drvgrps)); } diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 4f3df8fe9655..0139a2fdb239 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -12,7 +12,15 @@ #include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> + +void tegra_spl_board_init(void) +{ + tegra20_pinmux_uartd_gmc(); + tegra_spl_setup_uart(TEGRA_SPL_UART_D); +}
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index bac2d0c36101..cb2f8abf47bf 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -9,29 +9,32 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> +#include <mach/spl_uart.h> #include <mach/tegra_gpio.h> #include "pinmux-config-jetson-tk1.h"
DECLARE_GLOBAL_DATA_PTR;
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +#include <asm/arch/clock.h> + +void tegra_spl_board_init(void) { - pinmux_clear_tristate_input_clamping(); + tegra124_pinmux_uartd_gpio(); + tegra_spl_setup_uart(TEGRA_SPL_UART_D); +}
+void tegra_board_early_init_f(void) +{ + pinmux_clear_tristate_input_clamping(); gpio_config_table(jetson_tk1_gpio_inits, ARRAY_SIZE(jetson_tk1_gpio_inits)); - pinmux_config_pingrp_table(jetson_tk1_pingrps, ARRAY_SIZE(jetson_tk1_pingrps)); - pinmux_config_drvgrp_table(jetson_tk1_drvgrps, ARRAY_SIZE(jetson_tk1_drvgrps)); - pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps, ARRAY_SIZE(jetson_tk1_mipipadctrlgrps)); } diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 1af7f535f6d4..762dc955d7c1 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -14,15 +14,19 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> +#include <mach/spl_uart.h> #include "pinmux-config-nyan-big.h"
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra124_pinmux_uarta_kbc(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + +void tegra_board_early_init_f(void) { gpio_config_table(nyan_big_gpio_inits, ARRAY_SIZE(nyan_big_gpio_inits)); diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index a63f95f1f4f1..6152f8898c6d 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" @@ -34,20 +35,13 @@ void pin_mux_mmc(void) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_board_early_init_f(void) { pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2371_0000_gpio_inits, ARRAY_SIZE(p2371_0000_gpio_inits)); - pinmux_config_pingrp_table(p2371_0000_pingrps, ARRAY_SIZE(p2371_0000_pingrps)); - pinmux_config_drvgrp_table(p2371_0000_drvgrps, ARRAY_SIZE(p2371_0000_drvgrps)); } diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index c9884bd70335..8e0a5834415f 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "../p2571/max77620_init.h" @@ -34,20 +35,13 @@ void pin_mux_mmc(void) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_board_early_init_f(void) { pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2371_2180_gpio_inits, ARRAY_SIZE(p2371_2180_gpio_inits)); - pinmux_config_pingrp_table(p2371_2180_pingrps, ARRAY_SIZE(p2371_2180_pingrps)); - pinmux_config_drvgrp_table(p2371_2180_drvgrps, ARRAY_SIZE(p2371_2180_drvgrps)); } diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index ae9b6aa2e54c..ee82cc9e6fd7 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include "max77620_init.h" @@ -34,20 +35,13 @@ void pin_mux_mmc(void) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_board_early_init_f(void) { pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2571_gpio_inits, ARRAY_SIZE(p2571_gpio_inits)); - pinmux_config_pingrp_table(p2571_pingrps, ARRAY_SIZE(p2571_pingrps)); - pinmux_config_drvgrp_table(p2571_drvgrps, ARRAY_SIZE(p2571_drvgrps)); } diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index cc017554548a..1a430461aa02 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -13,17 +13,21 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <mach/board.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h>
-/* TODO: Remove this code when the SPI switch is working */ -#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) -void gpio_early_init_uart(void) +void tegra_spl_board_init(void) { + tegra20_pinmux_uartd_gmc(); + tegra_spl_setup_uart(TEGRA_SPL_UART_D); + +#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ gpio_request(TEGRA_GPIO(I, 3), "uart_en"); gpio_direction_output(TEGRA_GPIO(I, 3), 0); -} #endif +}
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index 9b02afd16040..6ed5f4af8cd4 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -8,15 +8,19 @@ #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> +#include <mach/spl_uart.h> #include "pinmux-config-venice2.h"
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra124_pinmux_uarta_kbc(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + +void tegra_board_early_init_f(void) { pinmux_set_tristate_input_clamping();
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index b2c71a361afd..757bef019718 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -7,13 +7,21 @@
#include <common.h> #include <dm.h> +#include <i2c.h> #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/gpio.h> +#include <mach/board_init.h> #include <mach/pinmux.h> -#include <i2c.h> +#include <mach/spl_uart.h> + +void tegra_spl_board_init(void) +{ + tegra20_pinmux_uarta_uaa_uab(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +}
#ifdef CONFIG_TEGRA_MMC /* diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 06fddec6e0fe..3db9308323fd 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -7,12 +7,14 @@ */
#include <common.h> +#include <dm.h> +#include <i2c.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> +#include <mach/board_init.h> #include <mach/pinmux.h> -#include <dm.h> -#include <i2c.h> +#include <mach/spl_uart.h>
#include "pinmux-config-apalis_t30.h"
@@ -28,18 +30,18 @@ int arch_misc_init(void) return 0; }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra30_pinmux_uarta_ulpi(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + +void tegra_board_early_init_f(void) { pinmux_config_pingrp_table(tegra3_pinmux_common, ARRAY_SIZE(tegra3_pinmux_common)); - pinmux_config_pingrp_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); - /* Initialize any non-default pad configs (APB_MISC_GP regs) */ pinmux_config_drvgrp_table(apalis_t30_padctrl, ARRAY_SIZE(apalis_t30_padctrl)); diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 87dfcd5f3f19..44851536e6c8 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -14,7 +14,9 @@ #include <asm/arch/funcmux.h> #include <asm/arch-tegra/tegra.h> #include <mach/board.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h>
#define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 @@ -22,6 +24,12 @@ #define PMU_SUPPLYENE_SYSINEN (1<<5) #define PMU_SUPPLYENE_EXITSLREQ (1<<1)
+void tegra_spl_board_init(void) +{ + tegra20_pinmux_uarta_sdio1(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + int arch_misc_init(void) { /* Disable PMIC sleep mode on low supply voltage */ diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 1be24b86fdc4..62a151a9dcb7 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -12,7 +12,9 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-tegra/tegra.h> +#include <mach/board_init.h> #include <mach/pinmux.h> +#include <mach/spl_uart.h> #include "pinmux-config-colibri_t30.h"
int arch_misc_init(void) @@ -24,11 +26,13 @@ int arch_misc_init(void) return 0; }
-/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) +void tegra_spl_board_init(void) +{ + tegra30_pinmux_uarta_ulpi(); + tegra_spl_setup_uart(TEGRA_SPL_UART_A); +} + +void tegra_board_early_init_f(void) { pinmux_config_pingrp_table(tegra3_pinmux_common, ARRAY_SIZE(tegra3_pinmux_common)); diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 32e9ba38d9df..d104aa9ccae9 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014-2015 Marcel Ziswiler + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * Configuration settings for the Toradex Apalis T30 modules. * @@ -18,10 +19,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
/* I2C */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index acfe96895fbb..cb90f3ccaa86 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -21,10 +21,6 @@ "board_name=cardhu-a04\0" \ "fdtfile=tegra30-cardhu-a04.dtb\0"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
/* I2C */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index e97e5a10dc26..93ed102a734c 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Lucas Stach + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * Configuration settings for the Toradex Colibri T20 modules. * @@ -16,11 +17,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T20
/* I2C */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 47914c767987..e5aaab742388 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2015 Stefan Agner + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * Configuration settings for the Toradex Colibri T30 modules. * @@ -18,10 +19,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
/* I2C */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index f74ced1b4395..43b81b63932d 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -14,10 +14,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
/* I2C */ diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 33ebb7c7afaa..6f4bfb2eb40b 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 0a3cb18a2ec4..ab1de5c23ad5 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,16 +14,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD - -/* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA_ENABLE_UARTA -/* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE -#endif - #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
/* SD/MMC */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 59dbb208cdd8..2ee15fa8775c 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2014 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0 @@ -18,10 +18,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 0b6173be9b81..6d037ba4e460 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,10 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_DISPLAY_BOARDINFO_LATE
/* I2C */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 9ca29f8b4ee1..0a066b7a1c70 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index c55f07ede277..3337080efe3f 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/p2571.h b/include/configs/p2571.h index d35e25524f9a..d8a5fdf15aca 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,10 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
-/* Board-specific serial config */ -#define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA_ENABLE_UARTA - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 6acecb1e27a1..18a7d5229f39 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016 NVIDIA CORPORATION. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -16,10 +16,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
/* SD/MMC */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 09509b45f993..a301b8fbf47d 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -22,10 +22,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
/* I2C */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 019e32ce867d..699eee3ab141 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -1,6 +1,7 @@ /* * (C) Copyright 2013 * Avionic Design GmbH <www.avionic-design.de> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,10 +14,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/tec.h b/include/configs/tec.h index a9472146b092..458d4bf093cb 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * (C) Copyright 2011-2012 * Avionic Design GmbH <www.avionic-design.de> @@ -15,10 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index ca188bec24c1..e504ee6a4c2b 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,11 +14,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
/* SPI */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 75f7268d10c2..06c2bf292658 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2014 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -15,10 +15,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/whistler.h b/include/configs/whistler.h index ff859644c36a..d42c26f336c9 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,11 +14,6 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
-/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_UAA_UAB -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
/* I2C */
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Implementations of the following functions are converted to use the new standardized hooks: gpio_early_init, gpio_early_init_uart, pinmux_init, board_init_uart_f. This simplifies the core board files.
SPL UART configuration is moved out of config headers and into board code. This removes logic from the board configuration files.
The now-unused board_init_uart_f() implementation is deleted, simplifying the core board files and removing code that's hard to port to future SoCs.
Whitespace was removed from tegra_board_early_init_f() to save space and be consistent between boards.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/board.c | 114 ------------------------------ arch/arm/mach-tegra/board2.c | 15 ---- arch/arm/mach-tegra/cpu.h | 2 - arch/arm/mach-tegra/include/mach/board.h | 7 -- arch/arm/mach-tegra/spl.c | 5 -- board/avionic-design/common/tamonten-ng.c | 22 ++++-- board/avionic-design/common/tamonten.c | 12 +++- board/compal/paz00/paz00.c | 8 +++ board/compulab/trimslice/trimslice.c | 10 ++- board/nvidia/cardhu/cardhu.c | 18 ++--- board/nvidia/dalmore/dalmore.c | 21 +++--- board/nvidia/e2220-1170/e2220-1170.c | 10 +-- board/nvidia/harmony/harmony.c | 8 +++ board/nvidia/jetson-tk1/jetson-tk1.c | 21 +++--- board/nvidia/nyan-big/nyan-big.c | 14 ++-- board/nvidia/p2371-0000/p2371-0000.c | 10 +-- board/nvidia/p2371-2180/p2371-2180.c | 10 +-- board/nvidia/p2571/p2571.c | 10 +-- board/nvidia/seaboard/seaboard.c | 12 ++-- board/nvidia/venice2/venice2.c | 14 ++-- board/nvidia/whistler/whistler.c | 10 ++- board/toradex/apalis_t30/apalis_t30.c | 20 +++--- board/toradex/colibri_t20/colibri_t20.c | 8 +++ board/toradex/colibri_t30/colibri_t30.c | 14 ++-- include/configs/apalis_t30.h | 5 +- include/configs/cardhu.h | 6 +- include/configs/colibri_t20.h | 6 +- include/configs/colibri_t30.h | 5 +- include/configs/dalmore.h | 6 +- include/configs/e2220-1170.h | 5 +- include/configs/harmony.h | 12 +--- include/configs/jetson-tk1.h | 6 +- include/configs/nyan-big.h | 6 +- include/configs/p2371-0000.h | 5 +- include/configs/p2371-2180.h | 5 +- include/configs/p2571.h | 6 +- include/configs/paz00.h | 6 +- include/configs/seaboard.h | 4 -- include/configs/tec-ng.h | 5 +- include/configs/tec.h | 6 +- include/configs/trimslice.h | 7 +- include/configs/venice2.h | 6 +- include/configs/whistler.h | 7 +- 44 files changed, 174 insertions(+), 336 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 8 -------- 1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 91965cbc3176..d7ca99985660 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -8,18 +8,12 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <ns16550.h> -#include <linux/compiler.h> -#include <linux/sizes.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" -#ifdef CONFIG_USB_EHCI_TEGRA -#include <usb.h> -#endif #include <mach/board.h> #include <mach/board_init.h> #ifdef CONFIG_TEGRA_MMC @@ -27,8 +21,6 @@ #endif #include <mach/xusb-padctl.h> #include <power/as3722.h> -#include <i2c.h> -#include <spi.h> #include "cpu.h" #include "gpu.h" #include "pmc.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 8 -------- 1 file changed, 8 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
SPL-specific code generally belongs in an SPL-specific file. This allows an ifdef to be removed too:-)
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 8 -------- arch/arm/mach-tegra/spl.c | 6 ++++++ 2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index d7ca99985660..fb58b5e5986a 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -6,7 +6,6 @@ */
#include <common.h> -#include <dm.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -33,13 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPL_BUILD -/* TODO(sjg@chromium.org): Remove once SPL supports device tree */ -U_BOOT_DEVICE(tegra_gpios) = { - "gpio_tegra" -}; -#endif - __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} __weak void pin_mux_display(void) {} diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 1c01f6c93c46..353a6ddfb6c2 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> #include <spl.h>
#include <asm/io.h> @@ -18,6 +19,11 @@ #include "apb_misc.h" #include "cpu.h"
+/* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +U_BOOT_DEVICE(tegra_gpios) = { + "gpio_tegra" +}; + __weak void tegra_spl_board_init(void) {}
void spl_board_init(void)
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
SPL-specific code generally belongs in an SPL-specific file. This allows an ifdef to be removed too:-)
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 8 -------- arch/arm/mach-tegra/spl.c | 6 ++++++ 2 files changed, 6 insertions(+), 8 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Implementations of the following functions are converted to use the new standardized hooks: pin_mux_usb, pin_mux_spi, pin_mux_nand, pin_mux_mmc, pin_mux_display. This simplifies the core board files.
For some boards, function sort order was changed so that functions appear in they order they're called.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 36 ---------- arch/arm/mach-tegra/include/mach/board.h | 13 ---- board/avionic-design/common/tamonten-ng.c | 11 ++- board/avionic-design/common/tamonten.c | 9 --- board/compal/paz00/paz00.c | 25 +------ board/compulab/trimslice/trimslice.c | 17 +---- board/nvidia/cardhu/cardhu.c | 18 ++--- board/nvidia/dalmore/dalmore.c | 18 ++--- board/nvidia/e2220-1170/e2220-1170.c | 26 +++---- board/nvidia/harmony/harmony.c | 33 +++------ board/nvidia/p2371-0000/p2371-0000.c | 26 +++---- board/nvidia/p2371-2180/p2371-2180.c | 26 +++---- board/nvidia/p2571/p2571.c | 26 +++---- board/nvidia/seaboard/seaboard.c | 18 ++--- board/nvidia/whistler/whistler.c | 57 +++++++-------- board/toradex/colibri_t20/colibri_t20.c | 114 +++++++++++------------------- board/toradex/colibri_t30/colibri_t30.c | 8 +-- 17 files changed, 161 insertions(+), 320 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index fb58b5e5986a..d9dfb01fdcfc 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -32,17 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
-__weak void pin_mux_usb(void) {} -__weak void pin_mux_spi(void) {} -__weak void pin_mux_display(void) {} - -#if defined(CONFIG_TEGRA_NAND) -__weak void pin_mux_nand(void) -{ - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); -} -#endif - /* * Routine: power_det_init * Description: turn off power detects @@ -102,14 +91,6 @@ int board_init(void)
tegra_gpu_config();
-#ifdef CONFIG_TEGRA_SPI - pin_mux_spi(); -#endif - - /* Init is handled automatically in the driver-model case */ -#if defined(CONFIG_DM_VIDEO) - pin_mux_display(); -#endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -132,10 +113,6 @@ int board_init(void) #endif #endif /* CONFIG_SYS_I2C_TEGRA */
-#ifdef CONFIG_USB_EHCI_TEGRA - pin_mux_usb(); -#endif - #if defined(CONFIG_DM_VIDEO) board_id = tegra_board_id(); err = tegra_lcd_pmic_init(board_id); @@ -143,10 +120,6 @@ int board_init(void) return err; #endif
-#ifdef CONFIG_TEGRA_NAND - pin_mux_nand(); -#endif - tegra_xusb_padctl_init(gd->fdt_blob);
#ifdef CONFIG_TEGRA_LP0 @@ -201,19 +174,10 @@ int board_late_init(void) }
#if defined(CONFIG_TEGRA_MMC) -__weak void pin_mux_mmc(void) -{ -} - /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("%s called\n", __func__); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("%s: init MMC\n", __func__); tegra_mmc_init();
return 0; diff --git a/arch/arm/mach-tegra/include/mach/board.h b/arch/arm/mach-tegra/include/mach/board.h index a621f37aa38a..04fabeaca3c9 100644 --- a/arch/arm/mach-tegra/include/mach/board.h +++ b/arch/arm/mach-tegra/include/mach/board.h @@ -8,19 +8,6 @@ #ifndef _MACH_BOARD_H #define _MACH_BOARD_H
-/* - * Hooks to allow boards to set up the pinmux for a specific function. - * Has to be implemented in the board files as we don't yet support pinmux - * setup from FTD. If a board file does not implement one of those functions - * an empty stub function will be called. - */ - -void pin_mux_usb(void); /* overridable USB pinmux setup */ -void pin_mux_spi(void); /* overridable SPI pinmux setup */ -void pin_mux_nand(void); /* overridable NAND pinmux setup */ -void pin_mux_mmc(void); /* overridable mmc pinmux setup */ -void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ - /** * tegra_lcd_pmic_init() - Set up the PMIC for a board * diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 695d0e714461..7c3aa7e16d9c 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -62,7 +62,7 @@ void tegra_board_early_init_f(void) gpio_direction_output(TEGRA_GPIO(I, 4), 1); }
-void pmu_write(uchar reg, uchar data) +static void pmu_write(uchar reg, uchar data) { struct udevice *dev; int ret; @@ -79,7 +79,7 @@ void pmu_write(uchar reg, uchar data) * Do I2C/PMU writes to bring up SD card bus power * */ -void board_sdmmc_voltage_init(void) +static void board_sdmmc_voltage_init(void) { /* Enable LDO5 with 3.3v for SDMMC3 */ pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); @@ -89,11 +89,7 @@ void board_sdmmc_voltage_init(void) gpio_direction_output(TEGRA_GPIO(J, 2), 1); }
-/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) +int tegra_board_init(void) { /* * NOTE: We don't do mmc-specific pin muxes here. @@ -102,4 +98,5 @@ void pin_mux_mmc(void)
/* Bring up the SDIO1 power rail */ board_sdmmc_voltage_init(); + return 0; } diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 0b1ed37c8b52..4727ebdc72c8 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -31,19 +31,10 @@ void tegra_board_early_init_f(void) { gpio_request(TEGRA_GPIO(I, 4), NULL); gpio_direction_output(TEGRA_GPIO(I, 4), 1); -}
-#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); /* for write-protect GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* for CD GPIO PH2 */ pinmux_tristate_disable(PMUX_PINGRP_ATD); } -#endif diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index e591af4f7b78..562a4df1f262 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -21,41 +21,22 @@ void tegra_spl_board_init(void) tegra_spl_setup_uart(TEGRA_SPL_UART_A); }
-#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) +void tegra_board_early_init_f(void) { + /* EN_VDD_PANEL GPIO A4 */ + pinmux_tristate_disable(PMUX_PINGRP_DAP2); /* SDMMC4: config 3, x8 on 2nd set of pins */ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PMUX_PINGRP_ATB); pinmux_tristate_disable(PMUX_PINGRP_GMA); pinmux_tristate_disable(PMUX_PINGRP_GME); - /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - /* For power GPIO PV1 */ pinmux_tristate_disable(PMUX_PINGRP_UAC); /* For CD GPIO PV5 */ pinmux_tristate_disable(PMUX_PINGRP_GPV); } -#endif - -#ifdef CONFIG_DM_VIDEO -/* this is a weak define that we are overriding */ -void pin_mux_display(void) -{ - debug("init display pinmux\n"); - - /* EN_VDD_PANEL GPIO A4 */ - pinmux_tristate_disable(PMUX_PINGRP_DAP2); -} -#endif diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 3fd10b2be4aa..775343e338b5 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -22,29 +22,16 @@ void tegra_spl_board_init(void) tegra_spl_setup_uart(TEGRA_SPL_UART_A); }
-void pin_mux_usb(void) +void tegra_board_early_init_f(void) { + tegra20_pinmux_spi1_gmc_gmd(); /* * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO * in the current device tree. */ pinmux_tristate_disable(PMUX_PINGRP_UAC); -} - -void pin_mux_spi(void) -{ - funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD); -} - -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); - /* For CD GPIO PP1 */ pinmux_tristate_disable(PMUX_PINGRP_DAP3); } diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index f5c04b45664f..ec6af06bf1b5 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -39,7 +39,7 @@ void tegra_board_early_init_f(void) * Do I2C/PMU writes to bring up SD card bus power * */ -void board_sdmmc_voltage_init(void) +static void board_sdmmc_voltage_init(void) { struct udevice *dev; uchar reg, data_buffer[1]; @@ -70,22 +70,16 @@ void board_sdmmc_voltage_init(void) udelay(100); } } +#else +static void board_sdmmc_voltage_init(void) {} +#endif
-/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) +int tegra_board_init(void) { - /* - * NOTE: We don't do mmc-specific pin muxes here. - * They were done globally in tegra_board_early_init_f(). - */ - /* Bring up the SDIO1 power rail */ board_sdmmc_voltage_init(); + return 0; } -#endif /* MMC */
#ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 3af42fa79ff2..309e1933fe74 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -39,7 +39,7 @@ void tegra_board_early_init_f(void) * Do I2C/PMU writes to bring up SD card bus power * */ -void board_sdmmc_voltage_init(void) +static void board_sdmmc_voltage_init(void) { struct udevice *dev; uchar reg, data_buffer[1]; @@ -83,19 +83,13 @@ void board_sdmmc_voltage_init(void) printf("%s: BAT i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); } +#else +static void board_sdmmc_voltage_init(void) {} +#endif
-/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) +int tegra_board_init(void) { - /* - * NOTE: We don't do mmc-specific pin muxes here. - * They were done globally in tegra_board_early_init_f(). - */ - /* Bring up the SDIO3 power rail */ board_sdmmc_voltage_init(); + return 0; } -#endif /* MMC */ diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index 9ccdc28b0b32..2c5ca4089a81 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -15,7 +15,18 @@ #include "../p2571/max77620_init.h" #include "pinmux-config-e2220-1170.h"
-void pin_mux_mmc(void) +void tegra_board_early_init_f(void) +{ + pinmux_clear_tristate_input_clamping(); + gpio_config_table(e2220_1170_gpio_inits, + ARRAY_SIZE(e2220_1170_gpio_inits)); + pinmux_config_pingrp_table(e2220_1170_pingrps, + ARRAY_SIZE(e2220_1170_pingrps)); + pinmux_config_drvgrp_table(e2220_1170_drvgrps, + ARRAY_SIZE(e2220_1170_drvgrps)); +} + +int tegra_board_init(void) { struct udevice *dev; uchar val; @@ -26,22 +37,13 @@ void pin_mux_mmc(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return; + return -1; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -}
-void tegra_board_early_init_f(void) -{ - pinmux_clear_tristate_input_clamping(); - gpio_config_table(e2220_1170_gpio_inits, - ARRAY_SIZE(e2220_1170_gpio_inits)); - pinmux_config_pingrp_table(e2220_1170_pingrps, - ARRAY_SIZE(e2220_1170_pingrps)); - pinmux_config_drvgrp_table(e2220_1170_drvgrps, - ARRAY_SIZE(e2220_1170_drvgrps)); + return 0; } diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 0139a2fdb239..9429b3b70cc4 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -22,39 +22,24 @@ void tegra_spl_board_init(void) tegra_spl_setup_uart(TEGRA_SPL_UART_D); }
-#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) +void tegra_board_early_init_f(void) { + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_SDC); + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + /* USB2 PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); - /* For power GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PH2 */ pinmux_tristate_disable(PMUX_PINGRP_ATD); - /* For power GPIO PT3 */ pinmux_tristate_disable(PMUX_PINGRP_DTB); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); } -#endif - -void pin_mux_usb(void) -{ - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); - pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PMUX_PINGRP_CDEV2); - /* USB2 PHY reset GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_UAC); -} - -void pin_mux_display(void) -{ - pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); - pinmux_tristate_disable(PMUX_PINGRP_SDC); -} diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index 6152f8898c6d..29c2f9a5d355 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -15,7 +15,18 @@ #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-0000.h"
-void pin_mux_mmc(void) +void tegra_board_early_init_f(void) +{ + pinmux_clear_tristate_input_clamping(); + gpio_config_table(p2371_0000_gpio_inits, + ARRAY_SIZE(p2371_0000_gpio_inits)); + pinmux_config_pingrp_table(p2371_0000_pingrps, + ARRAY_SIZE(p2371_0000_pingrps)); + pinmux_config_drvgrp_table(p2371_0000_drvgrps, + ARRAY_SIZE(p2371_0000_drvgrps)); +} + +int tegra_board_init(void) { struct udevice *dev; uchar val; @@ -26,22 +37,13 @@ void pin_mux_mmc(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return; + return -1; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -}
-void tegra_board_early_init_f(void) -{ - pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2371_0000_gpio_inits, - ARRAY_SIZE(p2371_0000_gpio_inits)); - pinmux_config_pingrp_table(p2371_0000_pingrps, - ARRAY_SIZE(p2371_0000_pingrps)); - pinmux_config_drvgrp_table(p2371_0000_drvgrps, - ARRAY_SIZE(p2371_0000_drvgrps)); + return 0; } diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 8e0a5834415f..4dee16b9c724 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -15,7 +15,18 @@ #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h"
-void pin_mux_mmc(void) +void tegra_board_early_init_f(void) +{ + pinmux_clear_tristate_input_clamping(); + gpio_config_table(p2371_2180_gpio_inits, + ARRAY_SIZE(p2371_2180_gpio_inits)); + pinmux_config_pingrp_table(p2371_2180_pingrps, + ARRAY_SIZE(p2371_2180_pingrps)); + pinmux_config_drvgrp_table(p2371_2180_drvgrps, + ARRAY_SIZE(p2371_2180_drvgrps)); +} + +int tegra_board_init(void) { struct udevice *dev; uchar val; @@ -26,24 +37,15 @@ void pin_mux_mmc(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return; + return -1; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -}
-void tegra_board_early_init_f(void) -{ - pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2371_2180_gpio_inits, - ARRAY_SIZE(p2371_2180_gpio_inits)); - pinmux_config_pingrp_table(p2371_2180_pingrps, - ARRAY_SIZE(p2371_2180_pingrps)); - pinmux_config_drvgrp_table(p2371_2180_drvgrps, - ARRAY_SIZE(p2371_2180_drvgrps)); + return 0; }
#ifdef CONFIG_PCI_TEGRA diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index ee82cc9e6fd7..c0f61483a3b0 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -15,7 +15,18 @@ #include "max77620_init.h" #include "pinmux-config-p2571.h"
-void pin_mux_mmc(void) +void tegra_board_early_init_f(void) +{ + pinmux_clear_tristate_input_clamping(); + gpio_config_table(p2571_gpio_inits, + ARRAY_SIZE(p2571_gpio_inits)); + pinmux_config_pingrp_table(p2571_pingrps, + ARRAY_SIZE(p2571_pingrps)); + pinmux_config_drvgrp_table(p2571_drvgrps, + ARRAY_SIZE(p2571_drvgrps)); +} + +int tegra_board_init(void) { struct udevice *dev; uchar val; @@ -26,24 +37,15 @@ void pin_mux_mmc(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return; + return -1; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -}
-void tegra_board_early_init_f(void) -{ - pinmux_clear_tristate_input_clamping(); - gpio_config_table(p2571_gpio_inits, - ARRAY_SIZE(p2571_gpio_inits)); - pinmux_config_pingrp_table(p2571_pingrps, - ARRAY_SIZE(p2571_pingrps)); - pinmux_config_drvgrp_table(p2571_drvgrps, - ARRAY_SIZE(p2571_drvgrps)); + return 0; }
void tegra_board_late_init(void) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 1a430461aa02..2208e3711f19 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -29,25 +29,15 @@ void tegra_spl_board_init(void) #endif }
-#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) +void tegra_board_early_init_f(void) { + /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ + pinmux_tristate_disable(PMUX_PINGRP_SLXK); + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); - /* For power GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); } -#endif - -void pin_mux_usb(void) -{ - /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ - pinmux_tristate_disable(PMUX_PINGRP_SLXK); -} diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 757bef019718..d66742880487 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -23,43 +23,13 @@ void tegra_spl_board_init(void) tegra_spl_setup_uart(TEGRA_SPL_UART_A); }
-#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) +void tegra_board_early_init_f(void) { - struct udevice *dev; - uchar val; - int ret; - - /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ - ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); - if (ret) { - printf("%s: Cannot find MAX8907B I2C chip\n", __func__); - return; - } - val = 0x29; - ret = dm_i2c_write(dev, 0x46, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); - val = 0x00; - ret = dm_i2c_write(dev, 0x45, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); - val = 0x1f; - ret = dm_i2c_write(dev, 0x44, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); } -#endif
-/* this is a weak define that we are overriding */ -void pin_mux_usb(void) +int tegra_board_init(void) { struct udevice *dev; uchar val; @@ -75,7 +45,7 @@ void pin_mux_usb(void) ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev); if (ret) { printf("%s: Cannot find TAC6416 I2C chip\n", __func__); - return; + return -1; } val = 0x03; ret = dm_i2c_write(dev, 2, &val, 1); @@ -85,4 +55,25 @@ void pin_mux_usb(void) ret = dm_i2c_write(dev, 6, &val, 1); if (ret) printf("i2c_write 0 0x20 6 failed: %d\n", ret); + + /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ + ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX8907B I2C chip\n", __func__); + return -1; + } + val = 0x29; + ret = dm_i2c_write(dev, 0x46, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); + val = 0x00; + ret = dm_i2c_write(dev, 0x45, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); + val = 0x1f; + ret = dm_i2c_write(dev, 0x44, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); + + return 0; } diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 44851536e6c8..6af76d68392e 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -30,6 +30,49 @@ void tegra_spl_board_init(void) tegra_spl_setup_uart(TEGRA_SPL_UART_A); }
+void tegra_board_early_init_f(void) +{ + /* + * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through + * device-tree + */ + pinmux_tristate_disable(PMUX_PINGRP_DTA); + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_SDC); + /* module internal USB bus to connect ethernet chipset */ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + /* ULPI reference clock output */ + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + /* PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); + /* VBus GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_DTE); + /* Assert reset for ASIX using LAN_RESET */ + gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(V, 4), 0); + pinmux_tristate_disable(PMUX_PINGRP_GPV); + /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ + pinmux_tristate_disable(PMUX_PINGRP_SPIG); + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); + /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + pinmux_tristate_disable(PMUX_PINGRP_GMB); +} + +int tegra_board_init(void) +{ + /* Release reset for ASIX using LAN_RESET */ + udelay(5); + gpio_set_value(TEGRA_GPIO(V, 4), 1); + + return 0; +} + int arch_misc_init(void) { /* Disable PMIC sleep mode on low supply voltage */ @@ -69,74 +112,3 @@ int arch_misc_init(void)
return 0; } - -#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); - pinmux_tristate_disable(PMUX_PINGRP_GMB); -} -#endif - -#ifdef CONFIG_TEGRA_NAND -void pin_mux_nand(void) -{ - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); - - /* - * configure pingroup ATC to something unrelated to - * avoid ATC overriding KBC - */ - pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); -} -#endif - -#ifdef CONFIG_USB_EHCI_TEGRA -void pin_mux_usb(void) -{ - /* module internal USB bus to connect ethernet chipset */ - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); - - /* ULPI reference clock output */ - pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PMUX_PINGRP_CDEV2); - - /* PHY reset GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_UAC); - - /* VBus GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_DTE); - - /* Reset ASIX using LAN_RESET */ - gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); - gpio_direction_output(TEGRA_GPIO(V, 4), 0); - pinmux_tristate_disable(PMUX_PINGRP_GPV); - udelay(5); - gpio_set_value(TEGRA_GPIO(V, 4), 1); - - /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ - pinmux_tristate_disable(PMUX_PINGRP_SPIG); -} -#endif - -#ifdef CONFIG_VIDEO_TEGRA20 -/* - * Routine: pin_mux_display - * Description: setup the pin muxes/tristate values for the LCD interface) - */ -void pin_mux_display(void) -{ - /* - * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through - * device-tree - */ - pinmux_tristate_disable(PMUX_PINGRP_DTA); - - pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); - pinmux_tristate_disable(PMUX_PINGRP_SDC); -} -#endif diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 62a151a9dcb7..1860ac4fec4e 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -45,14 +45,14 @@ void tegra_board_early_init_f(void) ARRAY_SIZE(colibri_t30_padctrl)); }
-/* - * Enable AX88772B USB to LAN controller - */ -void pin_mux_usb(void) +int tegra_board_init(void) { + /* Enable AX88772B USB to LAN controller */ /* Reset ASIX using LAN_RESET */ gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET"); gpio_direction_output(TEGRA_GPIO(DD, 0), 0); udelay(5); gpio_set_value(TEGRA_GPIO(DD, 0), 1); + + return 0; }
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Implementations of the following functions are converted to use the new standardized hooks: pin_mux_usb, pin_mux_spi, pin_mux_nand, pin_mux_mmc, pin_mux_display. This simplifies the core board files.
For some boards, function sort order was changed so that functions appear in they order they're called.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 36 ---------- arch/arm/mach-tegra/include/mach/board.h | 13 ---- board/avionic-design/common/tamonten-ng.c | 11 ++- board/avionic-design/common/tamonten.c | 9 --- board/compal/paz00/paz00.c | 25 +------ board/compulab/trimslice/trimslice.c | 17 +---- board/nvidia/cardhu/cardhu.c | 18 ++--- board/nvidia/dalmore/dalmore.c | 18 ++--- board/nvidia/e2220-1170/e2220-1170.c | 26 +++---- board/nvidia/harmony/harmony.c | 33 +++------ board/nvidia/p2371-0000/p2371-0000.c | 26 +++---- board/nvidia/p2371-2180/p2371-2180.c | 26 +++---- board/nvidia/p2571/p2571.c | 26 +++---- board/nvidia/seaboard/seaboard.c | 18 ++--- board/nvidia/whistler/whistler.c | 57 +++++++-------- board/toradex/colibri_t20/colibri_t20.c | 114 +++++++++++------------------- board/toradex/colibri_t30/colibri_t30.c | 8 +-- 17 files changed, 161 insertions(+), 320 deletions(-)
This should use a pinmux driver.
- Simon
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra keyboard driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/nvidia/seaboard/seaboard.c | 1 + drivers/input/tegra-kbc.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 2208e3711f19..5bd00278e203 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -40,4 +40,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); + funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); } diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index 349d95804201..df0f52c2c6f8 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -15,7 +15,6 @@ #include <tegra-kbc.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <linux/input.h>
DECLARE_GLOBAL_DATA_PTR; @@ -260,8 +259,6 @@ static int tegra_kbd_start(struct udevice *dev) { struct tegra_kbd_priv *priv = dev_get_priv(dev);
- /* Set up pin mux and enable the clock */ - funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); clock_enable(PERIPH_ID_KBC); config_kbc_gpio(priv, priv->kbc);
Hi Stephen.
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra keyboard driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/nvidia/seaboard/seaboard.c | 1 + drivers/input/tegra-kbc.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
With a pinctrl driver this can happen automatically, or you can load your single table in the probe() method.
Regards, Simon
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra20 video driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/avionic-design/common/tamonten.c | 1 + board/compal/paz00/paz00.c | 3 +++ board/nvidia/harmony/harmony.c | 1 + board/nvidia/seaboard/seaboard.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 1 + drivers/video/tegra.c | 3 --- 6 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 4727ebdc72c8..e5748b01722a 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -37,4 +37,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_ATA); /* for CD GPIO PH2 */ pinmux_tristate_disable(PMUX_PINGRP_ATD); + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 562a4df1f262..98e7cfdc352c 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -9,6 +9,8 @@
#include <common.h> #include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> #include <mach/board_init.h> @@ -39,4 +41,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_UAC); /* For CD GPIO PV5 */ pinmux_tristate_disable(PMUX_PINGRP_GPV); + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 9429b3b70cc4..f40b9c3b3152 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -42,4 +42,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_DTB); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 5bd00278e203..8958de2bdcd8 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -41,4 +41,5 @@ void tegra_board_early_init_f(void) /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 6af76d68392e..aff036ab243c 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -62,6 +62,7 @@ void tegra_board_early_init_f(void) pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); pinmux_tristate_disable(PMUX_PINGRP_GMB); + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); }
int tegra_board_init(void) diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 5b778777619f..8543c2980cf8 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -14,7 +14,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <mach/pinmux.h> #include "tegra_dc.h"
@@ -381,8 +380,6 @@ static int handle_stage(const void *blob, struct tegra_lcd_priv *priv) * remove all mention of lcd in the stdout environment * variable. */ - - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); break; case STAGE_PANEL_VDD: if (dm_gpio_is_valid(&priv->panel_vdd))
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra20 video driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 1 + board/compal/paz00/paz00.c | 3 +++ board/nvidia/harmony/harmony.c | 1 + board/nvidia/seaboard/seaboard.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 1 + drivers/video/tegra.c | 3 --- 6 files changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index e5748b01722a..c43a93de1fc6 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -37,5 +37,10 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_ATA); /* for CD GPIO PH2 */ pinmux_tristate_disable(PMUX_PINGRP_ATD); +#ifdef CONFIG_TARGET_MEDCOM_WIDE + funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); +#endif funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 8958de2bdcd8..a2d6ba557b7b 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -40,6 +40,9 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); + funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); } diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index d66742880487..549b67d5616f 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -27,6 +27,7 @@ void tegra_board_early_init_f(void) { funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); + funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); }
int tegra_board_init(void) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index aff036ab243c..d6348f794f5e 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -62,6 +62,9 @@ void tegra_board_early_init_f(void) pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); pinmux_tristate_disable(PMUX_PINGRP_GMB); + funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); + funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); }
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 4eb68b6e11b5..b462f2264b33 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -13,7 +13,6 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_i2c.h> #include "tegra_i2c_priv.h" @@ -31,7 +30,6 @@ struct i2c_bus { int id; enum periph_id periph_id; int speed; - int pinmux_config; struct i2c_control *control; struct i2c_ctlr *regs; enum i2c_type type; @@ -110,8 +108,6 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); } - - funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); }
static void send_packet_headers( @@ -338,22 +334,7 @@ static int tegra_i2c_probe(struct udevice *dev) i2c_bus->type = dev_get_driver_data(dev); i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
- /* - * We don't have a binding for pinmux yet. Leave it out for now. So - * far no one needs anything other than the default. - */ - i2c_bus->pinmux_config = FUNCMUX_DEFAULT; i2c_bus->periph_id = clock_decode_periph_id(blob, node); - - /* - * We can't specify the pinmux config in the fdt, so I2C2 will not - * work on Seaboard. It normally has no devices on it anyway. - * You could add in this little hack if you need to use it. - * The correct solution is a pinmux binding in the fdt. - * - * if (i2c_bus->periph_id == PERIPH_ID_I2C2) - * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; - */ if (i2c_bus->periph_id == -1) return -EINVAL;
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
This should use driver model, which handles pinmux automatically if you have a pinctrl driver.
Regards, Simon
On 04/27/2016 09:12 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
This should use driver model, which handles pinmux automatically if you have a pinctrl driver.
Can you define "automatic"? I don't understand exactly which benefit you're describing there.
I'd rather keep this series as simple cleanup of existing code, and handle any large-scale DM conversions separately later. That said, as full disclosure, I'm certainly not signing up for any more work on pinctrl, especially if it involves reading the pinmux tables from DT, as I see no benefit in that. Note that in future chips the boot ROM will handle 100% of static pinmux setup so there won't be a U-Boot driver for those SoCs going forward. I'd rather not invest any more than minimal effort in something that's going away.
Hi Stephen,
On 27 April 2016 at 10:24, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 09:12 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
This should use driver model, which handles pinmux automatically if you have a pinctrl driver.
Can you define "automatic"? I don't understand exactly which benefit you're describing there.
When you probe a device, its pinmux is set up automatically, so the explicit funcmux calls can go away.
I'd rather keep this series as simple cleanup of existing code, and handle any large-scale DM conversions separately later. That said, as full disclosure, I'm certainly not signing up for any more work on pinctrl, especially if it involves reading the pinmux tables from DT, as I see no benefit in that. Note that in future chips the boot ROM will handle 100% of static pinmux setup so there won't be a U-Boot driver for those SoCs going forward. I'd rather not invest any more than minimal effort in something that's going away.
There's no need for it to read from DT, and it doesn't have to be comprehensive but I think you should create a pinctrl driver and put the funcmux stuff in that (along with processing your big tables of pinmux stuff).
Regards, Simon
On 04/27/2016 10:58 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:24, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 09:12 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
This should use driver model, which handles pinmux automatically if you have a pinctrl driver.
Can you define "automatic"? I don't understand exactly which benefit you're describing there.
When you probe a device, its pinmux is set up automatically, so the explicit funcmux calls can go away.
So the device here would be the pin controller device itself, not individual I2C/SPI/SD/... devices.
That's because the Tegra HW does not support[1] dynamic or partial pinmux configuration. As such, we need to program the entire pinmux at once early during boot, not piece-by-piece as the individual U-Boot devices that use individual pins are probed. This is why for example the kernel DT contains a single pinmux table that the pin controller driver sets up at boot (with identical configuration to what U-Boot sets up, so it's a no-op), rather than splitting it into per-device chunks.
As such, there isn't any need for, say, an I2C device probe to call into pinmux at all; the pinmux would already have been set up entirely during early boot, and hence no I2C-specific actions would be needed later.
So I'm not sure what benefit conversion to DM pinctrl has here. Sure it means things get set up the same way as with any other pinctrl device or SoC, but this is early SoC-specific configuration, without any interaction with common or driver code besides being implemented via some standard core->board callbacks/hooks. It seems reasonable to just program the pinmux directly using SoC-specific APIs rather than having to add a layer of abstraction on top of it just so we can route it through DM. In other words, what's already done by this patch series.
Besides, I believe the programming happens before a DM pinctrl device would be ready, doesn't it, given it happens from tegra_board_early_init_f()? Or, would we be able to fully probe a DM device at that point? The UART console setup is even earlier, in SPL pre-T210, where I don't think we even have DM enabled.
[1] Yes, the HW registers can in practice be programmed bit-by-bit, simply because there are a number of registers and the SoC doesn't have a way to physically force SW to write to each of those registers. "Support" here refers to what the ASIC team will guarantee will work correctly without causing glitches or similar issues. There are a few limited exceptions, e.g. console UART muxing on its own has been at least partially thought out (although there are still conflicts in some cases on older chips), and IO controllers that may contain boot media are generally OK to mux on their own. However, for anything else, i.e. the majority of cases, the supported model is to program everything up-front in one go, and not change it later. Sticking to that general model in absolutely all cases removes special cases and simplifies the code.
Hi Stephen,
On 27 April 2016 at 11:16, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 10:58 AM, Simon Glass wrote:
Hi Stephen,
On 27 April 2016 at 10:24, Stephen Warren swarren@wwwdotorg.org wrote:
On 04/27/2016 09:12 AM, Simon Glass wrote:
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Remove funcmux calls from the Tegra I2C driver. Knowledge of pinmux setup must come from either board files or DT; it should not be embedded into board-agnostic driver code. The DT pinmux bindings do not allow drivers to derive funcmux-style information, since the DT bindings are pin-based whereas funcmux is controller-based, so there's no good way to call the existing funcmux APIs from drivers. Converting drivers to use a new (as yet non-existent in U-Boot) API that pulls pinmux information from DT isn't useful for Tegra, since Tegra's DT files don't contain any per-device pinmux tables, so this would simply be extra code that has no effect; doesn't actually set up the pinmux. We are left with moving the pinmux setup functionality into board files. In theory the board files could be converted later to use DT, but that would be a separate change.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 +++++ board/nvidia/seaboard/seaboard.c | 3 +++ board/nvidia/whistler/whistler.c | 1 + board/toradex/colibri_t20/colibri_t20.c | 3 +++ drivers/i2c/tegra_i2c.c | 19 ------------------- 5 files changed, 12 insertions(+), 19 deletions(-)
This should use driver model, which handles pinmux automatically if you have a pinctrl driver.
Can you define "automatic"? I don't understand exactly which benefit you're describing there.
When you probe a device, its pinmux is set up automatically, so the explicit funcmux calls can go away.
So the device here would be the pin controller device itself, not individual I2C/SPI/SD/... devices.
That's because the Tegra HW does not support[1] dynamic or partial pinmux configuration. As such, we need to program the entire pinmux at once early during boot, not piece-by-piece as the individual U-Boot devices that use individual pins are probed. This is why for example the kernel DT contains a single pinmux table that the pin controller driver sets up at boot (with identical configuration to what U-Boot sets up, so it's a no-op), rather than splitting it into per-device chunks.
Is this the big table that I see in device tree files?
pinmux@0,70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>;
pinmux_default: common { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; ...
As such, there isn't any need for, say, an I2C device probe to call into pinmux at all; the pinmux would already have been set up entirely during early boot, and hence no I2C-specific actions would be needed later.
OK. As you know I don't like this monolithic pinmux stuff - at least in early boot it is useful to enable (say) just the UART. Anyway I still think a driver is useful and will provide a better base for the future.
So I'm not sure what benefit conversion to DM pinctrl has here. Sure it means things get set up the same way as with any other pinctrl device or SoC, but this is early SoC-specific configuration, without any interaction with common or driver code besides being implemented via some standard core->board callbacks/hooks. It seems reasonable to just program the pinmux directly using SoC-specific APIs rather than having to add a layer of abstraction on top of it just so we can route it through DM. In other words, what's already done by this patch series.
Besides, I believe the programming happens before a DM pinctrl device would be ready, doesn't it, given it happens from tegra_board_early_init_f()? Or, would we be able to fully probe a DM device at that point? The UART console setup is even earlier, in SPL pre-T210, where I don't think we even have DM enabled.
DM is enabled pretty early, before board_early_init_f(). But if you hit a problem we can look at it. There is no point in setting up pinmux before driver model, since it is the drivers that use it.
Worst case, how about creating a pinctrl driver where everything happens in the probe() method? Ideally you could do the minimum necessary before relocation, and then the full table load afterwards.
[1] Yes, the HW registers can in practice be programmed bit-by-bit, simply because there are a number of registers and the SoC doesn't have a way to physically force SW to write to each of those registers. "Support" here refers to what the ASIC team will guarantee will work correctly without causing glitches or similar issues. There are a few limited exceptions, e.g. console UART muxing on its own has been at least partially thought out (although there are still conflicts in some cases on older chips), and IO controllers that may contain boot media are generally OK to mux on their own. However, for anything else, i.e. the majority of cases, the supported model is to program everything up-front in one go, and not change it later. Sticking to that general model in absolutely all cases removes special cases and simplifies the code.
Every SoC has its limitations in terms of pinmux. The point here is to have a sensible API on top of this stuff. At least then people know where to find the code, and all the pinmux hacking is in one place. Yes Tegra has some special features, but Linux has a pinctrl driver for Tegra. Can't U-Boot?
Regards, Simon
From: Stephen Warren swarren@nvidia.com
Replace all usage of funcmux APIs with the pinmux functions previously added to replace then. Delete the funcmux implementation since it's no longer used. This merges all pinmux-related logic into the pinmux code and avoids use of the funcmux "IOCTL" functions, which compile in support for all possible pinmux options even when they won't ever be used by a particular build.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/funcmux.h | 29 --- arch/arm/include/asm/arch-tegra114/funcmux.h | 21 -- arch/arm/include/asm/arch-tegra124/funcmux.h | 23 --- arch/arm/include/asm/arch-tegra20/funcmux.h | 52 ----- arch/arm/include/asm/arch-tegra210/funcmux.h | 23 --- arch/arm/include/asm/arch-tegra30/funcmux.h | 21 -- arch/arm/mach-tegra/board.c | 1 - arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/tegra114/Makefile | 2 +- arch/arm/mach-tegra/tegra114/funcmux.c | 57 ----- arch/arm/mach-tegra/tegra124/Makefile | 1 - arch/arm/mach-tegra/tegra124/funcmux.c | 71 ------- arch/arm/mach-tegra/tegra20/Makefile | 2 +- arch/arm/mach-tegra/tegra20/funcmux.c | 299 --------------------------- arch/arm/mach-tegra/tegra210/Makefile | 1 - arch/arm/mach-tegra/tegra210/funcmux.c | 39 ---- arch/arm/mach-tegra/tegra30/Makefile | 2 +- arch/arm/mach-tegra/tegra30/funcmux.c | 51 ----- board/avionic-design/common/tamonten.c | 11 +- board/compal/paz00/paz00.c | 4 +- board/compulab/trimslice/trimslice.c | 5 +- board/nvidia/harmony/harmony.c | 11 +- board/nvidia/seaboard/seaboard.c | 17 +- board/nvidia/whistler/whistler.c | 7 +- board/toradex/colibri_t20/colibri_t20.c | 14 +- drivers/mtd/nand/tegra_nand.c | 3 +- 26 files changed, 34 insertions(+), 734 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra114/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra124/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra20/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra30/funcmux.h delete mode 100644 arch/arm/mach-tegra/tegra114/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra124/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra20/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra30/funcmux.c
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h deleted file mode 100644 index d9bcf605c784..000000000000 --- a/arch/arm/include/asm/arch-tegra/funcmux.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* Tegra high-level function multiplexing */ - -#ifndef _TEGRA_FUNCMUX_H_ -#define _TEGRA_FUNCMUX_H_ - -/** - * Select a config for a particular peripheral. - * - * Each peripheral can operate through a number of configurations, - * which are sets of pins that it uses to bring out its signals. - * The basic config is 0, and higher numbers indicate different - * pinmux settings to bring the peripheral out on other pins, - * - * This function also disables tristate for the function's pins, - * so that they operate in normal mode. - * - * @param id Peripheral id - * @param config Configuration to use (FUNCMUX_...), 0 for default - * @return 0 if ok, -1 on error (e.g. incorrect id or config) - */ -int funcmux_select(enum periph_id id, int config); - -#endif /* _TEGRA_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h deleted file mode 100644 index 9c62cc39d5e0..000000000000 --- a/arch/arm/include/asm/arch-tegra114/funcmux.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* Tegra114 high-level function multiplexing */ - -#ifndef _TEGRA114_FUNCMUX_H_ -#define _TEGRA114_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART4_GMI = 0, -}; -#endif /* _TEGRA114_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h deleted file mode 100644 index df94d135f86d..000000000000 --- a/arch/arm/include/asm/arch-tegra124/funcmux.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra124 high-level function multiplexing */ - -#ifndef _TEGRA124_FUNCMUX_H_ -#define _TEGRA124_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_KBC = 0, - FUNCMUX_UART4_GPIO = 0, -}; -#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h deleted file mode 100644 index 39c2c9d825a0..000000000000 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 high-level function multiplexing */ - -#ifndef _TEGRA20_FUNCMUX_H_ -#define _TEGRA20_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_IRRX_IRTX = 0, - FUNCMUX_UART1_UAA_UAB, - FUNCMUX_UART1_GPU, - FUNCMUX_UART1_SDIO1, - FUNCMUX_UART2_UAD = 0, - FUNCMUX_UART4_GMC = 0, - - /* I2C configs */ - FUNCMUX_DVC_I2CP = 0, - FUNCMUX_I2C1_RM = 0, - FUNCMUX_I2C2_DDC = 0, - FUNCMUX_I2C2_PTA, - FUNCMUX_I2C3_DTF = 0, - - /* SDMMC configs */ - FUNCMUX_SDMMC1_SDIO1_4BIT = 0, - FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, - FUNCMUX_SDMMC3_SDB_4BIT = 0, - FUNCMUX_SDMMC3_SDB_SLXA_8BIT, - FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, - FUNCMUX_SDMMC4_ATB_GMA_4_BIT, - FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, - - /* USB configs */ - FUNCMUX_USB2_ULPI = 0, - - /* Serial Flash configs */ - FUNCMUX_SPI1_GMC_GMD = 0, - - /* NAND flags */ - FUNCMUX_NDFLASH_ATC = 0, - FUNCMUX_NDFLASH_KBC_8_BIT, -}; -#endif /* _TEGRA20_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h deleted file mode 100644 index f0851de122db..000000000000 --- a/arch/arm/include/asm/arch-tegra210/funcmux.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra210 high-level function multiplexing */ - -#ifndef _TEGRA210_FUNCMUX_H_ -#define _TEGRA210_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_UART1 = 0, - FUNCMUX_UART4_UART4 = 0, -}; -#endif /* _TEGRA210_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h deleted file mode 100644 index ae6236273fd4..000000000000 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* Tegra30 high-level function multiplexing */ - -#ifndef _TEGRA30_FUNCMUX_H_ -#define _TEGRA30_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_ULPI = 0, -}; -#endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index a5ee5a3572b1..1e7059798dcb 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -9,7 +9,6 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <mach/board.h> #include <soc/mc.h> diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index d9dfb01fdcfc..85de903559c6 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -9,7 +9,6 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index fd56b6a02f6e..2e02ae41ea4d 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -6,5 +6,5 @@
obj-$(CONFIG_SPL_BUILD) += cpu.o
-obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o pinmux.o obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c deleted file mode 100644 index e32b75c8a0b6..000000000000 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* Tegra114 high-level function multiplexing */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <mach/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART4: - switch (config) { - case FUNCMUX_UART4_GMI: - pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7, - PMUX_FUNC_UARTD); - - pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index e9554ccc966a..1050774a2f92 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o -obj-y += funcmux.o obj-y += pinmux.o obj-y += pllx.o obj-y += xusb-padctl.o diff --git a/arch/arm/mach-tegra/tegra124/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c deleted file mode 100644 index cdbe73f319a6..000000000000 --- a/arch/arm/mach-tegra/tegra124/funcmux.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra124 high-level function multiplexing */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <mach/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART4: - switch (config) { - case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ - pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); - - pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PMUX_PINGRP_PJ7); - pinmux_tristate_disable(PMUX_PINGRP_PB0); - pinmux_tristate_disable(PMUX_PINGRP_PB1); - pinmux_tristate_disable(PMUX_PINGRP_PK7); - break; - } - break; - - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_KBC: - pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, - PMUX_FUNC_UARTA); - - pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); - - pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); - pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 105f6ffa820c..768fa38aa21f 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -12,7 +12,7 @@ endif # flags for any startup files it might use. CFLAGS_warmboot_avp.o += -march=armv4t
-obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o pinmux.o obj-y += pllx.o obj-y += sku.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c deleted file mode 100644 index 348507aee2d6..000000000000 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 high-level function multiplexing */ -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <mach/pinmux.h> - -/* - * The PINMUX macro is used to set up pinmux tables. - */ -#define PINMUX(grp, mux, pupd, tri) \ - {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} - -static const struct pmux_pingrp_config disp1_default[] = { - PINMUX(LDI, DISPA, NORMAL, NORMAL), - PINMUX(LHP0, DISPA, NORMAL, NORMAL), - PINMUX(LHP1, DISPA, NORMAL, NORMAL), - PINMUX(LHP2, DISPA, NORMAL, NORMAL), - PINMUX(LHS, DISPA, NORMAL, NORMAL), - PINMUX(LM0, RSVD4, NORMAL, NORMAL), - PINMUX(LPP, DISPA, NORMAL, NORMAL), - PINMUX(LPW0, DISPA, NORMAL, NORMAL), - PINMUX(LPW2, DISPA, NORMAL, NORMAL), - PINMUX(LSC0, DISPA, NORMAL, NORMAL), - PINMUX(LSPI, DISPA, NORMAL, NORMAL), - PINMUX(LVP1, DISPA, NORMAL, NORMAL), - PINMUX(LVS, DISPA, NORMAL, NORMAL), - PINMUX(SLXD, SPDIF, NORMAL, NORMAL), -}; - - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_IRRX_IRTX: - pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_IRRX); - pinmux_tristate_disable(PMUX_PINGRP_IRTX); - break; - case FUNCMUX_UART1_UAA_UAB: - pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_UAA); - pinmux_tristate_disable(PMUX_PINGRP_UAB); - bad_config = 0; - break; - case FUNCMUX_UART1_GPU: - pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_GPU); - bad_config = 0; - break; - case FUNCMUX_UART1_SDIO1: - pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - bad_config = 0; - break; - } - if (!bad_config) { - /* - * Tegra appears to boot with function UARTA pre- - * selected on mux group SDB. If two mux groups are - * both set to the same function, it's unclear which - * group's pins drive the RX signals into the HW. - * For UARTA, SDB certainly overrides group IRTX in - * practice. To solve this, configure some alternative - * function on SDB to avoid the conflict. Also, tri- - * state the group to avoid driving any signal onto it - * until we know what's connected. - */ - pinmux_tristate_enable(PMUX_PINGRP_SDB); - pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); - } - break; - - case PERIPH_ID_UART2: - if (config == FUNCMUX_UART2_UAD) { - pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB); - pinmux_tristate_disable(PMUX_PINGRP_UAD); - } - break; - - case PERIPH_ID_UART4: - if (config == FUNCMUX_UART4_GMC) { - pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD); - pinmux_tristate_disable(PMUX_PINGRP_GMC); - } - break; - - case PERIPH_ID_DVC_I2C: - /* there is only one selection, pinmux_config is ignored */ - if (config == FUNCMUX_DVC_I2CP) { - pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C); - pinmux_tristate_disable(PMUX_PINGRP_I2CP); - } - break; - - case PERIPH_ID_I2C1: - /* support pinmux_config of 0 for now, */ - if (config == FUNCMUX_I2C1_RM) { - pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C); - pinmux_tristate_disable(PMUX_PINGRP_RM); - } - break; - case PERIPH_ID_I2C2: /* I2C2 */ - switch (config) { - case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */ - pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2); - /* PTA to HDMI */ - pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI); - pinmux_tristate_disable(PMUX_PINGRP_DDC); - break; - case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */ - pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2); - /* set DDC_SEL to RSVDx (RSVD2 works for now) */ - pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2); - pinmux_tristate_disable(PMUX_PINGRP_PTA); - bad_config = 0; - break; - } - break; - case PERIPH_ID_I2C3: /* I2C3 */ - /* support pinmux_config of 0 for now */ - if (config == FUNCMUX_I2C3_DTF) { - pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3); - pinmux_tristate_disable(PMUX_PINGRP_DTF); - } - break; - - case PERIPH_ID_SDMMC1: - if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { - pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - } - break; - - case PERIPH_ID_SDMMC2: - if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { - pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2); - pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2); - - pinmux_tristate_disable(PMUX_PINGRP_DTA); - pinmux_tristate_disable(PMUX_PINGRP_DTD); - } - break; - - case PERIPH_ID_SDMMC3: - switch (config) { - case FUNCMUX_SDMMC3_SDB_SLXA_8BIT: - pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3); - - pinmux_tristate_disable(PMUX_PINGRP_SLXA); - pinmux_tristate_disable(PMUX_PINGRP_SLXC); - pinmux_tristate_disable(PMUX_PINGRP_SLXD); - pinmux_tristate_disable(PMUX_PINGRP_SLXK); - /* fall through */ - - case FUNCMUX_SDMMC3_SDB_4BIT: - pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3); - - pinmux_tristate_disable(PMUX_PINGRP_SDB); - pinmux_tristate_disable(PMUX_PINGRP_SDC); - pinmux_tristate_disable(PMUX_PINGRP_SDD); - bad_config = 0; - break; - } - break; - - case PERIPH_ID_SDMMC4: - switch (config) { - case FUNCMUX_SDMMC4_ATC_ATD_8BIT: - pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4); - - pinmux_tristate_disable(PMUX_PINGRP_ATC); - pinmux_tristate_disable(PMUX_PINGRP_ATD); - break; - - case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT: - pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PMUX_PINGRP_GME); - /* fall through */ - - case FUNCMUX_SDMMC4_ATB_GMA_4_BIT: - pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); - - pinmux_tristate_disable(PMUX_PINGRP_ATB); - pinmux_tristate_disable(PMUX_PINGRP_GMA); - bad_config = 0; - break; - } - break; - - case PERIPH_ID_KBC: - if (config == FUNCMUX_DEFAULT) { - enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, - PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC, - PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE, - PMUX_PINGRP_KBCF}; - int i; - - for (i = 0; i < ARRAY_SIZE(grp); i++) { - pinmux_tristate_disable(grp[i]); - pinmux_set_func(grp[i], PMUX_FUNC_KBC); - pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); - } - } - break; - - case PERIPH_ID_USB2: - if (config == FUNCMUX_USB2_ULPI) { - pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI); - pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI); - pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI); - - pinmux_tristate_disable(PMUX_PINGRP_UAA); - pinmux_tristate_disable(PMUX_PINGRP_UAB); - pinmux_tristate_disable(PMUX_PINGRP_UDA); - } - break; - - case PERIPH_ID_SPI1: - if (config == FUNCMUX_SPI1_GMC_GMD) { - pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); - pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); - - pinmux_tristate_disable(PMUX_PINGRP_GMC); - pinmux_tristate_disable(PMUX_PINGRP_GMD); - } - break; - - case PERIPH_ID_NDFLASH: - switch (config) { - case FUNCMUX_NDFLASH_ATC: - pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND); - pinmux_tristate_disable(PMUX_PINGRP_ATC); - break; - case FUNCMUX_NDFLASH_KBC_8_BIT: - pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); - - pinmux_tristate_disable(PMUX_PINGRP_KBCA); - pinmux_tristate_disable(PMUX_PINGRP_KBCB); - pinmux_tristate_disable(PMUX_PINGRP_KBCC); - pinmux_tristate_disable(PMUX_PINGRP_KBCD); - pinmux_tristate_disable(PMUX_PINGRP_KBCE); - pinmux_tristate_disable(PMUX_PINGRP_KBCF); - - bad_config = 0; - break; - } - break; - case PERIPH_ID_DISP1: - if (config == FUNCMUX_DEFAULT) { - int i; - - for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) { - pinmux_set_func(i, PMUX_FUNC_DISPA); - pinmux_tristate_disable(i); - pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); - } - pinmux_config_pingrp_table(disp1_default, - ARRAY_SIZE(disp1_default)); - } - break; - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - - return 0; -} diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index dfc0a9b8e702..ba27794694e4 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -6,7 +6,6 @@ #
obj-y += clock.o -obj-y += funcmux.o obj-y += pinmux.o obj-y += pllx.o obj-y += xusb-padctl.o diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c deleted file mode 100644 index bd7c2521caf3..000000000000 --- a/arch/arm/mach-tegra/tegra210/funcmux.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra210 high-level function multiplexing */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - /* - * Add other periph IDs here as needed. - * Note that all pinmux/pads should have already - * been set up in the board pinmux table in - * pinmux-config-<board>.h for all periphs. - * Leave this in for the odd case where a mux - * needs to be changed on-the-fly. - */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index fd56b6a02f6e..2e02ae41ea4d 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -6,5 +6,5 @@
obj-$(CONFIG_SPL_BUILD) += cpu.o
-obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o pinmux.o obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c deleted file mode 100644 index c627574d61de..000000000000 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* Tegra30 high-level function multiplexing */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <mach/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_ULPI: - pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index c43a93de1fc6..162683eff9ce 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -13,7 +13,6 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/board.h> @@ -32,15 +31,15 @@ void tegra_board_early_init_f(void) gpio_request(TEGRA_GPIO(I, 4), NULL); gpio_direction_output(TEGRA_GPIO(I, 4), 1);
- funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); + tegra20_pinmux_sdmmc4_atb_gma_gme_8bit(); /* for write-protect GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* for CD GPIO PH2 */ pinmux_tristate_disable(PMUX_PINGRP_ATD); #ifdef CONFIG_TARGET_MEDCOM_WIDE - funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); + tegra20_pinmux_dvc_i2c_i2cp(); + tegra20_pinmux_i2c1_rm(); + tegra20_pinmux_i2c3_dtf(); #endif - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + tegra20_pinmux_disp1_ld0_17(); } diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 98e7cfdc352c..4727c074133b 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -9,8 +9,6 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> #include <mach/board_init.h> @@ -41,5 +39,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_UAC); /* For CD GPIO PV5 */ pinmux_tristate_disable(PMUX_PINGRP_GPV); - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + tegra20_pinmux_disp1_ld0_17(); } diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 775343e338b5..909ad2efaa48 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -10,7 +10,6 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> @@ -30,8 +29,8 @@ void tegra_board_early_init_f(void) * in the current device tree. */ pinmux_tristate_disable(PMUX_PINGRP_UAC); - funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + tegra20_pinmux_sdmmc1_sdio1_4bit(); + tegra20_pinmux_sdmmc4_atb_gma_4bit(); /* For CD GPIO PP1 */ pinmux_tristate_disable(PMUX_PINGRP_DAP3); } diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index f40b9c3b3152..5986bcbe0fb5 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -9,7 +9,6 @@ #include <lcd.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch/tegra.h> #include <asm/gpio.h> #include <mach/board_init.h> @@ -26,14 +25,14 @@ void tegra_board_early_init_f(void) { pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); pinmux_tristate_disable(PMUX_PINGRP_SDC); - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + tegra20_pinmux_usb2_ulpi(); pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); pinmux_tristate_disable(PMUX_PINGRP_CDEV2); /* USB2 PHY reset GPIO */ pinmux_tristate_disable(PMUX_PINGRP_UAC); - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); - funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); + tegra20_pinmux_ndflash_atc(); + tegra20_pinmux_sdmmc4_atb_gma_gme_8bit(); + tegra20_pinmux_sdmmc2_dta_dtd_8bit(); /* For power GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PH2 */ @@ -42,5 +41,5 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_DTB); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + tegra20_pinmux_disp1_ld0_17(); } diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index a2d6ba557b7b..651e74482531 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -11,7 +11,6 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <mach/board.h> #include <mach/board_init.h> #include <mach/pinmux.h> @@ -33,16 +32,16 @@ void tegra_board_early_init_f(void) { /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ pinmux_tristate_disable(PMUX_PINGRP_SLXK); - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); + tegra20_pinmux_ndflash_atc(); + tegra20_pinmux_sdmmc4_atb_gma_gme_8bit(); + tegra20_pinmux_sdmmc3_sdb_4bit(); /* For power GPIO PI6 */ pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PI5 */ pinmux_tristate_disable(PMUX_PINGRP_ATC); - funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + tegra20_pinmux_dvc_i2c_i2cp(); + tegra20_pinmux_i2c1_rm(); + tegra20_pinmux_i2c3_dtf(); + tegra20_pinmux_kbc_kbca_f(); + tegra20_pinmux_disp1_ld0_17(); } diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 549b67d5616f..38d94223d83f 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -11,7 +11,6 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> @@ -25,9 +24,9 @@ void tegra_spl_board_init(void)
void tegra_board_early_init_f(void) { - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); - funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); + tegra20_pinmux_sdmmc3_sdb_slxa_8bit(); + tegra20_pinmux_sdmmc4_atc_atd_8bit(); + tegra20_pinmux_dvc_i2c_i2cp(); }
int tegra_board_init(void) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index d6348f794f5e..37d1d9c71eef 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -11,7 +11,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch-tegra/tegra.h> #include <mach/board.h> #include <mach/board_init.h> @@ -40,7 +39,7 @@ void tegra_board_early_init_f(void) pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); pinmux_tristate_disable(PMUX_PINGRP_SDC); /* module internal USB bus to connect ethernet chipset */ - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + tegra20_pinmux_usb2_ulpi(); /* ULPI reference clock output */ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); pinmux_tristate_disable(PMUX_PINGRP_CDEV2); @@ -54,18 +53,17 @@ void tegra_board_early_init_f(void) pinmux_tristate_disable(PMUX_PINGRP_GPV); /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); + tegra20_pinmux_ndflash_kbc_8bit(); /* * configure pingroup ATC to something unrelated to * avoid ATC overriding KBC */ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + tegra20_pinmux_sdmmc4_atb_gma_4bit(); pinmux_tristate_disable(PMUX_PINGRP_GMB); - funcmux_select(PERIPH_ID_DVC_I2C, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C1, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_I2C3, FUNCMUX_DEFAULT); - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + tegra20_pinmux_i2c1_rm(); + tegra20_pinmux_i2c3_dtf(); + tegra20_pinmux_disp1_ld0_17(); }
int tegra_board_init(void) diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index a77db7b65dfa..391b807127c8 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011-2016 NVIDIA Corporation <www.nvidia.com> * (C) Copyright 2006 Detlev Zundel, dzu@denx.de * (C) Copyright 2006 DENX Software Engineering * @@ -12,7 +12,6 @@ #include <memalign.h> #include <nand.h> #include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/errno.h> #include <asm/gpio.h>
Hi Stephen,
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Replace all usage of funcmux APIs with the pinmux functions previously added to replace then. Delete the funcmux implementation since it's no longer used. This merges all pinmux-related logic into the pinmux code and avoids use of the funcmux "IOCTL" functions, which compile in support for all possible pinmux options even when they won't ever be used by a particular build.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/funcmux.h | 29 --- arch/arm/include/asm/arch-tegra114/funcmux.h | 21 -- arch/arm/include/asm/arch-tegra124/funcmux.h | 23 --- arch/arm/include/asm/arch-tegra20/funcmux.h | 52 ----- arch/arm/include/asm/arch-tegra210/funcmux.h | 23 --- arch/arm/include/asm/arch-tegra30/funcmux.h | 21 -- arch/arm/mach-tegra/board.c | 1 - arch/arm/mach-tegra/board2.c | 1 - arch/arm/mach-tegra/tegra114/Makefile | 2 +- arch/arm/mach-tegra/tegra114/funcmux.c | 57 ----- arch/arm/mach-tegra/tegra124/Makefile | 1 - arch/arm/mach-tegra/tegra124/funcmux.c | 71 ------- arch/arm/mach-tegra/tegra20/Makefile | 2 +- arch/arm/mach-tegra/tegra20/funcmux.c | 299 --------------------------- arch/arm/mach-tegra/tegra210/Makefile | 1 - arch/arm/mach-tegra/tegra210/funcmux.c | 39 ---- arch/arm/mach-tegra/tegra30/Makefile | 2 +- arch/arm/mach-tegra/tegra30/funcmux.c | 51 ----- board/avionic-design/common/tamonten.c | 11 +- board/compal/paz00/paz00.c | 4 +- board/compulab/trimslice/trimslice.c | 5 +- board/nvidia/harmony/harmony.c | 11 +- board/nvidia/seaboard/seaboard.c | 17 +- board/nvidia/whistler/whistler.c | 7 +- board/toradex/colibri_t20/colibri_t20.c | 14 +- drivers/mtd/nand/tegra_nand.c | 3 +- 26 files changed, 34 insertions(+), 734 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra114/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra124/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra20/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h delete mode 100644 arch/arm/include/asm/arch-tegra30/funcmux.h delete mode 100644 arch/arm/mach-tegra/tegra114/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra124/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra20/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c delete mode 100644 arch/arm/mach-tegra/tegra30/funcmux.c
The concept is fine, but this should use a pinctrl drive.r
- Simon
From: Stephen Warren swarren@nvidia.com
The only use of the BIT was to print a message indicating whether the system booted via cold boot or USB ReCovery Mode (RCM). If that is worth doing for some boards, it's worth doing for all, so make the core Tegra code do that.
This will allow the definitions related to the BIT to be removed from global visibility, and isolated into Tegra-specific code. This also avoids the need to implement arch_misc_init() for a couple of boards.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 4 ++++ board/toradex/apalis_t30/apalis_t30.c | 10 ---------- board/toradex/colibri_t20/colibri_t20.c | 5 ----- board/toradex/colibri_t30/colibri_t30.c | 10 ---------- include/configs/apalis_t30.h | 2 -- include/configs/colibri_t30.h | 2 -- 6 files changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 85de903559c6..cc12073d8ada 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -61,6 +61,10 @@ int checkboard(void) printf(", ID: %d\n", board_id); printf("\n");
+ if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == + NVBOOTTYPE_RECOVERY) + printf("Booted via USB recovery mode\n"); + return 0; } #endif /* CONFIG_DISPLAY_BOARDINFO */ diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 3db9308323fd..9670018e1b7f 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -11,7 +11,6 @@ #include <i2c.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> -#include <asm/io.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> @@ -21,15 +20,6 @@ #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3
-int arch_misc_init(void) -{ - if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == - NVBOOTTYPE_RECOVERY) - printf("USB recovery mode\n"); - - return 0; -} - void tegra_spl_board_init(void) { tegra30_pinmux_uarta_ulpi(); diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 37d1d9c71eef..a7f15472536c 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -9,7 +9,6 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <i2c.h> #include <asm/gpio.h> -#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/tegra.h> #include <mach/board.h> @@ -108,9 +107,5 @@ int arch_misc_init(void) /* make sure SODIMM pin 87 nRESET_OUT is released properly */ pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
- if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == - NVBOOTTYPE_RECOVERY) - printf("USB recovery mode\n"); - return 0; } diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 1860ac4fec4e..8188b2fb64b1 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -10,22 +10,12 @@ #include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/io.h> #include <asm/arch-tegra/tegra.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> #include "pinmux-config-colibri_t30.h"
-int arch_misc_init(void) -{ - if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == - NVBOOTTYPE_RECOVERY) - printf("USB recovery mode\n"); - - return 0; -} - void tegra_spl_board_init(void) { tegra30_pinmux_uarta_ulpi(); diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index d104aa9ccae9..2d2b6af8fb2f 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -14,8 +14,6 @@
#include "tegra30-common.h"
-#define CONFIG_ARCH_MISC_INIT - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30"
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index e5aaab742388..2af03d10c429 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -14,8 +14,6 @@
#include "tegra30-common.h"
-#define CONFIG_ARCH_MISC_INIT - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
The only use of the BIT was to print a message indicating whether the system booted via cold boot or USB ReCovery Mode (RCM). If that is worth doing for some boards, it's worth doing for all, so make the core Tegra code do that.
This will allow the definitions related to the BIT to be removed from global visibility, and isolated into Tegra-specific code. This also avoids the need to implement arch_misc_init() for a couple of boards.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/board2.c | 4 ++++ board/toradex/apalis_t30/apalis_t30.c | 10 ---------- board/toradex/colibri_t20/colibri_t20.c | 5 ----- board/toradex/colibri_t30/colibri_t30.c | 10 ---------- include/configs/apalis_t30.h | 2 -- include/configs/colibri_t30.h | 2 -- 6 files changed, 4 insertions(+), 29 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Tegra board files currently include many headers they don't need. Remove the unused include statements.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/avionic-design/common/tamonten.c | 5 ----- board/compal/paz00/paz00.c | 3 --- board/compulab/trimslice/trimslice.c | 4 ---- board/nvidia/harmony/harmony.c | 5 ----- board/nvidia/jetson-tk1/jetson-tk1.c | 1 - board/nvidia/nyan-big/nyan-big.c | 3 --- board/nvidia/seaboard/seaboard.c | 3 --- board/nvidia/venice2/as3722_init.c | 1 - board/nvidia/whistler/whistler.c | 3 --- board/toradex/apalis_t30/apalis_t30.c | 1 - board/toradex/colibri_t20/colibri_t20.c | 2 -- board/toradex/colibri_t30/colibri_t30.c | 2 -- drivers/gpio/tegra_gpio.c | 1 - 13 files changed, 34 deletions(-)
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 162683eff9ce..1d4cf09a3138 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -8,13 +8,8 @@ */
#include <common.h> -#include <ns16550.h> #include <dt-bindings/gpio/tegra-gpio.h> -#include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch/tegra.h> -#include <asm/arch-tegra/clk_rst.h> #include <mach/board.h> #include <mach/board_init.h> #include <mach/pinmux.h> diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 4727c074133b..d0d1b464cd6e 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -8,9 +8,6 @@ */
#include <common.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 909ad2efaa48..aa28ccd7ede3 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -7,10 +7,6 @@
#include <common.h> #include <i2c.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/clock.h> -#include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 5986bcbe0fb5..4597a7606a4e 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -6,11 +6,6 @@ */
#include <common.h> -#include <lcd.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/tegra.h> -#include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index cb2f8abf47bf..a5e958235355 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -12,7 +12,6 @@ #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> -#include <mach/spl_uart.h> #include <mach/tegra_gpio.h> #include "pinmux-config-jetson-tk1.h"
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 762dc955d7c1..c38ae8c9a02d 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -9,11 +9,8 @@ #include <errno.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> -#include <power/pmic.h> #include <asm/gpio.h> -#include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 651e74482531..87b5f722fa9c 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -8,9 +8,6 @@ #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/clock.h> #include <mach/board.h> #include <mach/board_init.h> #include <mach/pinmux.h> diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 86b164db3be1..e2d52a6e9dbb 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -6,7 +6,6 @@ */
#include <common.h> -#include <asm/io.h> #include <mach/tegra_i2c.h> #include "as3722_init.h"
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 38d94223d83f..a6fdaa920d47 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -8,9 +8,6 @@ #include <common.h> #include <dm.h> #include <i2c.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/clock.h> #include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 9670018e1b7f..ad0038fea719 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -9,7 +9,6 @@ #include <common.h> #include <dm.h> #include <i2c.h> -#include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <mach/board_init.h> #include <mach/pinmux.h> diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index a7f15472536c..f753a781aedb 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -9,8 +9,6 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <i2c.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/tegra.h> #include <mach/board.h> #include <mach/board_init.h> #include <mach/pinmux.h> diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 8188b2fb64b1..e3b1f2bcf489 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -7,10 +7,8 @@ */
#include <common.h> -#include <i2c.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <asm/gpio.h> -#include <asm/arch-tegra/tegra.h> #include <mach/board_init.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index a3b6878e47bd..152c303c4acf 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -18,7 +18,6 @@ #include <fdtdec.h> #include <asm/io.h> #include <asm/bitops.h> -#include <asm/arch/tegra.h> #include <asm/gpio.h> #include <dm/device-internal.h> #include <dt-bindings/gpio/gpio.h>
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra board files currently include many headers they don't need. Remove the unused include statements.
Signed-off-by: Stephen Warren swarren@nvidia.com
board/avionic-design/common/tamonten.c | 5 ----- board/compal/paz00/paz00.c | 3 --- board/compulab/trimslice/trimslice.c | 4 ---- board/nvidia/harmony/harmony.c | 5 ----- board/nvidia/jetson-tk1/jetson-tk1.c | 1 - board/nvidia/nyan-big/nyan-big.c | 3 --- board/nvidia/seaboard/seaboard.c | 3 --- board/nvidia/venice2/as3722_init.c | 1 - board/nvidia/whistler/whistler.c | 3 --- board/toradex/apalis_t30/apalis_t30.c | 1 - board/toradex/colibri_t20/colibri_t20.c | 2 -- board/toradex/colibri_t30/colibri_t30.c | 2 -- drivers/gpio/tegra_gpio.c | 1 - 13 files changed, 34 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
Most of arch/arm/include/asm/arch-tegra*/tegra.h is only used by code in arch/arm/mach-tegra, so move the header files there to avoid polluting the global include path. While moving, unify the per-SoC files into one using a couple of simple ifdefs; this avoids having so many headers.
Many source files relied on <common.h> including the board config.h file, which in turned used to include tegra.h. Now that we've removed this, we need to include tegra.h from those files, hence this patch adds a few new include statements.
A few defines from tegra.h are used by code outside mach-tegra. These are dealt with as follows:
- A few drivers program clock registers directly and hence use NV_PA_CLK_RST_BASE to locate the registers. Move this into clk_rst.h; that makes sense since it defines the register layout and may as well define the address too. Later patches will hopefully clean up the Tegra clock driver and hide this information too.
- Various other definitions are used by the board config headers and/or core U-Boot code (e.g. ARMv8 boot assembly). These can't include SoC-specific headers from <mach/>. Hence, move those definitions into tegra-common.h so they're generally available.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/include/asm/arch-tegra/clk_rst.h | 2 ++ arch/arm/include/asm/arch-tegra114/tegra.h | 25 -------------- arch/arm/include/asm/arch-tegra124/tegra.h | 27 --------------- arch/arm/include/asm/arch-tegra20/tegra.h | 20 ----------- arch/arm/include/asm/arch-tegra210/tegra.h | 29 ---------------- arch/arm/include/asm/arch-tegra30/tegra.h | 19 ----------- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/clock.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 2 +- arch/arm/mach-tegra/cpu.c | 2 +- arch/arm/mach-tegra/gpu.c | 2 +- arch/arm/mach-tegra/i2c_early.c | 1 + arch/arm/mach-tegra/lowlevel_init.S | 3 +- arch/arm/mach-tegra/pinmux-common.c | 1 + arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/spl_uart.c | 1 + .../{include/asm/arch-tegra => mach-tegra}/tegra.h | 39 ++++++++++++++++++---- arch/arm/mach-tegra/tegra114/clock.c | 2 +- arch/arm/mach-tegra/tegra114/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/psci.c | 1 + arch/arm/mach-tegra/tegra20/clock.c | 2 +- arch/arm/mach-tegra/tegra20/cpu.c | 2 +- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 2 +- arch/arm/mach-tegra/tegra20/sku.c | 1 + arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 2 +- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 3 +- arch/arm/mach-tegra/tegra30/clock.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- drivers/gpio/tegra_gpio.c | 2 ++ drivers/pci/pci_tegra.c | 1 + include/configs/tegra-common.h | 14 ++++++-- 39 files changed, 81 insertions(+), 152 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra124/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra20/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra30/tegra.h rename arch/arm/{include/asm/arch-tegra => mach-tegra}/tegra.h (59%)
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 304e1148cdcd..619793bfbef8 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -8,6 +8,8 @@ #ifndef _TEGRA_CLK_RST_H_ #define _TEGRA_CLK_RST_H_
+#define NV_PA_CLK_RST_BASE 0x60006000 + /* PLL registers - there are several PLLs in the clock controller */ struct clk_pll { uint pll_base; /* the control register */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h deleted file mode 100644 index f8407d178bce..000000000000 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA114_H_ -#define _TEGRA114_H_ - -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA114_H */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h deleted file mode 100644 index f009925611c6..000000000000 --- a/arch/arm/include/asm/arch-tegra124/tegra.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_H_ -#define _TEGRA124_H_ - -#define NV_PA_SDRAM_BASE 0x80000000 -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ -#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 - -#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h deleted file mode 100644 index 1cea245e4171..000000000000 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2010-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_H_ -#define _TEGRA20_H_ - -#define NV_PA_SDRAM_BASE 0x00000000 -#define NV_PA_MC_BASE 0x7000F000 - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 2 - -#endif /* TEGRA20_H */ diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h deleted file mode 100644 index 17b9f6af3679..000000000000 --- a/arch/arm/include/asm/arch-tegra210/tegra.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2013-2016 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA210_TEGRA_H_ -#define _TEGRA210_TEGRA_H_ - -#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ -#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ -#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ -#define NV_PA_SDRAM_BASE 0x80000000 - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 - -#endif /* _TEGRA210_TEGRA_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h deleted file mode 100644 index 28f9741a1d76..000000000000 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _TEGRA30_H_ -#define _TEGRA30_H_ - -#define NV_PA_MC_BASE 0x7000F000 -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA30_H */ diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 3406e0efe4cb..fba8a6417135 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -11,11 +11,11 @@ #include <linux/bug.h> #include <asm/io.h> #include <asm/arch-tegra/clock.h> -#include <asm/arch-tegra/tegra.h> #include <soc/mc.h> #include "cpu.h" #include "pmc.h" #include "scu.h" +#include "tegra.h"
#ifndef CONFIG_ARM64 static void enable_scu(void) diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 1e7059798dcb..2f8b79b63d83 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -9,10 +9,10 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <mach/board.h> #include <soc/mc.h> #include "pmc.h" +#include "tegra.h"
void save_boot_params_ret(void);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index cc12073d8ada..3a5ba94c19c9 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -9,7 +9,6 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" #include <mach/board.h> @@ -22,6 +21,7 @@ #include "cpu.h" #include "gpu.h" #include "pmc.h" +#include "tegra.h" #ifdef CONFIG_TEGRA20_CLOCK_SCALING #include "tegra20/emc.h" #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 1a6fc0151a60..e7f6aa7e04cc 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -10,11 +10,11 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> #include "pmc.h" +#include "tegra.h"
/* * This is our record of the current clock rate of each clock. We don't diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index d5205c39ab79..7ceaa441cc49 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -26,8 +26,8 @@ */
#include <common.h> -#include <asm/arch/tegra.h> #include "pmc.h" +#include "tegra.h"
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index eb9222b2f23d..aa72cc297c84 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -7,12 +7,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "cpu.h" #include "pllx.h" #include "pmc.h" #include "scu.h" +#include "tegra.h"
static inline void pllx_set_iddq(void) { diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 36204f54e4c9..1410be04bb86 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -9,9 +9,9 @@ #include <common.h> #include <fdt_support.h> #include <asm/io.h> -#include <asm/arch/tegra.h> #include <soc/mc.h> #include "gpu.h" +#include "tegra.h"
static bool _configured;
diff --git a/arch/arm/mach-tegra/i2c_early.c b/arch/arm/mach-tegra/i2c_early.c index dcdd86cef71e..141867043b56 100644 --- a/arch/arm/mach-tegra/i2c_early.c +++ b/arch/arm/mach-tegra/i2c_early.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <mach/tegra_i2c.h> +#include "tegra.h" #include "../../../drivers/i2c/tegra_i2c_priv.h"
void tegra_i2c_ll_write_addr(uint addr, uint config) diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index 1273f94aa38e..912cf85bff1c 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -1,7 +1,7 @@ /* * SoC-specific setup info * - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -9,6 +9,7 @@
#include <config.h> #include <linux/linkage.h> +#include "tegra.h"
#ifdef CONFIG_ARM64 .align 5 diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index faa406e077a4..b894c04c1db1 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/io.h> #include <mach/pinmux.h> +#include "tegra.h"
/* return 1 if a pingrp is in range */ #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 04205bb10cbb..17357e9f1b7f 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -9,9 +9,9 @@
#include <asm/io.h> #include <asm/types.h> -#include <asm/arch/tegra.h> #include <mach/powergate.h> #include <soc/flow.h> +#include "tegra.h"
#define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 353a6ddfb6c2..d5e709406e8b 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -12,12 +12,12 @@
#include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/spl.h> #include <mach/board.h> #include <mach/board_init.h> #include "apb_misc.h" #include "cpu.h" +#include "tegra.h"
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */ U_BOOT_DEVICE(tegra_gpios) = { diff --git a/arch/arm/mach-tegra/spl_uart.c b/arch/arm/mach-tegra/spl_uart.c index 2c1d237174fd..163e6443e821 100644 --- a/arch/arm/mach-tegra/spl_uart.c +++ b/arch/arm/mach-tegra/spl_uart.c @@ -9,6 +9,7 @@ #include <ns16550.h> #include <asm/arch/clock.h> #include <mach/spl_uart.h> +#include "tegra.h"
static struct ns16550_platdata ns16550_com1_pdata = { .reg_shift = 2, diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/mach-tegra/tegra.h similarity index 59% rename from arch/arm/include/asm/arch-tegra/tegra.h rename to arch/arm/mach-tegra/tegra.h index 71c9374c7ae0..0e8d8a22cd55 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/mach-tegra/tegra.h @@ -5,17 +5,15 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_H_ -#define _TEGRA_H_ +#ifndef _TEGRA_TEGRA_H +#define _TEGRA_TEGRA_H
/* AP base physical address of internal SRAM */ #define NV_PA_BASE_SRAM 0x40000000 #define NV_PA_ARM_PERIPHBASE 0x50040000 #define NV_PA_PG_UP_BASE 0x60000000 -#define NV_PA_TMRUS_BASE 0x60005010 -#define NV_PA_CLK_RST_BASE 0x60006000 #define NV_PA_FLOW_BASE 0x60007000 -#define NV_PA_GPIO_BASE 0x6000D000 +#define NV_PA_AHB_BASE 0x6000C000 #define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) @@ -32,6 +30,12 @@ #else #define NV_PA_CSITE_BASE 0x70800000 #endif +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) +#define NV_PA_MC_BASE 0x7000f000 +#else +#define NV_PA_MC_BASE 0x70019000 +#endif +#define NV_PA_TSC_BASE 0x700f0000
#define PG_UP_TAG_0 0x0 #define PG_UP_TAG_AVP 0xAAAAAAAA @@ -39,11 +43,34 @@ /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define NV_WB_RUN_ADDRESS 0x40020000
+#if defined(CONFIG_TEGRA20) +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ +#elif defined(CONFIG_TEGRA30) +#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ +#elif defined(CONFIG_TEGRA114) +#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ +#elif defined(CONFIG_TEGRA124) +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ +#elif defined(CONFIG_TEGRA210) +#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ +#endif + #define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */ #define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */ +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ +#else +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ +#endif + +#if defined(CONFIG_TEGRA20) +#define MAX_NUM_CPU 2 +#else +#define MAX_NUM_CPU 4 +#endif
#define PRM_RSTCTRL NV_PA_PMC_BASE
-#endif /* TEGRA_H */ +#endif diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 155353d44c52..39d8523ab1f0 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -10,11 +10,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> #include "../sysctr.h" +#include "../tegra.h"
/* * Clock types that we can use as a source. The Tegra114 has muxes for the diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 423ace4a2ebd..388c03002b88 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -8,12 +8,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h"
/* Tegra114-specific CPU init code */ static void enable_cpu_power_rail(void) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index dc060a6db569..692b82f336c0 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -10,11 +10,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> #include "../sysctr.h" +#include "../tegra.h"
/* * Clock types that we can use as a source. The Tegra124 has muxes for the diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index c01d36c11c4b..aa4b5581dd75 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -8,12 +8,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h"
/* Tegra124-specific CPU init code */
diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index 27f9e60e1372..ea3966a99c94 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -13,6 +13,7 @@ #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h"
static void park_cpu(void) { diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 0ff538830abd..182ab6f50db8 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -12,10 +12,10 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include "../tegra.h"
/* * Clock types that we can use as a source. The Tegra20 has muxes for the diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 10205dca5e53..d094487fcfa3 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -6,9 +6,9 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/tegra.h> #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h"
static void enable_cpu_power_rail(void) { diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index fa694d1fda84..c089e7a8ed0d 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -9,9 +9,9 @@ #include <fdtdec.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include "../apb_misc.h" #include "../emc.h" +#include "../tegra.h" #include "emc_priv.h" #include "sku.h"
diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index ac24c6b3ac1d..4b4d7bebc0d2 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -9,8 +9,8 @@ #include <i2c.h> #include <tps6586x.h> #include <asm/io.h> -#include <asm/arch/tegra.h> #include <mach/tegra_i2c.h> +#include "../tegra.h" #include "sku.h"
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ diff --git a/arch/arm/mach-tegra/tegra20/sku.c b/arch/arm/mach-tegra/tegra20/sku.c index 56c9e97e2454..9ddf4436de08 100644 --- a/arch/arm/mach-tegra/tegra20/sku.c +++ b/arch/arm/mach-tegra/tegra20/sku.c @@ -6,6 +6,7 @@
#include <common.h> #include <asm/io.h> +#include "../tegra.h" #include "fuse.h"
/* These are the available SKUs (product types) for Tegra20 */ diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 26db8a1477a5..1f3f3843b438 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -9,11 +9,11 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "../apb_misc.h" #include "../emc.h" #include "../pmc.h" +#include "../tegra.h" #include "crypto.h" #include "emc_priv.h" #include "fuse.h" diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 07aa542c11b0..82722b5b52ec 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -8,12 +8,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <soc/flow.h> #include "../apb_misc.h" #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h" #include "warmboot.h" #include "warmboot_avp.h"
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index d2d517b2c711..830ff6d267c6 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -11,11 +11,11 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> #include "../sysctr.h" +#include "../tegra.h"
/* * Clock types that we can use as a source. The Tegra210 has muxes for the diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 9ec93e7c4c4c..44523c5b385b 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -12,6 +12,7 @@ #include "../xusb-padctl-common.h"
#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 98289b8ac7a7..dca6d1118b3b 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -11,10 +11,10 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include "../tegra.h"
/* * Clock types that we can use as a source. The Tegra30 has muxes for the diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index f7cffb7d5106..ac234da59d50 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -7,12 +7,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <mach/tegra_i2c.h> #include <soc/flow.h> #include "../cpu.h" #include "../pmc.h" +#include "../tegra.h"
/* Tegra30-specific CPU init code */
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 152c303c4acf..894a12770cc0 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -24,6 +24,8 @@ #include <mach/tegra_gpio.h> #include "tegra_gpio_priv.h"
+#define NV_PA_GPIO_BASE 0x6000D000 + DECLARE_GLOBAL_DATA_PTR;
static const int CONFIG_SFIO = 0; diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 392ebde1e05c..f19e213bd7bd 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -23,6 +23,7 @@ #include <asm/gpio.h>
#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h>
#include <mach/powergate.h> #include <mach/xusb-padctl.h> diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index b6506e2fb3df..332382aec87d 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -10,14 +10,24 @@ #include <linux/sizes.h> #include <linux/stringify.h>
+#define NV_PA_TMRUS_BASE 0x60005010 +#ifdef CONFIG_TEGRA20 +#define NV_PA_SDRAM_BASE 0x00000000 +#else +#define NV_PA_SDRAM_BASE 0x80000000 +#endif + +#ifdef CONFIG_ARM64 +#define GICD_BASE 0x50041000 +#define GICC_BASE 0x50042000 +#endif + /* * High Level Configuration Options */ #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
-#include <asm/arch/tegra.h> /* get chip and board defs */ - /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ #ifndef CONFIG_ARM64 #define CONFIG_SYS_TIMER_RATE 1000000
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Most of arch/arm/include/asm/arch-tegra*/tegra.h is only used by code in arch/arm/mach-tegra, so move the header files there to avoid polluting the global include path. While moving, unify the per-SoC files into one using a couple of simple ifdefs; this avoids having so many headers.
Many source files relied on <common.h> including the board config.h file, which in turned used to include tegra.h. Now that we've removed this, we need to include tegra.h from those files, hence this patch adds a few new include statements.
A few defines from tegra.h are used by code outside mach-tegra. These are dealt with as follows:
- A few drivers program clock registers directly and hence use
NV_PA_CLK_RST_BASE to locate the registers. Move this into clk_rst.h; that makes sense since it defines the register layout and may as well define the address too. Later patches will hopefully clean up the Tegra clock driver and hide this information too.
- Various other definitions are used by the board config headers and/or
core U-Boot code (e.g. ARMv8 boot assembly). These can't include SoC-specific headers from <mach/>. Hence, move those definitions into tegra-common.h so they're generally available.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/include/asm/arch-tegra/clk_rst.h | 2 ++ arch/arm/include/asm/arch-tegra114/tegra.h | 25 -------------- arch/arm/include/asm/arch-tegra124/tegra.h | 27 --------------- arch/arm/include/asm/arch-tegra20/tegra.h | 20 ----------- arch/arm/include/asm/arch-tegra210/tegra.h | 29 ---------------- arch/arm/include/asm/arch-tegra30/tegra.h | 19 ----------- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/clock.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 2 +- arch/arm/mach-tegra/cpu.c | 2 +- arch/arm/mach-tegra/gpu.c | 2 +- arch/arm/mach-tegra/i2c_early.c | 1 + arch/arm/mach-tegra/lowlevel_init.S | 3 +- arch/arm/mach-tegra/pinmux-common.c | 1 + arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/spl_uart.c | 1 + .../{include/asm/arch-tegra => mach-tegra}/tegra.h | 39 ++++++++++++++++++---- arch/arm/mach-tegra/tegra114/clock.c | 2 +- arch/arm/mach-tegra/tegra114/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- arch/arm/mach-tegra/tegra124/cpu.c | 2 +- arch/arm/mach-tegra/tegra124/psci.c | 1 + arch/arm/mach-tegra/tegra20/clock.c | 2 +- arch/arm/mach-tegra/tegra20/cpu.c | 2 +- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 2 +- arch/arm/mach-tegra/tegra20/sku.c | 1 + arch/arm/mach-tegra/tegra20/warmboot.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 2 +- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 3 +- arch/arm/mach-tegra/tegra30/clock.c | 2 +- arch/arm/mach-tegra/tegra30/cpu.c | 2 +- drivers/gpio/tegra_gpio.c | 2 ++ drivers/pci/pci_tegra.c | 1 + include/configs/tegra-common.h | 14 ++++++-- 39 files changed, 81 insertions(+), 152 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra114/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra124/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra20/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h delete mode 100644 arch/arm/include/asm/arch-tegra30/tegra.h rename arch/arm/{include/asm/arch-tegra => mach-tegra}/tegra.h (59%)
Reviewed-by: Simon Glass sjg@chromium.org
From: Stephen Warren swarren@nvidia.com
These are the last files in arch/arm/include/asm/arch-tegra*. Move them into arch/arm/mach-tegra. The Tegra clock API currently exposes a lot of internal implementation details, which are unfortunately relied upon throughout the code base. Consequently, the headers are moved to <mach/> rather than being hidden out of the global include path. This needs cleanup/refactoring, especially since the current state cannot support the next chip at all. However, this cleanup series is already rather long, and the work to cleanup the clock API rather involved, so I'll do that later.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 4 ++-- arch/arm/mach-tegra/clock.c | 4 ++-- arch/arm/mach-tegra/cpu.c | 4 ++-- .../asm/arch-tegra => mach-tegra/include/mach}/clk_rst.h | 6 +++--- .../clock.h => mach-tegra/include/mach/clock_common.h} | 8 ++++---- arch/arm/mach-tegra/include/mach/powergate.h | 2 +- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/spl_uart.c | 2 +- arch/arm/mach-tegra/tegra114/clock.c | 4 ++-- arch/arm/mach-tegra/tegra114/cpu.c | 4 ++-- .../tegra114/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra114 => mach-tegra/tegra114/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra114/pllx.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 4 ++-- .../tegra124/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra124 => mach-tegra/tegra124/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra124/pllx.c | 2 +- arch/arm/mach-tegra/tegra20/clock.c | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 2 +- .../tegra20/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra20 => mach-tegra/tegra20/include/mach}/clock.h | 5 +++-- arch/arm/mach-tegra/tegra20/pllx.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot.c | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 4 ++-- arch/arm/mach-tegra/tegra210/clock.c | 4 ++-- .../tegra210/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra210 => mach-tegra/tegra210/include/mach}/clock.h | 8 ++++---- arch/arm/mach-tegra/tegra210/pllx.c | 2 +- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 8 +++----- arch/arm/mach-tegra/tegra30/clock.c | 4 ++-- arch/arm/mach-tegra/tegra30/cpu.c | 4 ++-- .../tegra30/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra30 => mach-tegra/tegra30/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra30/pllx.c | 2 +- arch/arm/mach-tegra/xusb-padctl-common.c | 6 ++---- board/nvidia/jetson-tk1/jetson-tk1.c | 3 +-- board/nvidia/nyan-big/nyan-big.c | 2 +- drivers/i2c/tegra_i2c.c | 4 ++-- drivers/input/tegra-kbc.c | 2 +- drivers/mmc/tegra_mmc.c | 4 ++-- drivers/mtd/nand/tegra_nand.c | 4 ++-- drivers/pci/pci_tegra.c | 5 ++--- drivers/pwm/tegra_pwm.c | 2 +- drivers/spi/tegra114_spi.c | 6 +++--- drivers/spi/tegra20_sflash.c | 4 ++-- drivers/spi/tegra20_slink.c | 6 +++--- drivers/spi/tegra210_qspi.c | 6 +++--- drivers/usb/host/ehci-tegra.c | 5 ++--- drivers/video/tegra.c | 2 +- drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/sor.c | 2 +- 54 files changed, 119 insertions(+), 125 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/clk_rst.h (99%) rename arch/arm/{include/asm/arch-tegra/clock.h => mach-tegra/include/mach/clock_common.h} (99%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock.h (61%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock.h (85%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock-tables.h (95%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock.h (77%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock.h (78%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock.h (58%)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index fba8a6417135..5883798bc4bd 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -10,7 +10,7 @@ #include <common.h> #include <linux/bug.h> #include <asm/io.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include <soc/mc.h> #include "cpu.h" #include "pmc.h" diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 2f8b79b63d83..7d2579671855 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -8,8 +8,8 @@ #include <common.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/clock.h> #include <mach/board.h> +#include <mach/clock.h> #include <soc/mc.h> #include "pmc.h" #include "tegra.h" diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 3a5ba94c19c9..b2ab301897a0 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -8,11 +8,11 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include "../../../drivers/usb/host/ehci-tegra-priv.h" #include <mach/board.h> #include <mach/board_init.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #ifdef CONFIG_TEGRA_MMC #include <mach/tegra_mmc.h> #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index e7f6aa7e04cc..9fd6802598f2 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -9,10 +9,10 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "pmc.h" #include "tegra.h"
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index aa72cc297c84..40e32cfbc946 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -6,8 +6,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "cpu.h" #include "pllx.h" #include "pmc.h" diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/mach-tegra/include/mach/clk_rst.h similarity index 99% rename from arch/arm/include/asm/arch-tegra/clk_rst.h rename to arch/arm/mach-tegra/include/mach/clk_rst.h index 619793bfbef8..47ae5e8301cc 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/mach-tegra/include/mach/clk_rst.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _TEGRA_CLK_RST_H_ -#define _TEGRA_CLK_RST_H_ +#ifndef _MACH_CLK_RST_H +#define _MACH_CLK_RST_H
#define NV_PA_CLK_RST_BASE 0x60006000
@@ -386,4 +386,4 @@ enum { /* CLK_RST_PLLD_MISC */ #define PLLD_CLKENABLE 30
-#endif /* _TEGRA_CLK_RST_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/mach-tegra/include/mach/clock_common.h similarity index 99% rename from arch/arm/include/asm/arch-tegra/clock.h rename to arch/arm/mach-tegra/include/mach/clock_common.h index a20832b7f35f..11e2a81ebde0 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/mach-tegra/include/mach/clock_common.h @@ -7,8 +7,8 @@
/* Tegra clock control functions */
-#ifndef _TEGRA_CLOCK_H_ -#define _TEGRA_CLOCK_H_ +#ifndef _MACH_CLOCK_COMMON_H +#define _MACH_CLOCK_COMMON_H
/* Set of oscillator frequencies supported in the internal API. */ enum clock_osc_freq { @@ -38,7 +38,7 @@ enum { MASK_BITS_31_28, };
-#include <asm/arch/clock-tables.h> +#include <mach/clock-tables.h> /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300
@@ -370,4 +370,4 @@ extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; */ int clock_external_output(int clk_id);
-#endif /* _TEGRA_CLOCK_H_ */ +#endif diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h index 3ac9c9b092b1..297cf2b43cc8 100644 --- a/arch/arm/mach-tegra/include/mach/powergate.h +++ b/arch/arm/mach-tegra/include/mach/powergate.h @@ -7,7 +7,7 @@ #ifndef _MACH_POWERGATE_H #define _MACH_POWERGATE_H
-#include <asm/arch/clock.h> +#include <mach/clock.h>
enum tegra_powergate { TEGRA_POWERGATE_CPU, diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index d5e709406e8b..f6c3b4aeeaaf 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -11,10 +11,10 @@ #include <spl.h>
#include <asm/io.h> -#include <asm/arch/clock.h> #include <asm/spl.h> #include <mach/board.h> #include <mach/board_init.h> +#include <mach/clock.h> #include "apb_misc.h" #include "cpu.h" #include "tegra.h" diff --git a/arch/arm/mach-tegra/spl_uart.c b/arch/arm/mach-tegra/spl_uart.c index 163e6443e821..9ae93587e075 100644 --- a/arch/arm/mach-tegra/spl_uart.c +++ b/arch/arm/mach-tegra/spl_uart.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <ns16550.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <mach/spl_uart.h> #include "tegra.h"
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 39d8523ab1f0..0a93c40663a0 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -9,10 +9,10 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../sysctr.h" #include "../tegra.h"
diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 388c03002b88..9f9883e50bda 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -7,8 +7,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/mach-tegra/tegra114/include/mach/clock-tables.h similarity index 97% rename from arch/arm/include/asm/arch-tegra114/clock-tables.h rename to arch/arm/mach-tegra/tegra114/include/mach/clock-tables.h index d4511817fa3b..c12770c37d8c 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/mach-tegra/tegra114/include/mach/clock-tables.h @@ -1,13 +1,13 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
/* Tegra114 clock PLL tables */
-#ifndef _TEGRA114_CLOCK_TABLES_H_ -#define _TEGRA114_CLOCK_TABLES_H_ +#ifndef _TEGRA114_CLOCK_TABLES_H +#define _TEGRA114_CLOCK_TABLES_H
/* The PLLs supported by the hardware */ enum clock_id { @@ -390,4 +390,4 @@ enum periphc_internal_id { #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ (id) < PERIPH_ID_COUNT)
-#endif /* _TEGRA114_CLOCK_TABLES_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/mach-tegra/tegra114/include/mach/clock.h similarity index 61% rename from arch/arm/include/asm/arch-tegra114/clock.h rename to arch/arm/mach-tegra/tegra114/include/mach/clock.h index 4d58bf184218..1f3f2ebc7aae 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/mach-tegra/tegra114/include/mach/clock.h @@ -1,15 +1,15 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
/* Tegra114 clock control functions */
-#ifndef _TEGRA114_CLOCK_H_ -#define _TEGRA114_CLOCK_H_ +#ifndef _TEGRA114_CLOCK_H +#define _TEGRA114_CLOCK_H
-#include <asm/arch-tegra/clock.h> +#include <mach/clock_common.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 28 @@ -18,4 +18,4 @@ /* CLK_RST_CONTROLLER_PLLC_MISC_0 */ #define PLLC_IDDQ (1 << 26)
-#endif /* _TEGRA114_CLOCK_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra114/pllx.c b/arch/arm/mach-tegra/tegra114/pllx.c index 4c4e8f74f973..362693408d76 100644 --- a/arch/arm/mach-tegra/tegra114/pllx.c +++ b/arch/arm/mach-tegra/tegra114/pllx.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include "../cpu.h" #include "../pllx.h"
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 692b82f336c0..2fc75da7f28a 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -9,10 +9,10 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../sysctr.h" #include "../tegra.h"
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index aa4b5581dd75..bd787ccc3d11 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -7,8 +7,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include <soc/flow.h> #include "../cpu.h" diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/mach-tegra/tegra124/include/mach/clock-tables.h similarity index 98% rename from arch/arm/include/asm/arch-tegra124/clock-tables.h rename to arch/arm/mach-tegra/tegra124/include/mach/clock-tables.h index 9466b4ffb33e..dcd5cd905dec 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/mach-tegra/tegra124/include/mach/clock-tables.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,8 +7,8 @@
/* Tegra124 clock PLL tables */
-#ifndef _TEGRA124_CLOCK_TABLES_H_ -#define _TEGRA124_CLOCK_TABLES_H_ +#ifndef _TEGRA124_CLOCK_TABLES_H +#define _TEGRA124_CLOCK_TABLES_H
/* The PLLs supported by the hardware */ enum clock_id { @@ -495,4 +495,4 @@ enum periphc_internal_id { #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ (id) < PERIPH_ID_COUNT)
-#endif /* _TEGRA124_CLOCK_TABLES_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/mach-tegra/tegra124/include/mach/clock.h similarity index 85% rename from arch/arm/include/asm/arch-tegra124/clock.h rename to arch/arm/mach-tegra/tegra124/include/mach/clock.h index ff99b9dfafda..e0d426704860 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/mach-tegra/tegra124/include/mach/clock.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2013 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,10 +7,10 @@
/* Tegra124 clock control definitions */
-#ifndef _TEGRA124_CLOCK_H_ -#define _TEGRA124_CLOCK_H_ +#ifndef _TEGRA124_CLOCK_H +#define _TEGRA124_CLOCK_H
-#include <asm/arch-tegra/clock.h> +#include <mach/clock_common.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 28 @@ -42,4 +42,4 @@ u32 clock_set_display_rate(u32 frequency); */ void clock_set_up_plldp(void);
-#endif /* _TEGRA124_CLOCK_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra124/pllx.c b/arch/arm/mach-tegra/tegra124/pllx.c index c19f1df6014b..56125b517c80 100644 --- a/arch/arm/mach-tegra/tegra124/pllx.c +++ b/arch/arm/mach-tegra/tegra124/pllx.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include "../cpu.h" #include "../pllx.h"
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 182ab6f50db8..9b6d2cac0f80 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -11,10 +11,10 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../tegra.h"
/* diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index c089e7a8ed0d..42a9a3089c14 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -8,7 +8,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include "../apb_misc.h" #include "../emc.h" #include "../tegra.h" diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/mach-tegra/tegra20/include/mach/clock-tables.h similarity index 95% rename from arch/arm/include/asm/arch-tegra20/clock-tables.h rename to arch/arm/mach-tegra/tegra20/include/mach/clock-tables.h index 812e8760d0cd..6a6bb40a31e7 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/mach-tegra/tegra20/include/mach/clock-tables.h @@ -1,14 +1,14 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */
/* Tegra20 clock PLL tables */
-#ifndef _CLOCK_TABLES_H_ -#define _CLOCK_TABLES_H_ +#ifndef _TEGRA20_CLOCK_TABLES_H +#define _TEGRA20_CLOCK_TABLES_H
/* The PLLs supported by the hardware */ enum clock_id { @@ -183,4 +183,4 @@ enum pll_out_id { #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ (id) < PERIPH_ID_COUNT)
-#endif /* _CLOCK_TABLES_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/mach-tegra/tegra20/include/mach/clock.h similarity index 77% rename from arch/arm/include/asm/arch-tegra20/clock.h rename to arch/arm/mach-tegra/tegra20/include/mach/clock.h index 4df8da96e2a3..0a59ef749721 100644 --- a/arch/arm/include/asm/arch-tegra20/clock.h +++ b/arch/arm/mach-tegra/tegra20/include/mach/clock.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +10,7 @@ #ifndef _TEGRA20_CLOCK_H #define _TEGRA20_CLOCK_H
-#include <asm/arch-tegra/clock.h> +#include <mach/clock_common.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 30 @@ -17,4 +18,4 @@
int tegra_plle_enable(void);
-#endif /* _TEGRA20_CLOCK_H */ +#endif diff --git a/arch/arm/mach-tegra/tegra20/pllx.c b/arch/arm/mach-tegra/tegra20/pllx.c index 1e0127313c4f..15b2c8d9d198 100644 --- a/arch/arm/mach-tegra/tegra20/pllx.c +++ b/arch/arm/mach-tegra/tegra20/pllx.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include "../pllx.h" #include "sku.h"
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 1f3f3843b438..e43699cd8fe8 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -8,8 +8,8 @@ #include <common.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../apb_misc.h" #include "../emc.h" #include "../pmc.h" diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 82722b5b52ec..aab4cb93ff7b 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -7,8 +7,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <soc/flow.h> #include "../apb_misc.h" #include "../cpu.h" diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 830ff6d267c6..38f91679222a 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -10,10 +10,10 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../sysctr.h" #include "../tegra.h"
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/mach-tegra/tegra210/include/mach/clock-tables.h similarity index 98% rename from arch/arm/include/asm/arch-tegra210/clock-tables.h rename to arch/arm/mach-tegra/tegra210/include/mach/clock-tables.h index a612485d8e23..fb5ba4840dd7 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/mach-tegra/tegra210/include/mach/clock-tables.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,8 +7,8 @@
/* Tegra210 clock PLL tables */
-#ifndef _TEGRA210_CLOCK_TABLES_H_ -#define _TEGRA210_CLOCK_TABLES_H_ +#ifndef _TEGRA210_CLOCK_TABLES_H +#define _TEGRA210_CLOCK_TABLES_H
/* The PLLs supported by the hardware */ enum clock_id { @@ -565,4 +565,4 @@ enum periphc_internal_id { #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ (id) < PERIPH_ID_COUNT)
-#endif /* _TEGRA210_CLOCK_TABLES_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/mach-tegra/tegra210/include/mach/clock.h similarity index 78% rename from arch/arm/include/asm/arch-tegra210/clock.h rename to arch/arm/mach-tegra/tegra210/include/mach/clock.h index 54e70439952d..785179a720a9 100644 --- a/arch/arm/include/asm/arch-tegra210/clock.h +++ b/arch/arm/mach-tegra/tegra210/include/mach/clock.h @@ -7,10 +7,10 @@
/* Tegra210 clock control definitions */
-#ifndef _TEGRA210_CLOCK_H_ -#define _TEGRA210_CLOCK_H_ +#ifndef _TEGRA210_CLOCK_H +#define _TEGRA210_CLOCK_H
-#include <asm/arch-tegra/clock.h> +#include <mach/clock_common.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 28 @@ -23,4 +23,4 @@
int tegra_plle_enable(void);
-#endif /* _TEGRA210_CLOCK_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra210/pllx.c b/arch/arm/mach-tegra/tegra210/pllx.c index 9c6f0e0013da..5558dd52e597 100644 --- a/arch/arm/mach-tegra/tegra210/pllx.c +++ b/arch/arm/mach-tegra/tegra210/pllx.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include "../cpu.h" #include "../pllx.h"
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 44523c5b385b..bfa0f3dd9ecd 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -8,13 +8,11 @@
#include <common.h> #include <errno.h> - +#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../xusb-padctl-common.h"
-#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> - -#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
enum tegra210_function { TEGRA210_FUNC_SNPS, diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index dca6d1118b3b..7483d052b47c 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -10,10 +10,10 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <div64.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "../tegra.h"
/* diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index ac234da59d50..b6a142dd1a9b 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -6,8 +6,8 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/tegra_i2c.h> #include <soc/flow.h> #include "../cpu.h" diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/mach-tegra/tegra30/include/mach/clock-tables.h similarity index 97% rename from arch/arm/include/asm/arch-tegra30/clock-tables.h rename to arch/arm/mach-tegra/tegra30/include/mach/clock-tables.h index 16b4b963305e..c89076f3c237 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/mach-tegra/tegra30/include/mach/clock-tables.h @@ -1,13 +1,13 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
/* Tegra30 clock PLL tables */
-#ifndef _TEGRA30_CLOCK_TABLES_H_ -#define _TEGRA30_CLOCK_TABLES_H_ +#ifndef _TEGRA30_CLOCK_TABLES_H +#define _TEGRA30_CLOCK_TABLES_H
/* The PLLs supported by the hardware */ enum clock_id { @@ -370,4 +370,4 @@ enum periphc_internal_id { #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ (id) < PERIPH_ID_COUNT)
-#endif /* _TEGRA30_CLOCK_TABLES_H_ */ +#endif diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/mach-tegra/tegra30/include/mach/clock.h similarity index 58% rename from arch/arm/include/asm/arch-tegra30/clock.h rename to arch/arm/mach-tegra/tegra30/include/mach/clock.h index 46cd7d8e01b8..da7d34cd9880 100644 --- a/arch/arm/include/asm/arch-tegra30/clock.h +++ b/arch/arm/mach-tegra/tegra30/include/mach/clock.h @@ -1,15 +1,15 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */
/* Tegra30 clock control functions */
-#ifndef _TEGRA30_CLOCK_H_ -#define _TEGRA30_CLOCK_H_ +#ifndef _TEGRA30_CLOCK_H +#define _TEGRA30_CLOCK_H
-#include <asm/arch-tegra/clock.h> +#include <mach/clock_common.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 28 @@ -17,4 +17,4 @@
int tegra_plle_enable(void);
-#endif /* _TEGRA30_CLOCK_H_ */ +#endif diff --git a/arch/arm/mach-tegra/tegra30/pllx.c b/arch/arm/mach-tegra/tegra30/pllx.c index 7c4f0ab67f1c..e0e7278a7523 100644 --- a/arch/arm/mach-tegra/tegra30/pllx.c +++ b/arch/arm/mach-tegra/tegra30/pllx.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch-tegra/clock.h> +#include <mach/clock.h> #include "../cpu.h" #include "../pllx.h"
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 18ad7bfbdc0f..fbcde07deaa8 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -8,11 +8,9 @@
#include <common.h> #include <errno.h> - +#include <mach/clock.h> #include "xusb-padctl-common.h"
-#include <asm/arch/clock.h> - int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) { if (phy && phy->ops && phy->ops->prepare) diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index a5e958235355..4d8bd224cda8 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -10,6 +10,7 @@ #include <power/as3722.h> #include <asm/gpio.h> #include <mach/board_init.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include <mach/spl_uart.h> #include <mach/tegra_gpio.h> @@ -17,8 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#include <asm/arch/clock.h> - void tegra_spl_board_init(void) { tegra124_pinmux_uartd_gpio(); diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index c38ae8c9a02d..3e7ef191d463 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -10,8 +10,8 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <power/as3722.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> #include <mach/board_init.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include <mach/tegra_gpio.h> #include <mach/spl_uart.h> diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index b462f2264b33..dcd71fa39cab 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -12,8 +12,8 @@ #include <fdtdec.h> #include <i2c.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/tegra_i2c.h> #include "tegra_i2c_priv.h"
diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index df0f52c2c6f8..e57b8ff0969d 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -14,7 +14,7 @@ #include <stdio_dev.h> #include <tegra-kbc.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <linux/input.h>
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 6e1667b3bce7..ae1cb366ddaa 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -13,8 +13,8 @@ #include <mmc.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/tegra_mmc.h> #include "tegra_mmc_priv.h"
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 391b807127c8..76f31fab06e6 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -11,12 +11,12 @@ #include <asm/io.h> #include <memalign.h> #include <nand.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <asm/errno.h> #include <asm/gpio.h> #include <fdtdec.h> #include <bouncebuf.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "tegra_nand.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index f19e213bd7bd..485c02626a91 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -22,9 +22,8 @@ #include <asm/io.h> #include <asm/gpio.h>
-#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> - +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/powergate.h> #include <mach/xusb-padctl.h>
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index a0f204a216de..8e760e61cc45 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -9,7 +9,7 @@ #include <dm.h> #include <pwm.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include "tegra_pwm_priv.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 509afba0a298..d4b91462dd91 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -1,7 +1,7 @@ /* * NVIDIA Tegra SPI controller (T114 and later) * - * Copyright (c) 2010-2013 NVIDIA Corporation + * Copyright (c) 2010-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -9,10 +9,10 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <spi.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 4e51b252e6a2..db71a879c524 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -11,8 +11,8 @@ #include <errno.h> #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include <spi.h> #include <fdtdec.h> diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index 238edec23ba5..5683aadc3e58 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -1,7 +1,7 @@ /* * NVIDIA Tegra SPI-SLINK controller * - * Copyright (c) 2010-2013 NVIDIA Corporation + * Copyright (c) 2010-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -9,10 +9,10 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <spi.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index 6bbbe9383954..8f5d6e750c84 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -1,7 +1,7 @@ /* * NVIDIA Tegra210 QSPI controller driver * - * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,10 +9,10 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <spi.h> #include <fdtdec.h> +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 9bf069382605..e69db25608e8 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -11,13 +11,12 @@ #include <asm/errno.h> #include <asm/io.h> #include <asm-generic/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/clk_rst.h> #include <usb.h> #include <usb/ulpi.h> #include <libfdt.h> #include <fdtdec.h> - +#include <mach/clk_rst.h> +#include <mach/clock.h> #include "ehci.h" #include "ehci-tegra-priv.h"
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 8543c2980cf8..d7db70eb7bf0 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -13,7 +13,7 @@ #include <asm/system.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <mach/pinmux.h> #include "tegra_dc.h"
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index bc31103e8b92..e5d0aabc75a0 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -18,7 +18,7 @@ #include <video.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <dm/uclass-internal.h> #include "../tegra_dc.h" #include "displayport.h" diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 40d9dd22a2c4..bb24ccecfc62 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -12,7 +12,7 @@ #include <panel.h> #include <video_bridge.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include "../tegra_dc.h" #include "displayport.h" #include "sor.h"
On 19 April 2016 at 14:59, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
These are the last files in arch/arm/include/asm/arch-tegra*. Move them into arch/arm/mach-tegra. The Tegra clock API currently exposes a lot of internal implementation details, which are unfortunately relied upon throughout the code base. Consequently, the headers are moved to <mach/> rather than being hidden out of the global include path. This needs cleanup/refactoring, especially since the current state cannot support the next chip at all. However, this cleanup series is already rather long, and the work to cleanup the clock API rather involved, so I'll do that later.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 4 ++-- arch/arm/mach-tegra/clock.c | 4 ++-- arch/arm/mach-tegra/cpu.c | 4 ++-- .../asm/arch-tegra => mach-tegra/include/mach}/clk_rst.h | 6 +++--- .../clock.h => mach-tegra/include/mach/clock_common.h} | 8 ++++---- arch/arm/mach-tegra/include/mach/powergate.h | 2 +- arch/arm/mach-tegra/spl.c | 2 +- arch/arm/mach-tegra/spl_uart.c | 2 +- arch/arm/mach-tegra/tegra114/clock.c | 4 ++-- arch/arm/mach-tegra/tegra114/cpu.c | 4 ++-- .../tegra114/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra114 => mach-tegra/tegra114/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra114/pllx.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 4 ++-- arch/arm/mach-tegra/tegra124/cpu.c | 4 ++-- .../tegra124/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra124 => mach-tegra/tegra124/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra124/pllx.c | 2 +- arch/arm/mach-tegra/tegra20/clock.c | 4 ++-- arch/arm/mach-tegra/tegra20/emc.c | 2 +- .../tegra20/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra20 => mach-tegra/tegra20/include/mach}/clock.h | 5 +++-- arch/arm/mach-tegra/tegra20/pllx.c | 2 +- arch/arm/mach-tegra/tegra20/warmboot.c | 4 ++-- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 4 ++-- arch/arm/mach-tegra/tegra210/clock.c | 4 ++-- .../tegra210/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra210 => mach-tegra/tegra210/include/mach}/clock.h | 8 ++++---- arch/arm/mach-tegra/tegra210/pllx.c | 2 +- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 8 +++----- arch/arm/mach-tegra/tegra30/clock.c | 4 ++-- arch/arm/mach-tegra/tegra30/cpu.c | 4 ++-- .../tegra30/include/mach}/clock-tables.h | 8 ++++---- .../arch-tegra30 => mach-tegra/tegra30/include/mach}/clock.h | 10 +++++----- arch/arm/mach-tegra/tegra30/pllx.c | 2 +- arch/arm/mach-tegra/xusb-padctl-common.c | 6 ++---- board/nvidia/jetson-tk1/jetson-tk1.c | 3 +-- board/nvidia/nyan-big/nyan-big.c | 2 +- drivers/i2c/tegra_i2c.c | 4 ++-- drivers/input/tegra-kbc.c | 2 +- drivers/mmc/tegra_mmc.c | 4 ++-- drivers/mtd/nand/tegra_nand.c | 4 ++-- drivers/pci/pci_tegra.c | 5 ++--- drivers/pwm/tegra_pwm.c | 2 +- drivers/spi/tegra114_spi.c | 6 +++--- drivers/spi/tegra20_sflash.c | 4 ++-- drivers/spi/tegra20_slink.c | 6 +++--- drivers/spi/tegra210_qspi.c | 6 +++--- drivers/usb/host/ehci-tegra.c | 5 ++--- drivers/video/tegra.c | 2 +- drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/sor.c | 2 +- 54 files changed, 119 insertions(+), 125 deletions(-) rename arch/arm/{include/asm/arch-tegra => mach-tegra/include/mach}/clk_rst.h (99%) rename arch/arm/{include/asm/arch-tegra/clock.h => mach-tegra/include/mach/clock_common.h} (99%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra114 => mach-tegra/tegra114/include/mach}/clock.h (61%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra124 => mach-tegra/tegra124/include/mach}/clock.h (85%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock-tables.h (95%) rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20/include/mach}/clock.h (77%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock-tables.h (98%) rename arch/arm/{include/asm/arch-tegra210 => mach-tegra/tegra210/include/mach}/clock.h (78%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock-tables.h (97%) rename arch/arm/{include/asm/arch-tegra30 => mach-tegra/tegra30/include/mach}/clock.h (58%)
Reviewed-by: Simon Glass sjg@chromium.org
Hi Stephen,
On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
This series cleans up Tegra code:
- Removes unused definitions.
- Unifies duplicate definitions and code.
- Moves Tegra headers from arch/arm/include to arch/arm/mach-tegra so
all Tegra files are located together. Headers for Tegra-specific APIs (intended e.g. for public/driver use) are placed into <mach/>, whereas headers intended only for use by code in arch/arm/mach-tegra are placed into <soc/>.
- Hides as much internal Tegra information as possible, to reduce the
size of the "API" provided to Tegra boards. This will help refactoring that "API" later; the next chip is quite different and various parts of this API (e.g. clock, reset, GPIO, ...) will need alternative implementations. This will hopefully be a bit easier after this series.
- Cleans up the set of functions the core Tegra "board" support calls and
which are implemented by Tegra board files.
- Replaces funcmux with pinmux functions so that pinmux is set up in as
much the same way across all Tegra SoCs as possible.
- Various other cleanup.
- Removes almost 3000 lines!
Future changes/series will likely/hopefully:
- Refactor C files in arch/arm/mach-tegra to allow Makefiles to easily
decide which parts to pull in for each chip, and avoid a mess of ifdefs in the C files when adding support for the next chip.
- Convert Tegra to standard clock/reset APIs, since the next chipd will
use a different implementation, yet we need them to share the same API so that drivers don't need conditional code.
- Add some new drivers for the next chip.
I've reviewed the reset of the patches. It is a huge improvement in the tegra code. It's more consistent and fixes up some of the weird code placement and muddy concepts.
If there are any patches I am missed, let me know.
My main comment is that the pinctrl stuff should go in a driver. There is not way we should be inventing a new pinmux API for tegra now that we have driver model pinctrl :-)
I am happy to help with this if you like.
Regards, Simon
participants (5)
-
Heiko Schocher -
Simon Glass -
Stephen Warren -
Tom Rini -
Wolfgang Denk