[U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 1001 is observed, change set the same value.
Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009008(): 1.Put a blank line after variable declaration. 2.Move common code together.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 40 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b..300f5ce 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -22,6 +22,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -43,6 +44,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -79,6 +81,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -222,6 +225,10 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010539 bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008 + bool "Workaround for USB PHY erratum A009008" + + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index aee1ffa..261b2dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -52,6 +52,30 @@ bool soc_has_aiop(void) return false; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); + + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6)); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6)); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6)); +#elif defined(CONFIG_ARCH_LS2080A) + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); + + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +222,7 @@ void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336(); + erratum_a009008(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -473,6 +498,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009008(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..62d7046 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -337,6 +337,12 @@ struct ccsr_gur { #define SCFG_USBPWRFAULT_USB2_SHIFT 2 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM1CR_USB3 0x088 +#define USB_TXVREFTUNE 0x9 + #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59410aa..c622ee5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -133,6 +133,7 @@ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a +#define USB_TXVREFTUNE 0x9 #define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV woards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009798(): 1.Put a blank line after variable declaration. 2.Move common code together.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 22 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 300f5ce..2dae539 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -23,6 +23,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -45,6 +46,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -82,6 +84,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -228,6 +231,8 @@ config SYS_FSL_ERRATUM_A010539 config SYS_FSL_ERRATUM_A009008 bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798 + bool "Workaround for USB PHY erratum A009798"
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 261b2dd..14b5584 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -76,6 +76,26 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); + + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); + val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); +#elif defined(CONFIG_ARCH_LS2080A) + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); + + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -223,6 +243,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008514(); erratum_a008336(); erratum_a009008(); + erratum_a009798(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -499,6 +520,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009660(); erratum_a010539(); erratum_a009008(); + erratum_a009798(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 62d7046..8bd40e8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -342,6 +342,7 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR_USB2 0x07C #define SCFG_USB3PRM1CR_USB3 0x088 #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index c622ee5..2d309d5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -134,6 +134,7 @@ #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change setting required for transmitter signal swings to pass compliance tests.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a008997(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 24 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++ 3 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2dae539..a2de86b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -24,6 +24,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -47,6 +48,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -85,6 +87,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009203 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -234,6 +237,9 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997 + bool "Workaround for USB PHY erratum A008997" + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 14b5584..460e589 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -96,6 +96,28 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ }
+static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 +#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4); + + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4, + val | (USB_PCSTXSWINGFULL << 9)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -244,6 +266,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008336(); erratum_a009008(); erratum_a009798(); + erratum_a008997(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -521,6 +544,7 @@ void fsl_lsch2_early_init_f(void) erratum_a010539(); erratum_a009008(); erratum_a009798(); + erratum_a008997(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8bd40e8..2e52078 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -339,10 +339,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000 #define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM2CR_USB1 0x074 #define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM2CR_USB2 0x080 #define SCFG_USB3PRM1CR_USB3 0x088 +#define SCFG_USB3PRM2CR_USB3 0x08c #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Changes identified in setup makes the Rx compliance test pass.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009007(): 1.Put a blank line after variable declaration. 2.Create a mcro to run for each USB for easier to read and maintain.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 40 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++ 4 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a2de86b..1744ed9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -25,6 +25,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -49,6 +50,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -88,6 +90,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -238,7 +241,14 @@ config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A008997 - bool "Workaround for USB PHY erratum A008997" + bool + help + Workaround for USB PHY erratum A008997 + +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 460e589..d01e665 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -118,6 +118,44 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + +#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ + out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ + out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ + out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ + out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) + +#elif defined(CONFIG_ARCH_LS2080A) + +#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ + out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ + out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ + out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ + out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) + +#endif + +static void erratum_a009007(void) +{ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + void __iomem *usb_phy = (void __iomem *)USB_PHY1; + + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); + + usb_phy = (void __iomem *)USB_PHY2; + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); + + usb_phy = (void __iomem *)USB_PHY3; + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); +#elif defined(CONFIG_ARCH_LS2080A) + void __iomem *dcsr = (void __iomem *)DCSR_BASE; + + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -267,6 +305,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -545,6 +584,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 2e52078..69fd79c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -347,6 +347,14 @@ struct ccsr_gur { #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF #define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY1 0x084F0000 +#define USB_PHY2 0x08500000 +#define USB_PHY3 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 2d309d5..238d647 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -137,6 +137,15 @@ #define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10
+#define DCSR_BASE 0x700000000ULL +#define DCSR_USB_PHY1 0x4600000 +#define DCSR_USB_PHY2 0x4610000 +#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 + #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ #define TP_ITYP_TYPE_ARM 0x0
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is ovserved, change set the same value.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009008(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 15 +++++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 6a013b2..96e9782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -51,6 +52,11 @@ config SECURE_BOOT config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008 + bool + help + Workaround for USB erratum A009008 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b84a1a6..ac060bb 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void) return major; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + + val &= ~(0xF << 6); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + + void s_init(void) { } @@ -146,6 +158,9 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */ + erratum_a009008(); + return 0; }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c34fd63..6ea8c4b 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -173,6 +173,10 @@ struct ccsr_gur { #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR 0x070 +#define USB_TXVREFTUNE 0x9 + /* Supplemental Configuration Unit */ struct ccsr_scfg { u32 dpslpcr;
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009798(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++- arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 96e9782..609333e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -6,6 +6,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -55,7 +56,12 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A009008 bool help - Workaround for USB erratum A009008 + Workaround for USB PHY erratum A009008 + +config SYS_FSL_ERRATUM_A009798 + bool + help + Workaround for USB PHY erratum A009798
config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index ac060bb..9401175 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -71,6 +71,15 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + + out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +}
void s_init(void) { @@ -160,6 +169,7 @@ int arch_soc_init(void)
/* Erratum */ erratum_a009008(); + erratum_a009798();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 6ea8c4b..8cafa07 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -176,6 +176,7 @@ struct ccsr_gur { #define SCFG_BASE 0x01570000 #define SCFG_USB3PRM1CR 0x070 #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF
/* Supplemental Configuration Unit */ struct ccsr_scfg {
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass compliance tests.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a008997(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 3 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 609333e..0acff07 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -63,6 +64,11 @@ config SYS_FSL_ERRATUM_A009798 help Workaround for USB PHY erratum A009798
+config SYS_FSL_ERRATUM_A008997 + bool + help + Workaround for USB PHY erratum A008997 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 9401175..6f8eb0b 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -81,6 +81,19 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ }
+static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM2CR / 4); + + val &= ~USB_PCSTXSWINGFULL_MASK; + val |= USB_PCSTXSWINGFULL_VAL; + out_be32(scfg + SCFG_USB3PRM2CR / 4, val); +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + + void s_init(void) { } @@ -170,6 +183,7 @@ int arch_soc_init(void) /* Erratum */ erratum_a009008(); erratum_a009798(); + erratum_a008997();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 8cafa07..539c1cf 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -177,6 +177,9 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR 0x070 #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define SCFG_USB3PRM2CR 0x074 +#define USB_PCSTXSWINGFULL_MASK 0x0000FE00 +#define USB_PCSTXSWINGFULL_VAL 0x00008E00
/* Supplemental Configuration Unit */ struct ccsr_scfg {
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: In function erratum_a009007(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 7 +++++++ 3 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 0acff07..f45bb1d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -8,6 +8,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -69,6 +70,11 @@ config SYS_FSL_ERRATUM_A008997 help Workaround for USB PHY erratum A008997
+config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 6f8eb0b..9e78344 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -93,6 +93,17 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009007 + void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; + + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +}
void s_init(void) { @@ -184,6 +195,7 @@ int arch_soc_init(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 539c1cf..703e59f 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -181,6 +181,13 @@ struct ccsr_gur { #define USB_PCSTXSWINGFULL_MASK 0x0000FE00 #define USB_PCSTXSWINGFULL_VAL 0x00008E00
+#define USB_PHY_BASE 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8004 +#define USB_PHY_RX_EQ_VAL_4 0x800C + /* Supplemental Configuration Unit */ struct ccsr_scfg { u32 dpslpcr;
On 08/11/2017 12:26 AM, Ran Wang wrote:
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_ARCH_LS2080A)
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +}
Ran,
Wouldn't it be cleaner to make an inline function like this
static inline void usb_errata_a009008(u32 __iomem *scfg, u32 offset) { u32 val;
val = scfg_in32(scfg + offset / 4) & ~(0xF << 6); val |= USB_TXVREFTUNE << 6; scfg_out32(scfg + offset / 4, val); }
Then your function can be rewritten as
static void erratum_a009008(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB1); usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB2); usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB3); usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB4); #elif defined(CONFIG_ARCH_LS2080A) usb_errata_a009008(scfg, SCFG_USB3PRM1CR); #else #error Platform not defined #endif #endif }
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