On x86 the SPI ROM can be memory-mapped, at least most of it. Add a way to tell binman the offset from a ROM address to a RAM address.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Changes in v1: - Add a way to set the binman ROM offset

include/binman.h | 8 ++++++++ lib/binman.c | 17 +++++++++++++++++ 2 files changed, 25 insertions(+)

diff --git a/include/binman.h b/include/binman.h index b462dc8542..baf49f7876 100644 --- a/include/binman.h +++ b/include/binman.h @@ -20,6 +20,14 @@ struct binman_entry { u32 size; };

+/** + * binman_set_rom_offset() - Set the ROM memory-map offset + * + * @rom_offset: Offset from an image_pos to the memory-mapped address. This + * tells binman that ROM image_pos x can be addressed at rom_offset + x + */ +void binman_set_rom_offset(int rom_offset); + /** * binman_entry_find() - Find a binman symbol * diff --git a/lib/binman.c b/lib/binman.c index fd7de24bd2..dc3a880882 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -12,10 +12,21 @@ #include <log.h> #include <malloc.h>

+/** + * struct binman_info - Information needed by the binman library + * + * @image: Node describing the image we are running from + * @rom_offset: Offset from an image_pos to the memory-mapped address, or + * ROM_OFFSET_NONE if the ROM is not memory-mapped. Can be positive or + * negative + */ struct binman_info { ofnode image; + int rom_offset; };

+#define ROM_OFFSET_NONE (-1) + static struct binman_info *binman;

int binman_entry_find(const char *name, struct binman_entry *entry) @@ -37,6 +48,11 @@ int binman_entry_find(const char *name, struct binman_entry *entry) return 0; }

+void binman_set_rom_offset(int rom_offset) +{ + binman->rom_offset = rom_offset; +} + int binman_init(void) { binman = malloc(sizeof(struct binman_info)); @@ -45,6 +61,7 @@ int binman_init(void) binman->image = ofnode_path("/binman"); if (!ofnode_valid(binman->image)) return log_msg_ret("binman node", -EINVAL); + binman->rom_offset = ROM_OFFSET_NONE;

return 0; }

At present we can only read from a top-level binman node entry. Refactor this function to produce a second local function which supports reading from any node.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Rename binman_entry_find_()

lib/binman.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/lib/binman.c b/lib/binman.c index dc3a880882..9098a1dffa 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -29,25 +29,32 @@ struct binman_info {

static struct binman_info *binman;

-int binman_entry_find(const char *name, struct binman_entry *entry) +static int binman_entry_find_internal(ofnode node, const char *name, + struct binman_entry *entry) { - ofnode node; int ret;

- node = ofnode_find_subnode(binman->image, name); if (!ofnode_valid(node)) - return log_msg_ret("no binman node", -ENOENT); + node = binman->image; + node = ofnode_find_subnode(node, name); + if (!ofnode_valid(node)) + return log_msg_ret("node", -ENOENT);

ret = ofnode_read_u32(node, "image-pos", &entry->image_pos); if (ret) - return log_msg_ret("bad binman node1", ret); + return log_msg_ret("import-pos", ret); ret = ofnode_read_u32(node, "size", &entry->size); if (ret) - return log_msg_ret("bad binman node2", ret); + return log_msg_ret("size", ret);

return 0; }

+int binman_entry_find(const char *name, struct binman_entry *entry) +{ + return binman_entry_find_internal(binman->image, name, entry); +} + void binman_set_rom_offset(int rom_offset) { binman->rom_offset = rom_offset;

Add support for accessing an entry's contents in memory-mapped SPI flash.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

include/binman.h | 22 ++++++++++++++++++++++ lib/binman.c | 23 +++++++++++++++++++++++ 2 files changed, 45 insertions(+)

diff --git a/include/binman.h b/include/binman.h index baf49f7876..e0b92075e2 100644 --- a/include/binman.h +++ b/include/binman.h @@ -9,6 +9,8 @@ #ifndef _BINMAN_H_ #define _BINMAN_H_

+#include <dm/ofnode.h> + /** *struct binman_entry - information about a binman entry * @@ -20,6 +22,18 @@ struct binman_entry { u32 size; };

+/** + * binman_entry_map() - Look up the address of an entry in memory + * + * @parent: Parent binman node + * @name: Name of entry + * @bufp: Returns a pointer to the entry + * @sizep: Returns the size of the entry + * @return 0 on success, -EPERM if the ROM offset is not set, -ENOENT if the + * entry cannot be found, other error code other error + */ +int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep); + /** * binman_set_rom_offset() - Set the ROM memory-map offset * @@ -41,6 +55,14 @@ void binman_set_rom_offset(int rom_offset); */ int binman_entry_find(const char *name, struct binman_entry *entry);

+/** + * binman_section_find_node() - Find a binman node + * + * @name: Name of node to look for + * @return Node that was found, ofnode_null() if not found + */ +ofnode binman_section_find_node(const char *name); + /** * binman_init() - Set up the binman symbol information * diff --git a/lib/binman.c b/lib/binman.c index 9098a1dffa..7a8ad62c4a 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -11,6 +11,7 @@ #include <dm.h> #include <log.h> #include <malloc.h> +#include <mapmem.h>

/** * struct binman_info - Information needed by the binman library @@ -55,6 +56,28 @@ int binman_entry_find(const char *name, struct binman_entry *entry) return binman_entry_find_internal(binman->image, name, entry); }

+int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep) +{ + struct binman_entry entry; + int ret; + + if (binman->rom_offset == ROM_OFFSET_NONE) + return -EPERM; + ret = binman_entry_find_internal(parent, name, &entry); + if (ret) + return log_msg_ret("entry", ret); + if (sizep) + *sizep = entry.size; + *bufp = map_sysmem(entry.image_pos + binman->rom_offset, entry.size); + + return 0; +} + +ofnode binman_section_find_node(const char *name) +{ + return ofnode_find_subnode(binman->image, name); +} + void binman_set_rom_offset(int rom_offset) { binman->rom_offset = rom_offset;

In some cases an internal error may prevent this from working. Update the function return value and report the error. At present the API for writing tables does not easily support reporting errors, but once it is fully updated to use a context pointer, this will be easier.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Fix 'Gailed' typo

Changes in v1: - Add linux/err.h header

arch/x86/cpu/baytrail/acpi.c | 4 +++- arch/x86/cpu/quark/acpi.c | 4 +++- arch/x86/cpu/tangier/acpi.c | 4 +++- arch/x86/include/asm/acpi_table.h | 10 +++++++++- arch/x86/lib/acpi_table.c | 11 +++++++++-- 5 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index b17bc62a2d..07757b88a3 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -139,7 +139,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -159,6 +159,8 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) gnvs->iuart_en = 1; else gnvs->iuart_en = 0; + + return 0; }

/* diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 26cda3b337..b0406a04e9 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -133,8 +133,10 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { /* quark is a uni-processor */ gnvs->pcnt = 1; + + return 0; } diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 4ec8fdd6f8..41bd177e09 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -107,7 +107,7 @@ u32 acpi_fill_csrt(u32 current) return current; }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -122,4 +122,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) if (ret > 0) gnvs->pcnt = ret; } + + return 0; } diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 928475cef4..733085c178 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -35,7 +35,15 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); u32 acpi_fill_mcfg(u32 current); u32 acpi_fill_csrt(u32 current); -void acpi_create_gnvs(struct acpi_global_nvs *gnvs); + +/** + * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table + * + * @gnvs: Table to fill in + * @return 0 if OK, -ve on error + */ +int acpi_create_gnvs(struct acpi_global_nvs *gnvs); + ulong write_acpi_tables(ulong start);

/** diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index eeacfe9b06..8219376e17 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -23,6 +23,7 @@ #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <dm/acpi.h> +#include <linux/err.h>

/* * IASL compiles the dsdt entries and writes the hex values @@ -443,8 +444,14 @@ ulong write_acpi_tables(ulong start_addr) dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);

- /* Fill in platform-specific global NVS variables */ - acpi_create_gnvs(ctx->current); + /* + * Fill in platform-specific global NVS variables. If this fails we + * cannot return the error but this should only happen while debugging. + */ + addr = acpi_create_gnvs(ctx->current); + if (IS_ERR_VALUE(addr)) + printf("Error: Failed to create GNVS\n"); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));

debug("ACPI: * FADT\n");

Some devices such as GPIO need to override the normal path that would be generated by driver model. Add a device-tree property for this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

doc/device-tree-bindings/device.txt | 23 +++++++++++++++++++++++ drivers/core/acpi.c | 19 +++++++++++++++++++ include/dm/acpi.h | 13 +++++++++++++ 3 files changed, 55 insertions(+)

diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt index 7140339623..2a5736c598 100644 --- a/doc/device-tree-bindings/device.txt +++ b/doc/device-tree-bindings/device.txt @@ -17,6 +17,8 @@ the acpi,compatible property. System) Device Name) - acpi,hid : Contains the string to use as the HID (Hardware ID) identifier _HID + - acpi,path : Specifies the full ACPI path for a device. This overrides the + normal path built from the driver-model hierarchy - acpi,name : Provides the ACPI name for a device, which is a string consisting of four alphanumeric character (upper case) - acpi,uid : _UID value for device @@ -47,3 +49,24 @@ pcie-a0@14,0 { interrupts-extended = <&acpi_gpe 0x3c 0>; }; }; + +p2sb: p2sb@d,0 { + u-boot,dm-pre-reloc; + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = <IOMAP_P2SB_BAR 0x100000>; + pci,no-autoconfig; + + n { + compatible = "intel,apl-pinctrl"; + u-boot,dm-pre-reloc; + intel,p2sb-port-id = <PID_GPIO_N>; + acpi,path = "\_SB.GPO0"; + gpio_n: gpio-n { + compatible = "intel,gpio"; + u-boot,dm-pre-reloc; + gpio-controller; + #gpio-cells = <2>; + linux-name = "INT3452:00"; + }; + }; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index b566f4f186..ae69258562 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -82,6 +82,25 @@ int acpi_get_name(const struct udevice *dev, char *out_name) return 0; }

+int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen) +{ + const char *path; + int ret; + + path = dev_read_string(dev, "acpi,path"); + if (path) { + if (strlen(path) >= maxlen) + return -E2BIG; + strcpy(out_path, path); + return 0; + } + ret = acpi_device_path(dev, out_path, maxlen); + if (ret) + return log_msg_ret("dev", ret); + + return 0; +} + /** * acpi_add_item() - Add a new item to the list of data collected * diff --git a/include/dm/acpi.h b/include/dm/acpi.h index 8e9b9f75ba..d8d2eb6130 100644 --- a/include/dm/acpi.h +++ b/include/dm/acpi.h @@ -187,6 +187,19 @@ int acpi_inject_dsdt(struct acpi_ctx *ctx); */ void acpi_dump_items(enum acpi_dump_option option);

+/** + * acpi_get_path() - Get the full ACPI path for a device + * + * This checks for any override in the device tree and calls acpi_device_path() + * if not + * + * @dev: Device to check + * @out_path: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -ve on error + */ +int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen); + #endif /* __ACPI__ */

#endif

At present only acpigen_write_integer() is exported for use by other code. But in some cases it is useful to call the specific function depending on the size of the value.

Export these functions and add a test.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

include/acpi/acpigen.h | 46 ++++++++++++++++++++++++++++++++++++++++++ test/dm/acpigen.c | 45 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index d06d2c0c73..c6644bc2b2 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -172,6 +172,52 @@ void acpigen_pop_len(struct acpi_ctx *ctx); */ char *acpigen_write_package(struct acpi_ctx *ctx, int nr_el);

+/** + * acpigen_write_byte() - Write a byte + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_byte(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_word() - Write a word + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_word(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_dword() - Write a dword + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_dword(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_qword() - Write a qword + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_qword(struct acpi_ctx *ctx, u64 data); + +/** + * acpigen_write_zero() - Write zero + * + * @ctx: ACPI context pointer + */ +void acpigen_write_zero(struct acpi_ctx *ctx); + +/** + * acpigen_write_one() - Write one + * + * @ctx: ACPI context pointer + */ +void acpigen_write_one(struct acpi_ctx *ctx); + /** * acpigen_write_integer() - Write an integer * diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 9e7a928b24..167a014553 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -872,5 +872,48 @@ static int dm_test_acpi_power_seq(struct unit_test_state *uts)

return 0; } - DM_TEST(dm_test_acpi_power_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test writing values */ +static int dm_test_acpi_write_values(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + ptr = acpigen_get_current(ctx); + + acpigen_write_zero(ctx); + acpigen_write_one(ctx); + acpigen_write_byte(ctx, TEST_INT8); + acpigen_write_word(ctx, TEST_INT16); + acpigen_write_dword(ctx, TEST_INT32); + acpigen_write_qword(ctx, TEST_INT64); + + ut_asserteq(ZERO_OP, *ptr++); + + ut_asserteq(ONE_OP, *ptr++); + + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(TEST_INT8, *ptr++); + + ut_asserteq(WORD_PREFIX, *ptr++); + ut_asserteq(TEST_INT16, get_unaligned((u16 *)ptr)); + ptr += 2; + + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(TEST_INT32, get_unaligned((u32 *)ptr)); + ptr += 4; + + ut_asserteq(QWORD_PREFIX, *ptr++); + ut_asserteq_64(TEST_INT64, get_unaligned((u64 *)ptr)); + ptr += 8; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_values, 0); +

Add a function to write a scope to the generated ACPI code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Rename parameter from 'name' to 'scope'

include/acpi/acpigen.h | 9 +++++++++ lib/acpi/acpigen.c | 7 +++++++ test/dm/acpi.c | 3 +-- test/dm/acpigen.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index c6644bc2b2..4a606125de 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -31,6 +31,7 @@ enum { DWORD_PREFIX = 0x0c, STRING_PREFIX = 0x0d, QWORD_PREFIX = 0x0e, + SCOPE_OP = 0x10, BUFFER_OP = 0x11, PACKAGE_OP = 0x12, METHOD_OP = 0x14, @@ -261,6 +262,14 @@ void acpigen_emit_namestring(struct acpi_ctx *ctx, const char *namepath); */ void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath);

+/** + * acpigen_write_scope() - Write a scope + * + * @ctx: ACPI context pointer + * @scope: Scope to write (e.g. "\_SB.ABCD") + */ +void acpigen_write_scope(struct acpi_ctx *ctx, const char *scope); + /** * acpigen_write_uuid() - Write a UUID * diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index 45216c1f9d..1e0a489d7b 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -258,6 +258,13 @@ void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath) acpigen_emit_namestring(ctx, namepath); }

+void acpigen_write_scope(struct acpi_ctx *ctx, const char *scope) +{ + acpigen_emit_byte(ctx, SCOPE_OP); + acpigen_write_len_f(ctx); + acpigen_emit_namestring(ctx, scope); +} + static void acpigen_write_method_internal(struct acpi_ctx *ctx, const char *name, uint flags) { diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 7768f9514c..b94c4ba4d1 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -20,9 +20,8 @@ #include <dm/acpi.h> #include <dm/test.h> #include <test/ut.h> +#include "acpi.h"

-#define ACPI_TEST_DEV_NAME "ABCD" -#define ACPI_TEST_CHILD_NAME "EFGH" #define BUF_SIZE 4096

/** diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 167a014553..1031185b96 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -917,3 +917,33 @@ static int dm_test_acpi_write_values(struct unit_test_state *uts) } DM_TEST(dm_test_acpi_write_values, 0);

+/* Test writing a scope */ +static int dm_test_acpi_scope(struct unit_test_state *uts) +{ + char buf[ACPI_PATH_MAX]; + struct acpi_ctx *ctx; + struct udevice *dev; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + ptr = acpigen_get_current(ctx); + + ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev)); + ut_assertok(acpi_device_path(dev, buf, sizeof(buf))); + acpigen_write_scope(ctx, buf); + acpigen_pop_len(ctx); + + ut_asserteq(SCOPE_OP, *ptr++); + ut_asserteq(13, get_length(ptr)); + ptr += 3; + ut_asserteq(ROOT_PREFIX, *ptr++); + ut_asserteq(DUAL_NAME_PREFIX, *ptr++); + ut_asserteq_strn("_SB_" ACPI_TEST_DEV_NAME, (char *)ptr); + ptr += 8; + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_scope, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

Write required information into the SSDT to describe the SD card card-detect pin. Since the required GPIO properties are not present in the device-tree binding, set them manually for now.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

Changes in v1: - Capitalise ACPI_OPS_PTR

configs/sandbox_defconfig | 2 + drivers/mmc/pci_mmc.c | 78 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 20c2694f4e..43e03221ad 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -145,7 +145,9 @@ CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y +CONFIG_MMC_PCI=y CONFIG_MMC_SANDBOX=y +CONFIG_MMC_SDHCI=y CONFIG_MTD=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 404264a697..0c45e1b893 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -7,10 +7,15 @@ #include <common.h> #include <dm.h> #include <errno.h> +#include <log.h> #include <malloc.h> #include <mapmem.h> #include <sdhci.h> -#include <asm/pci.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <acpi/acpi_dp.h> +#include <asm-generic/gpio.h> +#include <dm/acpi.h>

struct pci_mmc_plat { struct mmc_config cfg; @@ -20,6 +25,7 @@ struct pci_mmc_plat { struct pci_mmc_priv { struct sdhci_host host; void *base; + struct gpio_desc cd_gpio; };

static int pci_mmc_probe(struct udevice *dev) @@ -44,6 +50,15 @@ static int pci_mmc_probe(struct udevice *dev) return sdhci_probe(dev); }

+static int pci_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct pci_mmc_priv *priv = dev_get_priv(dev); + + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + + return 0; +} + static int pci_mmc_bind(struct udevice *dev) { struct pci_mmc_plat *plat = dev_get_platdata(dev); @@ -51,14 +66,75 @@ static int pci_mmc_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); }

+static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct pci_mmc_priv *priv = dev_get_priv(dev); + char path[ACPI_PATH_MAX]; + struct acpi_gpio gpio; + struct acpi_dp *dp; + int ret; + + if (!dev_of_valid(dev)) + return 0; + + ret = gpio_get_acpi(&priv->cd_gpio, &gpio); + if (ret) + return log_msg_ret("gpio", ret); + gpio.type = ACPI_GPIO_TYPE_INTERRUPT; + gpio.pull = ACPI_GPIO_PULL_NONE; + gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio.irq.shared = ACPI_IRQ_SHARED; + gpio.irq.wake = ACPI_IRQ_WAKE; + gpio.interrupt_debounce_timeout = 10000; /* 100ms */ + + /* Use device path as the Scope for the SSDT */ + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + acpigen_write_scope(ctx, path); + acpigen_write_name(ctx, "_CRS"); + + /* Write GpioInt() as default (if set) or custom from devicetree */ + acpigen_write_resourcetemplate_header(ctx); + acpi_device_write_gpio(ctx, &gpio); + acpigen_write_resourcetemplate_footer(ctx); + + /* Bind the cd-gpio name to the GpioInt() resource */ + dp = acpi_dp_new_table("_DSD"); + if (!dp) + return -ENOMEM; + acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1); + ret = acpi_dp_write(ctx, dp); + if (ret) + return log_msg_ret("cd", ret); + + acpigen_pop_len(ctx); + + return 0; +} + +struct acpi_ops pci_mmc_acpi_ops = { + .fill_ssdt = pci_mmc_acpi_fill_ssdt, +}; + +static const struct udevice_id pci_mmc_match[] = { + { .compatible = "intel,apl-sd" }, + { } +}; + U_BOOT_DRIVER(pci_mmc) = { .name = "pci_mmc", .id = UCLASS_MMC, + .of_match = pci_mmc_match, .bind = pci_mmc_bind, + .ofdata_to_platdata = pci_mmc_ofdata_to_platdata, .probe = pci_mmc_probe, .ops = &sdhci_ops, .priv_auto_alloc_size = sizeof(struct pci_mmc_priv), .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat), + ACPI_OPS_PTR(&pci_mmc_acpi_ops) };

static struct pci_device_id mmc_supported[] = {

Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table (NHLT).

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Add a comment pointing to the PCI spec

include/dt-bindings/sound/nhlt.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/sound/nhlt.h

diff --git a/include/dt-bindings/sound/nhlt.h b/include/dt-bindings/sound/nhlt.h new file mode 100644 index 0000000000..dad69c24b4 --- /dev/null +++ b/include/dt-bindings/sound/nhlt.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _DT_BINDINGS_SOUND_NHLT_H +#define _DT_BINDINGS_SOUND_NHLT_H + +/* See Table 2-1. NHLT Endpoint Descriptor in the NHLT Specification (0.8.1) */ +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +/* Hardware links available to use for codecs */ +#define AUDIO_LINK_SSP0 0 +#define AUDIO_LINK_SSP1 1 +#define AUDIO_LINK_SSP2 2 +#define AUDIO_LINK_SSP3 3 +#define AUDIO_LINK_SSP4 4 +#define AUDIO_LINK_SSP5 5 +#define AUDIO_LINK_DMIC 6 + +#endif /* _DT_BINDINGS_SOUND_NHLT_H */

Allow writing an ACPI device to the generated ACPI code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

include/acpi/acpigen.h | 9 +++++++++ lib/acpi/acpigen.c | 7 +++++++ test/dm/acpigen.c | 27 +++++++++++++++++++++++++++ 3 files changed, 43 insertions(+)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 1f37c9c31c..59d7c2ff6f 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -56,6 +56,7 @@ enum { AND_OP = 0x7b, OR_OP = 0x7d, NOT_OP = 0x80, + DEVICE_OP = 0x82, POWER_RES_OP = 0x84, RETURN_OP = 0xa4, }; @@ -313,6 +314,14 @@ void acpigen_write_method(struct acpi_ctx *ctx, const char *name, int nargs); void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name, int nargs);

+/** + * acpigen_write_device() - Write an ACPI device + * + * @ctx: ACPI context pointer + * @name: Device name to write + */ +void acpigen_write_device(struct acpi_ctx *ctx, const char *name); + /** * acpigen_write_sta() - Write a _STA method * diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index 45691b7961..a66601a138 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -291,6 +291,13 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name, ACPI_METHOD_SERIALIZED_MASK); }

+void acpigen_write_device(struct acpi_ctx *ctx, const char *name) +{ + acpigen_emit_ext_op(ctx, DEVICE_OP); + acpigen_write_len_f(ctx); + acpigen_emit_namestring(ctx, name); +} + void acpigen_write_sta(struct acpi_ctx *ctx, uint status) { /* Method (_STA, 0, NotSerialized) { Return (status) } */ diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index d1bdd18ce5..8fbe30b152 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -993,3 +993,30 @@ static int dm_test_acpi_resource_template(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_resource_template, 0); + +/* Test writing a device */ +static int dm_test_acpi_device(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + ptr = acpigen_get_current(ctx); + + acpigen_write_device(ctx, "\_SB." ACPI_TEST_DEV_NAME); + acpigen_pop_len(ctx); + + ut_asserteq(EXT_OP_PREFIX, *ptr++); + ut_asserteq(DEVICE_OP, *ptr++); + ut_asserteq(0xd, get_length(ptr)); + ptr += 3; + ut_asserteq(ROOT_PREFIX, *ptr++); + ut_asserteq(DUAL_NAME_PREFIX, *ptr++); + ptr += 8; + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_device, 0);

The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the audio codecs and connections in a system. Various devices can contribute information to produce the table.

Add functions to allow adding to the structure that is eventually written to the ACPI tables. Also add the device-tree bindings.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Move this patch before the audio-codec drivers - Use BIT() for the SPEAKER enum

Changes in v1: - Add a new patch to support building up an NHLT structure

arch/x86/include/asm/acpi_nhlt.h | 314 ++++++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/acpi_nhlt.c | 482 +++++++++++++++++++++++++++++++ 3 files changed, 797 insertions(+) create mode 100644 arch/x86/include/asm/acpi_nhlt.h create mode 100644 arch/x86/lib/acpi_nhlt.c

diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h new file mode 100644 index 0000000000..4720321381 --- /dev/null +++ b/arch/x86/include/asm/acpi_nhlt.h @@ -0,0 +1,314 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + * + * Modified from coreboot nhlt.h + */ + +#ifndef _NHLT_H_ +#define _NHLT_H_ + +struct acpi_ctx; +struct nhlt; +struct nhlt_endpoint; +struct nhlt_format; +struct nhlt_format_config; + +/* + * Non HD Audio ACPI support. This table is typically used for Intel Smart + * Sound Technology DSP. It provides a way to encode opaque settings in + * the ACPI tables. + * + * While the structure fields of the NHLT structs are exposed below + * the SoC/chipset code should be the only other user manipulating the + * fields directly aside from the library itself. + * + * The NHLT table consists of endpoints which in turn contain different + * supporting stream formats. Each endpoint may contain a device specific + * configuration payload as well as each stream format. + * + * Most code should use the SoC variants of the functions because + * there is required logic needed to be performed by the SoC. The SoC + * code should be abstracting the inner details of these functions that + * specically apply to NHLT objects for that SoC. + * + * An example sequence: + * + * nhlt = nhlt_init() + * ep = nhlt_add_endpoint() + * nhlt_endpoint_append_config(ep) + * nhlt_endpoint_add_formats(ep) + * nhlt_soc_serialise() + */ + +/* Obtain an nhlt object for adding endpoints. Returns NULL on error. */ +struct nhlt *nhlt_init(void); + +/* Return the size of the NHLT table including ACPI header. */ +size_t nhlt_current_size(struct nhlt *nhlt); + +/* + * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor + * to drive the logic. + */ + +struct nhlt_endp_descriptor { + /* NHLT endpoint types. */ + int link; + int device; + int direction; + u16 vid; + u16 did; + /* Optional endpoint specific configuration data. */ + const void *cfg; + size_t cfg_size; + /* Formats supported for endpoint. */ + const struct nhlt_format_config *formats; + size_t num_formats; +}; + +/* + * Add the number of endpoints described by each descriptor. The virtual bus + * id for each descriptor is the default value of 0. + * Returns < 0 on error, 0 on success. + */ +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, + size_t num_epds); + +/* + * Add the number of endpoints associated with a single NHLT SSP instance id. + * Each endpoint described in the endpoint descriptor array uses the provided + * virtual bus id. Returns < 0 on error, 0 on success. + */ +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds); + +/* + * Add endpoint to NHLT object. Returns NULL on error. + * + * generic nhlt_add_endpoint() is called by the SoC code to provide + * the specific assumptions/uses for NHLT for that platform. All fields + * are the NHLT enumerations found within this header file. + */ +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, + int device_type, int dir, + u16 vid, u16 did); + +/* + * Append blob of configuration to the endpoint proper. Returns 0 on + * success, < 0 on error. A copy of the configuration is made so any + * resources pointed to by config can be freed after the call. + */ +int nhlt_endpoint_append_config(struct nhlt_endpoint *endpoint, + const void *config, size_t config_sz); + +/* Add a format type to the provided endpoint. Returns NULL on error. */ +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endpoint, + int num_channels, int sample_freq_khz, + int container_bits_per_sample, + int valid_bits_per_sample, + u32 speaker_mask); + +/* + * Append blob of configuration to the format proper. Returns 0 on + * success, < 0 on error. A copy of the configuration is made so any + * resources pointed to by config can be freed after the call. + */ +int nhlt_format_append_config(struct nhlt_format *format, const void *config, + size_t config_sz); + +/* + * Add num_formats described by formats to the endpoint. This function + * effectively wraps nhlt_add_format() and nhlt_format_config() using the + * data found in each nhlt_format_config object. Returns 0 on success, < 0 + * on error. + */ +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint, + const struct nhlt_format_config *formats, + size_t num_formats); + +/* + * Increment the instance id for a given link type. This function is + * used for marking a device being completely added to the NHLT object. + * Subsequent endpoints added to the nhlt object with the same link type + * will use incremented instance id. + */ +void nhlt_next_instance(struct nhlt *nhlt, int link_type); + +/* + * Serialize NHLT object to ACPI table. Take in the beginning address of where + * the table will reside and return the address of the next ACPI table. On + * error 0 will be returned. The NHLT object is no longer valid after this + * function is called. + */ +uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr); + +/* + * Serialize NHLT object to ACPI table. Take in the beginning address of where + * the table will reside oem_id and oem_table_id and return the address of the + * next ACPI table. On error 0 will be returned. The NHLT object is no longer + * valid after this function is called. + */ +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, + const char *oem_id, const char *oem_table_id, + u32 oem_revision); + +int nhlt_setup(struct nhlt *nhlt, ofnode node); + +/* Link and device types. */ +enum { + NHLT_LINK_HDA, + NHLT_LINK_DSP, + NHLT_LINK_PDM, + NHLT_LINK_SSP, + NHLT_MAX_LINK_TYPES, +}; + +enum { + NHLT_SSP_DEV_BT, /* Bluetooth */ + NHLT_SSP_DEV_MODEM, + NHLT_SSP_DEV_FM, + NHLT_SSP_DEV_RESERVED, + NHLT_SSP_DEV_I2S = 4, +}; + +enum { + NHLT_PDM_DEV, +}; + +/* Endpoint direction. */ +enum { + NHLT_DIR_RENDER, + NHLT_DIR_CAPTURE, + NHLT_DIR_BIDIRECTIONAL, +}; + +/* + * Channel mask for an endpoint. While they are prefixed with 'SPEAKER' the + * channel masks are also used for capture devices + */ +enum { + SPEAKER_FRONT_LEFT = BIT(0), + SPEAKER_FRONT_RIGHT = BIT(1), + SPEAKER_FRONT_CENTER = BIT(2), + SPEAKER_LOW_FREQUENCY = BIT(3), + SPEAKER_BACK_LEFT = BIT(4), + SPEAKER_BACK_RIGHT = BIT(5), + SPEAKER_FRONT_LEFT_OF_CENTER = BIT(6), + SPEAKER_FRONT_RIGHT_OF_CENTER = BIT(7), + SPEAKER_BACK_CENTER = BIT(8), + SPEAKER_SIDE_LEFT = BIT(9), + SPEAKER_SIDE_RIGHT = BIT(10), + SPEAKER_TOP_CENTER = BIT(11), + SPEAKER_TOP_FRONT_LEFT = BIT(12), + SPEAKER_TOP_FRONT_CENTER = BIT(13), + SPEAKER_TOP_FRONT_RIGHT = BIT(14), + SPEAKER_TOP_BACK_LEFT = BIT(15), + SPEAKER_TOP_BACK_CENTER = BIT(16), + SPEAKER_TOP_BACK_RIGHT = BIT(17), +}; + +/* + * Supporting structures. Only SoC/chipset and the library code directly should + * be manipulating these structures + */ +struct sub_format { + u32 data1; + u16 data2; + u16 data3; + u8 data4[8]; +}; + +struct nhlt_specific_config { + u32 size; + void *capabilities; +}; + +struct nhlt_waveform { + u16 tag; + u16 num_channels; + u32 samples_per_second; + u32 bytes_per_second; + u16 block_align; + u16 bits_per_sample; + u16 extra_size; + u16 valid_bits_per_sample; + u32 channel_mask; + struct sub_format sub_format; +}; + +struct nhlt_format { + struct nhlt_waveform waveform; + struct nhlt_specific_config config; +}; + +/* + * This struct is used by nhlt_endpoint_add_formats() for easily adding + * waveform formats with associated settings file. + */ +struct nhlt_format_config { + int num_channels; + int sample_freq_khz; + int container_bits_per_sample; + int valid_bits_per_sample; + u32 speaker_mask; + const char *settings_file; +}; + +/* Arbitrary max number of formats per endpoint. */ +#define MAX_FORMATS 2 +struct nhlt_endpoint { + u32 length; + u8 link_type; + u8 instance_id; + u16 vendor_id; + u16 device_id; + u16 revision_id; + u32 subsystem_id; + u8 device_type; + u8 direction; + u8 virtual_bus_id; + struct nhlt_specific_config config; + u8 num_formats; + struct nhlt_format formats[MAX_FORMATS]; +}; + +#define MAX_ENDPOINTS 8 +struct nhlt { + u32 subsystem_id; + u8 num_endpoints; + struct nhlt_endpoint endpoints[MAX_ENDPOINTS]; + u8 current_instance_id[NHLT_MAX_LINK_TYPES]; +}; + +struct nhlt_tdm_config { + u8 virtual_slot; + u8 config_type; +}; + +enum { + NHLT_TDM_BASIC, + NHLT_TDM_MIC_ARRAY, +}; + +struct nhlt_dmic_array_config { + struct nhlt_tdm_config tdm_config; + u8 array_type; +}; + +/* + * Microphone array definitions may be found here: + * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85... + */ +enum { + NHLT_MIC_ARRAY_2CH_SMALL = 0xa, + NHLT_MIC_ARRAY_2CH_BIG = 0xb, + NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc, + NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd, + NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe, + NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf, +}; + +#endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 1079bf2022..1185a88c27 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,6 +22,7 @@ obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o +obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c new file mode 100644 index 0000000000..c64dd9c008 --- /dev/null +++ b/arch/x86/lib/acpi_nhlt.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + * + * Modified from coreboot nhlt.c + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include <common.h> +#include <binman.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <tables_csum.h> +#include <acpi/acpi_table.h> +#include <asm/acpi_nhlt.h> +#include <asm/unaligned.h> +#include <dm/acpi.h> + +#define NHLT_RID 1 +#define NHLT_SSID 1 +#define WAVEFORMAT_TAG 0xfffe +#define DEFAULT_VIRTUAL_BUS_ID 0 + +static const struct sub_format pcm_subformat = { + .data1 = 0x00000001, + .data2 = 0x0000, + .data3 = 0x0010, + .data4 = { 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 }, +}; + +struct nhlt *nhlt_init(void) +{ + struct nhlt *nhlt; + + nhlt = malloc(sizeof(*nhlt)); + + if (!nhlt) + return NULL; + + memset(nhlt, 0, sizeof(*nhlt)); + nhlt->subsystem_id = NHLT_SSID; + + return nhlt; +} + +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, + int device_type, int dir, + u16 vid, u16 did) +{ + struct nhlt_endpoint *endp; + + if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES) + return NULL; + + if (nhlt->num_endpoints >= MAX_ENDPOINTS) + return NULL; + + endp = &nhlt->endpoints[nhlt->num_endpoints]; + + endp->link_type = link_type; + endp->instance_id = nhlt->current_instance_id[link_type]; + endp->vendor_id = vid; + endp->device_id = did; + endp->revision_id = NHLT_RID; + endp->subsystem_id = nhlt->subsystem_id; + endp->device_type = device_type; + endp->direction = dir; + endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID; + + nhlt->num_endpoints++; + + return endp; +} + +static int append_specific_config(struct nhlt_specific_config *spec_cfg, + const void *config, size_t config_sz) +{ + size_t new_sz; + void *new_cfg; + + new_sz = spec_cfg->size + config_sz; + new_cfg = malloc(new_sz); + if (!new_cfg) + return -ENOMEM; + + /* Append new config */ + memcpy(new_cfg, spec_cfg->capabilities, spec_cfg->size); + memcpy(new_cfg + spec_cfg->size, config, config_sz); + + free(spec_cfg->capabilities); + + /* Update with new config data */ + spec_cfg->size = new_sz; + spec_cfg->capabilities = new_cfg; + + return 0; +} + +int nhlt_endpoint_append_config(struct nhlt_endpoint *endp, const void *config, + size_t config_sz) +{ + return append_specific_config(&endp->config, config, config_sz); +} + +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp, + int num_channels, int sample_freq_khz, + int container_bits_per_sample, + int valid_bits_per_sample, + uint32_t speaker_mask) +{ + struct nhlt_format *fmt; + struct nhlt_waveform *wave; + + if (endp->num_formats >= MAX_FORMATS) + return NULL; + + fmt = &endp->formats[endp->num_formats]; + wave = &fmt->waveform; + + wave->tag = WAVEFORMAT_TAG; + wave->num_channels = num_channels; + wave->samples_per_second = sample_freq_khz * 1000; + wave->bits_per_sample = container_bits_per_sample; + wave->extra_size = sizeof(wave->valid_bits_per_sample); + wave->extra_size += sizeof(wave->channel_mask); + wave->extra_size += sizeof(wave->sub_format); + wave->valid_bits_per_sample = valid_bits_per_sample; + wave->channel_mask = speaker_mask; + memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format)); + + /* Calculate the dervied fields */ + wave->block_align = wave->num_channels * wave->bits_per_sample / 8; + wave->bytes_per_second = wave->block_align * wave->samples_per_second; + + endp->num_formats++; + + return fmt; +} + +int nhlt_format_append_config(struct nhlt_format *fmt, const void *config, + size_t config_sz) +{ + return append_specific_config(&fmt->config, config, config_sz); +} + +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endp, + const struct nhlt_format_config *formats, + size_t num_formats) +{ + ofnode node; + size_t i; + + node = binman_section_find_node("private-files"); + + for (i = 0; i < num_formats; i++) { + const struct nhlt_format_config *cfg = &formats[i]; + struct nhlt_format *fmt; + void *data; + int size; + int ret; + + fmt = nhlt_add_format(endp, cfg->num_channels, + cfg->sample_freq_khz, + cfg->container_bits_per_sample, + cfg->valid_bits_per_sample, + cfg->speaker_mask); + if (!fmt) + return -ENOSPC; + + if (!cfg->settings_file) + continue; + + ret = binman_entry_map(node, cfg->settings_file, &data, &size); + if (ret) { + log_warning("Failed to find settings file %s\n", + cfg->settings_file); + return log_msg_ret("settings", ret); + } + + ret = nhlt_format_append_config(fmt, data, size); + if (ret) + return log_msg_ret("append", ret); + } + + return 0; +} + +void nhlt_next_instance(struct nhlt *nhlt, int link_type) +{ + if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES) + return; + + nhlt->current_instance_id[link_type]++; +} + +static size_t calc_specific_config_size(struct nhlt_specific_config *cfg) +{ + return sizeof(cfg->size) + cfg->size; +} + +static size_t calc_format_size(struct nhlt_format *fmt) +{ + size_t sz = 0; + + /* Wave format first */ + sz += sizeof(fmt->waveform.tag); + sz += sizeof(fmt->waveform.num_channels); + sz += sizeof(fmt->waveform.samples_per_second); + sz += sizeof(fmt->waveform.bytes_per_second); + sz += sizeof(fmt->waveform.block_align); + sz += sizeof(fmt->waveform.bits_per_sample); + sz += sizeof(fmt->waveform.extra_size); + sz += sizeof(fmt->waveform.valid_bits_per_sample); + sz += sizeof(fmt->waveform.channel_mask); + sz += sizeof(fmt->waveform.sub_format); + + sz += calc_specific_config_size(&fmt->config); + + return sz; +} + +static size_t calc_endpoint_size(struct nhlt_endpoint *endp) +{ + int i; + size_t sz = 0; + + sz += sizeof(endp->length) + sizeof(endp->link_type); + sz += sizeof(endp->instance_id) + sizeof(endp->vendor_id); + sz += sizeof(endp->device_id) + sizeof(endp->revision_id); + sz += sizeof(endp->subsystem_id) + sizeof(endp->device_type); + sz += sizeof(endp->direction) + sizeof(endp->virtual_bus_id); + sz += calc_specific_config_size(&endp->config); + sz += sizeof(endp->num_formats); + + for (i = 0; i < endp->num_formats; i++) + sz += calc_format_size(&endp->formats[i]); + + /* Adjust endpoint length to reflect current configuration */ + endp->length = sz; + + return sz; +} + +static size_t calc_endpoints_size(struct nhlt *nhlt) +{ + size_t sz = 0; + int i; + + for (i = 0; i < nhlt->num_endpoints; i++) + sz += calc_endpoint_size(&nhlt->endpoints[i]); + + return sz; +} + +static size_t calc_size(struct nhlt *nhlt) +{ + return sizeof(nhlt->num_endpoints) + calc_endpoints_size(nhlt); +} + +size_t nhlt_current_size(struct nhlt *nhlt) +{ + return calc_size(nhlt) + sizeof(struct acpi_table_header); +} + +static void nhlt_free_resources(struct nhlt *nhlt) +{ + int i, j; + + /* Free all specific configs */ + for (i = 0; i < nhlt->num_endpoints; i++) { + struct nhlt_endpoint *endp = &nhlt->endpoints[i]; + + free(endp->config.capabilities); + for (j = 0; j < endp->num_formats; j++) { + struct nhlt_format *fmt = &endp->formats[j]; + + free(fmt->config.capabilities); + } + } + + /* Free nhlt object proper */ + free(nhlt); +} + +struct cursor { + u8 *buf; +}; + +static void ser8(struct cursor *cur, uint val) +{ + *cur->buf = val; + cur->buf += sizeof(val); +} + +static void ser16(struct cursor *cur, uint val) +{ + put_unaligned_le16(val, cur->buf); + cur->buf += sizeof(val); +} + +static void ser32(struct cursor *cur, uint val) +{ + put_unaligned_le32(val, cur->buf); + cur->buf += sizeof(val); +} + +static void serblob(struct cursor *cur, void *from, size_t sz) +{ + memcpy(cur->buf, from, sz); + cur->buf += sz; +} + +static void serialise_specific_config(struct nhlt_specific_config *cfg, + struct cursor *cur) +{ + ser32(cur, cfg->size); + serblob(cur, cfg->capabilities, cfg->size); +} + +static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur) +{ + ser16(cur, wave->tag); + ser16(cur, wave->num_channels); + ser32(cur, wave->samples_per_second); + ser32(cur, wave->bytes_per_second); + ser16(cur, wave->block_align); + ser16(cur, wave->bits_per_sample); + ser16(cur, wave->extra_size); + ser16(cur, wave->valid_bits_per_sample); + ser32(cur, wave->channel_mask); + ser32(cur, wave->sub_format.data1); + ser16(cur, wave->sub_format.data2); + ser16(cur, wave->sub_format.data3); + serblob(cur, wave->sub_format.data4, sizeof(wave->sub_format.data4)); +} + +static void serialise_format(struct nhlt_format *fmt, struct cursor *cur) +{ + serialise_waveform(&fmt->waveform, cur); + serialise_specific_config(&fmt->config, cur); +} + +static void serialise_endpoint(struct nhlt_endpoint *endp, struct cursor *cur) +{ + int i; + + ser32(cur, endp->length); + ser8(cur, endp->link_type); + ser8(cur, endp->instance_id); + ser16(cur, endp->vendor_id); + ser16(cur, endp->device_id); + ser16(cur, endp->revision_id); + ser32(cur, endp->subsystem_id); + ser8(cur, endp->device_type); + ser8(cur, endp->direction); + ser8(cur, endp->virtual_bus_id); + serialise_specific_config(&endp->config, cur); + ser8(cur, endp->num_formats); + + for (i = 0; i < endp->num_formats; i++) + serialise_format(&endp->formats[i], cur); +} + +static void nhlt_serialise_endpoints(struct nhlt *nhlt, struct cursor *cur) +{ + int i; + + ser8(cur, nhlt->num_endpoints); + + for (i = 0; i < nhlt->num_endpoints; i++) + serialise_endpoint(&nhlt->endpoints[i], cur); +} + +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, + const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) +{ + struct cursor cur; + struct acpi_table_header *header; + size_t sz; + size_t oem_id_len; + size_t oem_table_id_len; + int ret; + + log_info("ACPI: * NHLT\n"); + sz = nhlt_current_size(nhlt); + + /* Create header */ + header = (void *)ctx->current; + memset(header, '\0', sizeof(struct acpi_table_header)); + acpi_fill_header(header, "NHLT"); + header->length = sz; + header->revision = acpi_get_table_revision(ACPITAB_NHLT); + + if (oem_id) { + oem_id_len = min((int)strlen(oem_id), 6); + memcpy(header->oem_id, oem_id, oem_id_len); + } + if (oem_table_id) { + oem_table_id_len = min((int)strlen(oem_table_id), 8); + memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); + } + header->oem_revision = oem_revision; + + cur.buf = (void *)(header + 1); + nhlt_serialise_endpoints(nhlt, &cur); + + header->checksum = table_compute_checksum(header, sz); + nhlt_free_resources(nhlt); + + ret = acpi_add_table(ctx, ctx->current); + if (ret) + return log_msg_ret("add", ret); + acpi_inc_align(ctx, sz); + + return 0; +} + +static int _nhlt_add_single_endpoint(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epd) +{ + struct nhlt_endpoint *endp; + int ret; + + endp = nhlt_add_endpoint(nhlt, epd->link, epd->device, epd->direction, + epd->vid, epd->did); + if (!endp) + return -EINVAL; + + endp->virtual_bus_id = virtual_bus_id; + + ret = nhlt_endpoint_append_config(endp, epd->cfg, epd->cfg_size); + if (ret) + return ret; + + ret = nhlt_endpoint_add_formats(endp, epd->formats, epd->num_formats); + if (ret) + return log_msg_ret("formats", ret); + + return 0; +} + +static int _nhlt_add_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + size_t i; + int ret; + + for (i = 0; i < num_epds; i++) { + ret = _nhlt_add_single_endpoint(nhlt, virtual_bus_id, &epds[i]); + if (ret) + return log_ret(ret); + } + + return 0; +} + +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, size_t num_epds) +{ + int ret; + + ret = _nhlt_add_endpoints(nhlt, DEFAULT_VIRTUAL_BUS_ID, epds, num_epds); + + return ret; +} + +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + int ret; + + ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds); + if (!ret) + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return ret; +}

This chip is used on coral and we need to generate ACPI tables for sound to make it work. Add a driver that does just this (i.e. at present does not actually support playing sound).

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: Add a comment about only x86 boards supporting NHLT

Changes in v1: - Use acpi,ddn instead of acpi,desc - Drop the unwanted acpi_device_write_gpio_desc() - Rename max97357a to max98357a - Add NHLT support - Capitalise ACPI_OPS_PTR - Rebase to master

configs/sandbox_defconfig | 1 + doc/device-tree-bindings/sound/max98357a.txt | 22 +++ drivers/sound/Kconfig | 9 ++ drivers/sound/Makefile | 1 + drivers/sound/max98357a.c | 161 +++++++++++++++++++ 5 files changed, 194 insertions(+) create mode 100644 doc/device-tree-bindings/sound/max98357a.txt create mode 100644 drivers/sound/max98357a.c

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 3817091d02..0c9524ff6c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -207,6 +207,7 @@ CONFIG_SMEM=y CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y +CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_SANDBOX=y CONFIG_SANDBOX_SPI=y CONFIG_SPMI=y diff --git a/doc/device-tree-bindings/sound/max98357a.txt b/doc/device-tree-bindings/sound/max98357a.txt new file mode 100644 index 0000000000..4bce14ce80 --- /dev/null +++ b/doc/device-tree-bindings/sound/max98357a.txt @@ -0,0 +1,22 @@ +Maxim MAX98357A audio DAC + +This node models the Maxim MAX98357A DAC. + +Required properties: +- compatible : "maxim,max98357a" + +Optional properties: +- sdmode-gpios : GPIO specifier for the chip's SD_MODE pin. + If this option is not specified then driver does not manage + the pin state (e.g. chip is always on). +- sdmode-delay : specify delay time for SD_MODE pin. + If this option is specified, which means it's required i2s clocks + ready before SD_MODE is unmuted in order to avoid the speaker pop noise. + It's observed that 5ms is sufficient. + +Example: + +max98357a { + compatible = "maxim,max98357a"; + sdmode-gpios = <&qcom_pinmux 25 0>; +}; diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 7f214b97be..0948d8caab 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -113,6 +113,15 @@ config SOUND_MAX98095 audio data and I2C for codec control. At present it only works with the Samsung I2S driver.

+config SOUND_MAX98357A + bool "Support Maxim max98357a audio codec" + depends on PCI + help + Enable the max98357a audio codec. This is connected on PCI for + audio data codec control. This is currently only capable of providing + ACPI information. A full driver (with sound in U-Boot) is currently + not available. + config SOUND_RT5677 bool "Support Realtek RT5677 audio codec" depends on SOUND diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 8c3933ad15..9b40c8012f 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o +obj-$(CONFIG_SOUND_MAX98357A) += max98357a.o obj-$(CONFIG_SOUND_INTEL_HDA) += hda_codec.o obj-$(CONFIG_SOUND_I8254) += i8254_beep.o obj-$(CONFIG_SOUND_RT5677) += rt5677.o diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c new file mode 100644 index 0000000000..827262d235 --- /dev/null +++ b/drivers/sound/max98357a.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * max98357a.c -- MAX98357A Audio driver + * + * Copyright 2019 Google LLC + * Parts taken from coreboot + */ + +#include <common.h> +#include <audio_codec.h> +#include <dm.h> +#include <log.h> +#include <sound.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <acpi/acpi_dp.h> +#include <asm-generic/gpio.h> +#ifdef CONFIG_X86 +#include <asm/acpi_nhlt.h> +#endif +#include <dt-bindings/sound/nhlt.h> +#include <dm/acpi.h> + +struct max98357a_priv { + struct gpio_desc sdmode_gpio; +}; + +static int max98357a_ofdata_to_platdata(struct udevice *dev) +{ + struct max98357a_priv *priv = dev_get_priv(dev); + int ret; + + ret = gpio_request_by_name(dev, "sdmode-gpios", 0, &priv->sdmode_gpio, + GPIOD_IS_IN); + if (ret) + return log_msg_ret("gpio", ret); + + return 0; +} + +static int max98357a_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct max98357a_priv *priv = dev_get_priv(dev); + char scope[ACPI_PATH_MAX]; + char name[ACPI_NAME_MAX]; + char path[ACPI_PATH_MAX]; + struct acpi_dp *dp; + int ret; + + ret = acpi_device_scope(dev, scope, sizeof(scope)); + if (ret) + return log_msg_ret("scope", ret); + ret = acpi_get_name(dev, name); + if (ret) + return log_msg_ret("name", ret); + + /* Device */ + acpigen_write_scope(ctx, scope); + acpigen_write_device(ctx, name); + acpigen_write_name_string(ctx, "_HID", + dev_read_string(dev, "acpi,hid")); + acpigen_write_name_integer(ctx, "_UID", 0); + acpigen_write_name_string(ctx, "_DDN", + dev_read_string(dev, "acpi,ddn")); + acpigen_write_sta(ctx, acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name(ctx, "_CRS"); + acpigen_write_resourcetemplate_header(ctx); + ret = acpi_device_write_gpio_desc(ctx, &priv->sdmode_gpio); + if (ret) + return log_msg_ret("gpio", ret); + acpigen_write_resourcetemplate_footer(ctx); + + /* _DSD for devicetree properties */ + /* This points to the first pin in the first gpio entry in _CRS */ + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, + priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ? + ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH); + acpi_dp_add_integer(dp, "sdmode-delay", + dev_read_u32_default(dev, "sdmode-delay", 0)); + acpi_dp_write(ctx, dp); + + acpigen_pop_len(ctx); /* Device */ + acpigen_pop_len(ctx); /* Scope */ + + return 0; +} + +/* For now only X86 boards support NHLT */ +#ifdef CONFIG_X86 +static const struct nhlt_format_config max98357a_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.dat", + }, +}; + +static const struct nhlt_endp_descriptor max98357a_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357a_formats, + .num_formats = ARRAY_SIZE(max98357a_formats), + }, +}; + +static int max98357a_acpi_setup_nhlt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + u32 hwlink; + int ret; + + if (dev_read_u32(dev, "acpi,audio-link", &hwlink)) + return log_msg_ret("link", -EINVAL); + + /* Virtual bus id of SSP links are the hardware port ids proper. */ + ret = nhlt_add_ssp_endpoints(ctx->nhlt, hwlink, max98357a_descriptors, + ARRAY_SIZE(max98357a_descriptors)); + if (ret) + return log_msg_ret("add", ret); + + return 0; +} +#endif + +struct acpi_ops max98357a_acpi_ops = { + .fill_ssdt = max98357a_acpi_fill_ssdt, +#ifdef CONFIG_X86 + .setup_nhlt = max98357a_acpi_setup_nhlt, +#endif +}; + +static const struct audio_codec_ops max98357a_ops = { +}; + +static const struct udevice_id max98357a_ids[] = { + { .compatible = "maxim,max98357a" }, + { } +}; + +U_BOOT_DRIVER(max98357a) = { + .name = "max98357a", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98357a_ids, + .ofdata_to_platdata = max98357a_ofdata_to_platdata, + .ops = &max98357a_ops, + ACPI_OPS_PTR(&max98357a_acpi_ops) +};

Add information about what is returned on error.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/x86/include/asm/intel_pinctrl.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h index b5564b9ee1..a6a9edd0d4 100644 --- a/arch/x86/include/asm/intel_pinctrl.h +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset); * @pad: Pad to check * @devp: Returns pinctrl device containing that pad * @offsetp: Returns offset of pad within that pinctrl device + * @return 0 if OK, -ENOTBLK if pad number is invalid */ int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);

Add a Kconfig to control whether pinctrl is represented as a single ACPI device or as multiple devices. In the latter case (the default) we should return the pin number relative to the pinctrl device.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Add help for CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES

drivers/pinctrl/intel/Kconfig | 12 ++++++++++++ drivers/pinctrl/intel/pinctrl.c | 2 ++ 2 files changed, 14 insertions(+)

diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index e62a2e0349..1acc5dabb0 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -15,6 +15,18 @@ config INTEL_PINCTRL_IOSTANDBY bool default y

+config INTEL_PINCTRL_MULTI_ACPI_DEVICES + bool + default y + help + Enable this if the pinctrl devices are modelled as multiple, + separate ACPI devices in the ACPI tables. If enabled, the ACPI + devices match the U-Boot pinctrl devices and the pin 'offset' is + relatove to a particular pinctrl device. If disabled, there is a + single ACPI pinctrl device which includes all U-Boot pinctrl devices + and the pin 'offset' is in effect a global pin number. + + config PINCTRL_INTEL_APL bool "Support Intel Apollo Lake (APL)" help diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index bf3989bf32..32ca303b27 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -427,6 +427,8 @@ int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset) const struct pad_community *comm = priv->comm; int group;

+ if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES)) + return offset; group = pinctrl_group_index(comm, offset);

/* If pad base is not set then use GPIO number as ACPI pin number */

At present the itss is probed in the ofdata_to_platdata() method. This is incorrect since itss is a child of p2sb which itself needs to probe the pinctrl device. This means that p2sb is effectively not probed when the itss is probed, so we get the wrong register address from p2sb.

Fix this by moving the itss probe to the correct place.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

drivers/pinctrl/intel/pinctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index 32ca303b27..ba21c9dcc2 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -619,15 +619,11 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, { struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); struct intel_pinctrl_priv *priv = dev_get_priv(dev); - int ret;

if (!comm) { log_err("Cannot find community for pid %d\n", pplat->pid); return -EDOM; } - ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss); - if (ret) - return log_msg_ret("Cannot find ITSS", ret); priv->comm = comm; priv->num_cfgs = num_cfgs;

@@ -637,8 +633,12 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, int intel_pinctrl_probe(struct udevice *dev) { struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int ret;

priv->itss_pol_cfg = true; + ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss); + if (ret) + return log_msg_ret("Cannot find ITSS", ret);

return 0; }

Use the new binman memory-mapping function to access the VBT, to simplify the code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

arch/x86/cpu/apollolake/fsp_s.c | 19 +++++-------------- arch/x86/lib/fsp2/fsp_silicon_init.c | 1 + 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 13e6b20f08..0f5520fc7d 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -36,29 +36,20 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset, ofnode node;

if (IS_ENABLED(CONFIG_HAVE_VBT)) { - struct binman_entry vbt; - void *vbt_buf; + void *buf; int ret;

- ret = binman_entry_find("intel-vbt", &vbt); + ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL); if (ret) return log_msg_ret("Cannot find VBT", ret); - vbt.image_pos += rom_offset; - vbt_buf = malloc(vbt.size); - if (!vbt_buf) - return log_msg_ret("Alloc VBT", -ENOMEM); + if (*(u32 *)buf != VBT_SIGNATURE) + return log_msg_ret("VBT signature", -EINVAL);

/* * Load VBT before devicetree-specific config. This only * supports memory-mapped SPI at present. */ - bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); - memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size); - bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); - if (*(u32 *)vbt_buf != VBT_SIGNATURE) - return log_msg_ret("VBT signature", -EINVAL); - - cfg->graphics_config_ptr = (ulong)vbt_buf; + cfg->graphics_config_ptr = (ulong)buf; }

node = dev_read_subnode(dev, "fsp-s"); diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index 45c0c7d90b..0f221a864f 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -32,6 +32,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash) &rom_offset); if (ret) return log_msg_ret("locate FSP", ret); + binman_set_rom_offset(rom_offset); gd->arch.fsp_s_hdr = hdr;

/* Copy over the default config */

Add a few of these calls to make it easier to see where an error occurs, if CONFIG_LOG_ERROR_RETURN is enabled.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Heiko Schocher hs@denx.de ---

(no changes since v1)

drivers/i2c/i2c-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 8bc69e870f..2373aa2ea4 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -458,7 +458,7 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len) struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);

if (offset_len > I2C_MAX_OFFSET_LEN) - return -EINVAL; + return log_ret(-EINVAL); chip->offset_len = offset_len;

return 0; @@ -625,7 +625,7 @@ int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip) if (addr == -1) { debug("%s: I2C Node '%s' has no 'reg' property %s\n", __func__, dev_read_name(dev), dev->name); - return -EINVAL; + return log_ret(-EINVAL); } chip->chip_addr = addr;

The P2SB bus needs to be hidden in some cases so that it does not get auto-configured by Linux. Add a method for this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Tested-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

drivers/misc/p2sb-uclass.c | 10 ++++++++++ include/p2sb.h | 25 ++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index d5fe12ebd8..b5219df46b 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -18,6 +18,16 @@

#define PCR_COMMON_IOSF_1_0 1

+int p2sb_set_hide(struct udevice *dev, bool hide) +{ + struct p2sb_ops *ops = p2sb_get_ops(dev); + + if (!ops->set_hide) + return -ENOSYS; + + return ops->set_hide(dev, hide); +} + void *pcr_reg_address(struct udevice *dev, uint offset) { struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); diff --git a/include/p2sb.h b/include/p2sb.h index 74eb08b7ff..93e1155dca 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -31,13 +31,36 @@ struct p2sb_uc_priv { };

/** - * struct p2sb_ops - Operations for the P2SB (none at present) + * struct p2sb_ops - Operations for the P2SB */ struct p2sb_ops { + /** + * set_hide() - Set/clear the 'hide' bit on the p2sb + * + * This device can be hidden from the PCI bus if needed. This method + * can be called before the p2sb is probed. + * + * @dev: P2SB device + * @hide: true to hide the device, false to show it + * @return 0 if OK, -ve on error + */ + int (*set_hide)(struct udevice *dev, bool hide); };

#define p2sb_get_ops(dev) ((struct p2sb_ops *)(dev)->driver->ops)

+/** + * p2sb_set_hide() - Set/clear the 'hide' bit on the p2sb + * + * This device can be hidden from the PCI bus if needed. This method + * can be called before the p2sb is probed. + * + * @dev: P2SB device + * @hide: true to hide the device, false to show it + * @return 0 if OK, -ve on error + */ +int p2sb_set_hide(struct udevice *dev, bool hide); + /** * pcr_read32/16/8() - Read from a PCR device *

This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Tested-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

arch/x86/cpu/intel_common/p2sb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index db3d70d92a..361d4c90cb 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -153,6 +153,17 @@ static int intel_p2sb_set_hide(struct udevice *dev, bool hide) return 0; }

+static int p2sb_remove(struct udevice *dev) +{ + int ret; + + ret = intel_p2sb_set_hide(dev, true); + if (ret) + return log_msg_ret("hide", ret); + + return 0; +} + static int p2sb_child_post_bind(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) @@ -183,10 +194,12 @@ U_BOOT_DRIVER(p2sb_drv) = { .id = UCLASS_P2SB, .of_match = p2sb_ids, .probe = p2sb_probe, + .remove = p2sb_remove, .ops = &p2sb_ops, .ofdata_to_platdata = p2sb_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), .per_child_platdata_auto_alloc_size = sizeof(struct p2sb_child_platdata), .child_post_bind = p2sb_child_post_bind, + .flags = DM_FLAG_OS_PREPARE, };

The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add mention of why log_msg_ret() is dropped

arch/x86/cpu/apollolake/fsp_s.c | 11 +++++------ arch/x86/cpu/cpu.c | 13 +++++++++++++ arch/x86/cpu/intel_common/itss.c | 25 +++++++++++++++++++++++-- arch/x86/include/asm/global_data.h | 1 + arch/x86/include/asm/itss.h | 2 +- drivers/misc/irq-uclass.c | 2 +- 6 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 3a54297a28..e54b0ac104 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -160,11 +160,6 @@ int arch_fsps_preinit(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* - * Snapshot the current GPIO IRQ polarities. FSP is setting a default - * policy that doesn't honour boards' requirements - */ - irq_snapshot_polarities(itss);

/* * Clear the GPI interrupt status and enable registers. These @@ -203,7 +198,11 @@ int arch_fsp_init_r(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* Restore GPIO IRQ polarities back to previous settings */ + + /* + * Restore GPIO IRQ polarities back to previous settings. This was + * stored in reserve_arch() - see X86_IRQT_ITSS + */ irq_restore_polarities(itss);

/* soc_init() */ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index baa7dae172..9bc243ebc8 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,7 @@ #include <dm.h> #include <errno.h> #include <init.h> +#include <irq.h> #include <log.h> #include <malloc.h> #include <syscon.h> @@ -274,6 +275,9 @@ int cpu_init_r(void) #ifndef CONFIG_EFI_STUB int reserve_arch(void) { + struct udevice *itss; + int ret; + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) mrccache_reserve();

@@ -291,6 +295,15 @@ int reserve_arch(void) fsp_save_s3_stack(); } } + ret = irq_first_device_type(X86_IRQT_ITSS, &itss); + if (!ret) { + /* + * Snapshot the current GPIO IRQ polarities. FSP-S is about to + * run and will set a default policy that doesn't honour boards' + * requirements + */ + irq_snapshot_polarities(itss); + }

return 0; } diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 963afa8f5b..fe84ebe29f 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev) int i;

reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);

+ log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot); for (i = reg_start; i < reg_end; i++) { uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;

priv->irq_snapshot[i] = pcr_read32(dev, reg); + log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg, + priv->irq_snapshot[i]); }

+ /* Save the snapshot for use after relocation */ + gd->start_addr_sp -= sizeof(*priv); + gd->start_addr_sp &= ~0xf; + gd->arch.itss_priv = (void *)gd->start_addr_sp; + memcpy(gd->arch.itss_priv, priv, sizeof(*priv)); + return 0; }

@@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg) static int restore_polarities(struct udevice *dev) { struct itss_priv *priv = dev_get_priv(dev); + struct itss_priv *old_priv; const int start = GPIO_IRQ_START; const int end = GPIO_IRQ_END; int reg_start; int reg_end; int i;

+ /* Get the snapshot which was stored by the pre-reloc device */ + old_priv = gd->arch.itss_priv; + if (!old_priv) + return log_msg_ret("priv", -EFAULT); + memcpy(priv->irq_snapshot, old_priv->irq_snapshot, + sizeof(priv->irq_snapshot)); + show_polarities(dev, "Before"); + log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);

reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); +

for (i = reg_start; i < reg_end; i++) { u32 mask; @@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev) mask &= ~((1U << irq_start) - 1);

reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n", + i, reg, mask, priv->irq_snapshot[i]); pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]); }

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 0e64c8a46d..5bc251c0dd 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -121,6 +121,7 @@ struct arch_global_data { #ifdef CONFIG_FSP_VERSION2 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ #endif + void *itss_priv; /* Private ITSS data pointer */ ulong acpi_start; /* Start address of ACPI tables */ };

diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h index c75d8fe8c2..f7d3240384 100644 --- a/arch/x86/include/asm/itss.h +++ b/arch/x86/include/asm/itss.h @@ -16,7 +16,7 @@

#define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC) +#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)

/* Max PXRC registers in ITSS */ #define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 8727a33dd9..94fa233f19 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -168,7 +168,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)

ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp); if (ret) - return log_msg_ret("find", ret); + return ret;

return 0; }

If there is MRC information we should run FSP-M with a different boot_mode flag since it is supposed to do a 'fast path' through the memory init. Fix this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Add a new commit to handle the boot_mode fix

arch/x86/cpu/apollolake/fsp_m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 65461d85b8..e19a2b0826 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -26,7 +26,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) return log_msg_ret("mrc", cache_ret); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION : + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;

node = dev_ofnode(dev); if (!ofnode_valid(node))

Update this code to calculate the address to use, rather than hard-coding it. Obtain the requested stack size from the FSP.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

Changes in v2: - Split out the boot_mode change into a separate patch

arch/x86/cpu/apollolake/fsp_m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index e19a2b0826..cef937573b 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -24,7 +24,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) cache_ret = prepare_mrc_cache(upd); if (cache_ret && cache_ret != -ENOENT) return log_msg_ret("mrc", cache_ret); - arch->stack_base = (void *)0xfef96000; + arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - + arch->stack_size); arch->boot_loader_tolum_size = 0; arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION : FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;

At present this information is used to locate and parse the tables but is not stored. Store it so that we can display it to the user, e.g. with the 'bdinfo' command.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

arch/x86/cpu/coreboot/tables.c | 8 +++++++- arch/x86/cpu/i386/cpu.c | 7 ++++++- arch/x86/include/asm/global_data.h | 1 + 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index a5d31d1dea..1594b4a8b2 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -10,6 +10,8 @@ #include <net.h> #include <asm/arch/sysinfo.h>

+DECLARE_GLOBAL_DATA_PTR; + /* * This needs to be in the .data section so that it's copied over during * relocation. By default it's put in the .bss section which is simply filled @@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info) if (addr < 0) return addr; ret = cb_parse_header((void *)addr, 0x1000, info); + if (!ret) + return -ENOENT; + gd->arch.coreboot_table = addr; + gd->flags |= GD_FLG_SKIP_LL_INIT;

- return ret == 1 ? 0 : -ENOENT; + return 0; } diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index fca3f79b69..8f342dd06e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -456,10 +456,15 @@ int x86_cpu_init_f(void)

int x86_cpu_reinit_f(void) { + long addr; + setup_identity(); setup_pci_ram_top(); - if (locate_coreboot_table() >= 0) + addr = locate_coreboot_table(); + if (addr >= 0) { + gd->arch.coreboot_table = addr; gd->flags |= GD_FLG_SKIP_LL_INIT; + }

return 0; } diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 5bc251c0dd..3e4044593c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,7 @@ struct arch_global_data { #endif void *itss_priv; /* Private ITSS data pointer */ ulong acpi_start; /* Start address of ACPI tables */ + ulong coreboot_table; /* Address of coreboot table */ };

#endif

At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr' command does not work correctly. It is not easy to make it work for all CPUs, since coreboot has halted them and we would need to start them up again, but it is easy enough to make them work on the boot CPU.

Update the code to avoid assuming that the MP init routine has completed, so that this can work.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/x86/cpu/mp_init.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 0f99a405bb..21fbe5bda5 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -558,7 +558,7 @@ static int get_bsp(struct udevice **devp, int *cpu_countp) if (cpu_countp) *cpu_countp = ret;

- return dev->req_seq; + return dev->req_seq >= 0 ? dev->req_seq : 0; }

/** @@ -718,9 +718,6 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg) int num_cpus; int ret;

- if (!(gd->flags & GD_FLG_SMP_READY)) - return -ENXIO; - ret = get_bsp(&dev, &num_cpus); if (ret < 0) return log_msg_ret("bsp", ret); @@ -730,6 +727,13 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg) func(arg); }

+ if (!(gd->flags & GD_FLG_SMP_READY)) { + /* Allow use of this function on the BSP only */ + if (cpu_select == MP_SELECT_BSP || !cpu_select) + return 0; + return -ENXIO; + } + /* Allow up to 1 second for all APs to finish */ ret = run_ap_work(&lcb, dev, num_cpus, 1000 /* ms */); if (ret)

The comment here applies only to FSP1, so update it.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

arch/x86/cpu/start.S | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 01524635e9..4ad515ce08 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -124,6 +124,7 @@ car_init_ret: #endif #else /* + * Instructions for FSP1, but not FSP2: * U-Boot enters here twice. For the first time it comes from * car_init_done() with esp points to a temporary stack and esi * set to zero. For the second time it comes from fsp_init_done()

This function sounds like something that is called when U-Boot is about to jump to Linux. In fact it is an init function.

Rename it to reduce confusion.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v1)

arch/x86/cpu/coreboot/coreboot.c | 4 ++-- arch/x86/cpu/cpu.c | 8 ++++---- arch/x86/cpu/efi/app.c | 2 +- arch/x86/cpu/quark/quark.c | 2 +- arch/x86/lib/fsp/fsp_common.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d44db1347b..22a93254a9 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -42,7 +42,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); }

-static void board_final_cleanup(void) +static void board_final_init(void) { /* * Un-cache the ROM so the kernel has one @@ -80,7 +80,7 @@ int last_stage_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init();

- board_final_cleanup(); + board_final_init();

return 0; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 9bc243ebc8..69c14189d1 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -182,10 +182,10 @@ void show_boot_progress(int val)

#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) /* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. + * Implement a weak default function for boards that need to do some final init + * before the system is ready. */ -__weak void board_final_cleanup(void) +__weak void board_final_init(void) { }

@@ -193,7 +193,7 @@ int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt;

- board_final_cleanup(); + board_final_init();

if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { fadt = acpi_find_fadt(); diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 10677ecbc2..f754489784 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -24,7 +24,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); }

-void board_final_cleanup(void) +void board_final_init(void) { }

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index ddad02e375..30b4711b9a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -363,7 +363,7 @@ int arch_misc_init(void) return 0; }

-void board_final_cleanup(void) +void board_final_init(void) { struct quark_rcba *rcba; u32 base, val; diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 8e3082d4c8..ea52954725 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -47,7 +47,7 @@ int fsp_init_phase_pci(void) return status ? -EPERM : 0; }

-void board_final_cleanup(void) +void board_final_init(void) { u32 status;