[U-Boot] [PATCH 01/15] MPC85xx: Add QE clk support

older
[U-Boot] [PATCH 03/14 v2] MPC85xx:...

Haiying Wang

20 May 2009 20 May '09

6:30 p.m.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Acked-by: Timur Tabi Timur@freescale.com --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/speed.c | 15 ++++++++++++++- include/asm-ppc/immap_85xx.h | 2 ++ include/e500.h | 1 + 4 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index ef976a4..b812d88 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,6 +184,10 @@ int checkcpu (void) printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif

+#ifdef CONFIG_QE + printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");

return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index b0f47e0..286b6b2 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo) uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; +#ifdef CONFIG_QE + u32 qe_ratio; +#endif

plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif

+#ifdef CONFIG_QE + qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) + >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; +#endif + #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -112,6 +121,10 @@ int get_clocks (void) gd->mem_clk = sys_info.freqDDRBus; gd->lbc_clk = sys_info.freqLocalBus;

+#ifdef CONFIG_QE + gd->qe_clk = sys_info.freqQE; + gd->brg_clk = gd->qe_clk / 2; +#endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, * there is no pattern that can be used to determine the frequency, so diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 0810b8e..a4d25cd 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1581,6 +1581,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif +#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ diff --git a/include/e500.h b/include/e500.h index 4c5eeb7..84b580d 100644 --- a/include/e500.h +++ b/include/e500.h @@ -18,6 +18,7 @@ typedef struct unsigned long freqSystemBus; unsigned long freqDDRBus; unsigned long freqLocalBus; + unsigned long freqQE; } MPC85xx_SYS_INFO;

#endif /* _ASMLANGUAGE */

-- 1.6.0.2

Show replies by date

Haiying Wang

20 May 20 May

6:30 p.m.

New subject: [U-Boot] [PATCH 02/15] MPC85xx: Fix MURAM size for MPC8569

MPC8569 has 128K bytes MURAM.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- include/asm-ppc/immap_qe.h | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 66a4735..55667ca 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -582,9 +582,12 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) +#if defined(CONFIG_MPC8568) u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ +#elif defined(CONFIG_MPC8569) + u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ + u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ #else u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ @@ -594,8 +597,10 @@ typedef struct qe_immap {

extern qe_map_t *qe_immr;

-#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) +#if defined(CONFIG_MPC8568) #define QE_MURAM_SIZE 0x10000UL +#elif defined(CONFIG_MPC8569) +#define QE_MURAM_SIZE 0x20000UL #elif defined(CONFIG_MPC8360) #define QE_MURAM_SIZE 0xc000UL #elif defined(CONFIG_MPC832X)

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 03/15] MPC85xx: Fix some settings for MPC8569MDS board

- Change the CONFIG_SYS_CLK_FREQ and CONFIG_DDR_CLK_FREQ to 66666666 since the on-board oscillator's freq is 66.666MHz. - Increase the size of malloc to 512KB because MPC8569MDS needs more memory for malloc to support up to eight Ethernet interfaces. - Move Environment address out of uboot thus the saved environment variables will not be erased after u-boot is re-programmed.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Signed-off-by: Dave Liu daveliu@freescale.com --- include/configs/MPC8569MDS.h | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..ea996ff 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -55,8 +55,8 @@ extern unsigned long get_clock_freq(void); #endif /* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_DDR_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ

/* * These can be toggled for performance analysis, otherwise use default. @@ -194,7 +194,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */

/* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -327,9 +327,9 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 04/15] MPC85xx: Add PIB support at CS4/CS5 for MPC8569MDS

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Signed-off-by: Yu Liu Yu.Liu@freescale.com --- include/configs/MPC8569MDS.h | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ea996ff..c87e51d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -156,10 +156,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR0_PRELIM 0xfe000801 #define CONFIG_SYS_OR0_PRELIM 0xfe000ff7

-/*Chip slelect 1 - BCSR*/ +/*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7

+/*Chip select 4 - PIB*/ +#define CONFIG_SYS_BR4_PRELIM 0xf8008801 +#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 + +/*Chip select 5 - PIB*/ +#define CONFIG_SYS_BR5_PRELIM 0xf8010801 +#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 05/15] MPC85xx: Add UART1 support for MPC8569MDS

MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define those pins before using UART1.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- board/freescale/mpc8569mds/mpc8569mds.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 129c58c..7e6cfb7 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -77,6 +77,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */

+ /* UART1 is muxed with QE PortF bit [9-12].*/ + {5, 12, 2, 0, 3}, /* UART1_SIN */ + {5, 9, 1, 0, 3}, /* UART1_SOUT */ + {5, 10, 2, 0, 3}, /* UART1_CTS_B */ + {5, 11, 1, 0, 2}, /* UART1_RTS_B */ + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ };

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 06/15] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Acked-by: Timur Tabi timur@freescale.com --- drivers/qe/qe.c | 3 --- drivers/qe/qe.h | 17 +++++++++++------ drivers/qe/uec.c | 32 +++++++++++++++++++++++++++++++- drivers/qe/uec.h | 4 ++-- include/asm-ppc/immap_qe.h | 8 ++++++++ 5 files changed, 52 insertions(+), 12 deletions(-)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index f114fe0..30fe726 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num) return 0; }

-/* The maximum number of RISCs we support */ -#define MAX_QE_RISC 2 - /* Firmware information stored here for qe_get_firmware_info() */ static struct qe_firmware_info qe_firmware_info;

diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index d78edba..2128f56 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * based on source code of Shlomi Gridish @@ -46,11 +46,16 @@ typedef struct qe_snum {

/* QE RISC allocation */ -typedef enum qe_risc_allocation { - QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ - QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ - QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */ -} qe_risc_allocation_e; +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4)

/* QE CECR commands for UCC fast. */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index bba3ef2..eadcc2c 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * @@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC1_PHY_ADDR, @@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC2_PHY_ADDR, @@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC3_PHY_ADDR, @@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC4_PHY_ADDR, @@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC5_PHY_ADDR, @@ -161,8 +186,13 @@ static uec_info_t eth6_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC6_PHY_ADDR, diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 0b64499..411f0d2 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -654,8 +654,8 @@ typedef struct uec_info { ucc_fast_info_t uf_info; uec_num_of_threads_e num_threads_tx; uec_num_of_threads_e num_threads_rx; - qe_risc_allocation_e riscTx; - qe_risc_allocation_e riscRx; + unsigned int riscTx; + unsigned int riscRx; u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 55667ca..7613b5c 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -607,4 +607,12 @@ extern qe_map_t *qe_immr; #define QE_MURAM_SIZE 0x4000UL #endif

+#if defined(CONFIG_MPC8323) +#define MAX_QE_RISC 1 +#elif defined(CONFIG_MPC8569) +#define MAX_QE_RISC 4 +#else +#define MAX_QE_RISC 2 +#endif + #endif /* __IMMAP_QE_H__ */

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 07/15] drivers/qe: Add more SNUM number for QE

Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII- 1000 mode.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Acked-by: Timur Tabi timur@freescale.com --- drivers/qe/qe.c | 15 ++++++++++++--- drivers/qe/qe.h | 1 - include/asm-ppc/immap_qe.h | 5 ++++- 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 30fe726..beeb189 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * based on source code of Shlomi Gridish @@ -108,14 +108,23 @@ static void qe_sdma_init(void) out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT)); }

-static u8 thread_snum[QE_NUM_OF_SNUM] = { +/* This table is a list of the serial numbers of the Threads, taken from the + * "SNUM Table" chart in the QE Reference Manual. The order is not important, + * we just need to know what the SNUMs are for the threads. + */ +static u8 thread_snum[] = { 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, 0x34, 0x35, 0x88, 0x89, 0x98, 0x99, 0xa8, 0xa9, 0xb8, 0xb9, 0xc8, 0xc9, - 0xd8, 0xd9, 0xe8, 0xe9 + 0xd8, 0xd9, 0xe8, 0xe9, + 0x08, 0x09, 0x18, 0x19, + 0x28, 0x29, 0x38, 0x39, + 0x48, 0x49, 0x58, 0x59, + 0x68, 0x69, 0x78, 0x79, + 0x80, 0x81 };

static void qe_snums_init(void) diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 2128f56..faad43c 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -25,7 +25,6 @@

#include "common.h"

-#define QE_NUM_OF_SNUM 28 #define QE_NUM_OF_BRGS 16 #define UCC_MAX_NUM 8

diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 7613b5c..6e7f392 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -3,7 +3,7 @@ * The Internal Memory Map for devices with QE on them. This * is the superset of all QE devices (8360, etc.). * - * Copyright (c) 2006 Freescale Semiconductor, Inc. + * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. * Author: Shlomi Gridih gridish@freescale.com * * This program is free software; you can redistribute it and/or modify it @@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;

#if defined(CONFIG_MPC8323) #define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_MPC8569) #define MAX_QE_RISC 4 +#define QE_NUM_OF_SNUM 46 #else #define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 #endif

#endif /* __IMMAP_QE_H__ */

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 08/15] MPC85xx: Add UEC3 and UEC4 support for MPC8569MDS

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- board/freescale/mpc8569mds/bcsr.c | 4 ++++ board/freescale/mpc8569mds/mpc8569mds.c | 30 ++++++++++++++++++++++++++++++ include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++ 3 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index 5adffc2..f133732 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -41,6 +41,10 @@ void enable_8569mds_qe_mdio() BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); }

void disable_8569mds_brd_eeprom_write_protect() diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 7e6cfb7..387ecad 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -77,6 +77,36 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */

+ /* UCC_3_RGMII */ + {2, 11, 2, 0, 1}, /* CLK12 */ + {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ + {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ + {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ + {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ + {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ + {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ + {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ + {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ + {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ + {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ + {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ + {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ + + /* UCC_4_RGMII */ + {2, 16, 2, 0, 3}, /* CLK17 */ + {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ + {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ + {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ + {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ + {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ + {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ + {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ + {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ + {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ + {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ + {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ + {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ + /* UART1 is muxed with QE PortF bit [9-12].*/ {5, 12, 2, 0, 3}, /* UART1_SIN */ {5, 9, 1, 0, 3}, /* UART1_SOUT */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index c87e51d..7208c78 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -313,6 +313,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif

+#define CONFIG_UEC_ETH3 /* GETH3 */ +#define CONFIG_HAS_ETH2 + +#ifdef CONFIG_UEC_ETH3 +#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC3_PHY_ADDR 2 +#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID +#endif + +#define CONFIG_UEC_ETH4 /* GETH4 */ +#define CONFIG_HAS_ETH3 + +#ifdef CONFIG_UEC_ETH4 +#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC4_PHY_ADDR 3 +#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID +#endif #endif /* CONFIG_QE */

#if defined(CONFIG_PCI)

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 09/15] MPC85xx: Add RMII support for MPC8569MDS

This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to enalbe_mpc8569mds_qe_uec which is more accurate.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- board/freescale/mpc8569mds/bcsr.c | 15 +++++- board/freescale/mpc8569mds/bcsr.h | 2 +- board/freescale/mpc8569mds/mpc8569mds.c | 96 ++++++++++++++++++++++++++++++- include/configs/MPC8569MDS.h | 38 +++++++++++- 4 files changed, 144 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index f133732..b895b4e 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -35,8 +35,9 @@ void disable_8569mds_flash_write() clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); }

-void enable_8569mds_qe_mdio() +void enable_8569mds_qe_uec() { +#if defined(CONFIG_SYS_UCC_RGMII_MODE) setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), @@ -45,6 +46,18 @@ void enable_8569mds_qe_mdio() BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); +#elif defined(CONFIG_SYS_UCC_RMII_MODE) + /* Set UCC1-4 working at RMII mode */ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), + BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), + BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); +#endif }

void disable_8569mds_brd_eeprom_write_protect() diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index 8efe9bd..e5d63c7 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -76,7 +76,7 @@

void enable_8569mds_flash_write(void); void disable_8569mds_flash_write(void); -void enable_8569mds_qe_mdio(void); +void enable_8569mds_qe_uec(void); void disable_8569mds_brd_eeprom_write_protect(void);

#endif /* __BCSR_H_ */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 387ecad..1e7526a 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDIO */ {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */

+#if defined(CONFIG_SYS_UCC_RGMII_MODE) /* UCC_1_RGMII */ {2, 11, 2, 0, 1}, /* CLK12 */ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ @@ -107,6 +108,44 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */

+#elif defined(CONFIG_SYS_UCC_RMII_MODE) + /* UCC_1_RMII */ + {2, 15, 2, 0, 1}, /* CLK16 */ + {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ + + /* UCC_2_RMII */ + {2, 15, 2, 0, 1}, /* CLK16 */ + {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ + {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ + {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ + {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ + {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ + {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ + + /* UCC_3_RMII */ + {2, 15, 2, 0, 1}, /* CLK16 */ + {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ + {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ + {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ + {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ + {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ + {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ + + /* UCC_4_RMII */ + {2, 15, 2, 0, 1}, /* CLK16 */ + {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ + {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ + {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ + {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ + {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ + {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ +#endif + /* UART1 is muxed with QE PortF bit [9-12].*/ {5, 12, 2, 0, 3}, /* UART1_SIN */ {5, 9, 1, 0, 3}, /* UART1_SOUT */ @@ -128,7 +167,7 @@ int board_early_init_f (void) enable_8569mds_flash_write();

#ifdef CONFIG_QE - enable_8569mds_qe_mdio(); + enable_8569mds_qe_uec(); #endif

#if CONFIG_SYS_I2C2_OFFSET @@ -350,6 +389,61 @@ pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_SYS_UCC_RMII_MODE) + int nodeoff, off, err; + unsigned int val; + const u32 *ph; + const u32 *index; + + /* fixup device tree for supporting rmii mode */ + nodeoff = -1; + while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, + "ucc_geth")) >= 0) { + err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", + "clk16"); + if (err < 0) { + printf("WARNING: could not set tx-clock-name %s.\n", + fdt_strerror(err)); + break; + } + + err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", + "rmii"); + if (err < 0) { + printf("WARNING: could not set phy-connection-type " + "%s.\n", fdt_strerror(err)); + break; + } + + index = fdt_getprop(blob, nodeoff, "cell-index", 0); + if (index == NULL) { + printf("WARNING: could not get cell-index of ucc\n"); + break; + } + + ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); + if (ph == NULL) { + printf("WARNING: could not get phy-handle of ucc\n"); + break; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("WARNING: could not get phy node %s.\n", + fdt_strerror(err)); + break; + } + + val = 0x7 + *index; /* RMII phy address starts from 0x8 */ + + err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); + if (err < 0) { + printf("WARNING: could not set reg for phy-handle " + "%s.\n", fdt_strerror(err)); + break; + } + } +#endif ft_cpu_setup(blob, bd);

#ifdef CONFIG_PCIE1 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 7208c78..81df4c8 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -283,6 +283,8 @@ extern unsigned long get_clock_freq(void); /* * QE UEC ethernet configuration */ +#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ +#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */

#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) #define CONFIG_UEC_ETH @@ -295,11 +297,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH1 */

#define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_HAS_ETH1 @@ -307,11 +316,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH2 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH2 */

#define CONFIG_UEC_ETH3 /* GETH3 */ #define CONFIG_HAS_ETH2 @@ -319,11 +335,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH3 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ +#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ +#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH3 */

#define CONFIG_UEC_ETH4 /* GETH4 */ #define CONFIG_HAS_ETH3 @@ -331,11 +354,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH4 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ +#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH4 */ #endif /* CONFIG_QE */

#if defined(CONFIG_PCI)

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 10/15] Update the number of ethxaddr in reading system eeprom

We support up to 8 mac addresses in system eeprom, so we'd limit the mac_count to 8, and update the number of ethxaddr if there is more than 4 ethernet ports.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- board/freescale/common/sys_eeprom.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 988cb94..d71a5e4 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2008 Freescale Semiconductor + * Copyright 2006, 2008-2009 Freescale Semiconductor * York Sun (yorksun@freescale.com) * Haiying Wang (haiying.wang@freescale.com) * Timur Tabi (timur@freescale.com) @@ -404,7 +404,14 @@ int mac_read_from_eeprom(void) } }

- for (i = 0; i < min(4, e.mac_count); i++) { + /* Check the number of MAC address which is limited to 8 */ + if (e.mac_count > 8) { + printf("Warning: The number of MAC address is greater" + " than 8, force it to 8.\n"); + e.mac_count = 8; + } + + for (i = 0; i < e.mac_count; i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { char ethaddr[18];

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 11/15] MPC85xx: update uec to support up to 8 UECs in QE

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- cpu/mpc85xx/cpu.c | 6 +++++ cpu/mpc85xx/fdt.c | 4 ++- drivers/qe/uec.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b812d88..eb2aeec 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -399,6 +399,12 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_UEC_ETH6) uec_initialize(5); #endif +#if defined(CONFIG_UEC_ETH7) + uec_initialize(6); +#endif +#if defined(CONFIG_UEC_ETH8) + uec_initialize(7); +#endif #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) tsec_standard_init(bis); #endif diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 26a8f48..720c645 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -279,7 +279,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_crypto_node(blob, 0);

#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ + defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) ||\ + defined(CONFIG_HAS_ETH6) || defined(CONFIG_HAS_ETH7) fdt_fixup_ethernet(blob);

fdt_add_enet_stashing(blob); diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index eadcc2c..deeb947 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -199,8 +199,64 @@ static uec_info_t eth6_uec_info = { .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE, }; #endif +#ifdef CONFIG_UEC_ETH7 +static uec_info_t eth7_uec_info = { + .uf_info = { + .ucc_num = CONFIG_SYS_UEC7_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC7_RX_CLK, + .tx_clock = CONFIG_SYS_UEC7_TX_CLK, + .eth_type = CONFIG_SYS_UEC7_ETH_TYPE, + }, +#if (CONFIG_SYS_UEC7_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CONFIG_SYS_UEC7_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC7_INTERFACE_MODE, +}; +#endif +#ifdef CONFIG_UEC_ETH8 +static uec_info_t eth8_uec_info = { + .uf_info = { + .ucc_num = CONFIG_SYS_UEC8_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC8_RX_CLK, + .tx_clock = CONFIG_SYS_UEC8_TX_CLK, + .eth_type = CONFIG_SYS_UEC8_ETH_TYPE, + }, +#if (CONFIG_SYS_UEC8_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif +#if (MAX_QE_RISC == 4) + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS, + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS, +#else + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CONFIG_SYS_UEC8_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC8_INTERFACE_MODE, +}; +#endif

-#define MAXCONTROLLERS (6) +#define MAXCONTROLLERS (8)

static struct eth_device *devlist[MAXCONTROLLERS];

@@ -1493,6 +1549,14 @@ int uec_initialize(int index) #ifdef CONFIG_UEC_ETH6 uec_info = &eth6_uec_info; #endif + } else if (index == 6) { +#ifdef CONFIG_UEC_ETH7 + uec_info = &eth7_uec_info; +#endif + } else if (index == 7) { +#ifdef CONFIG_UEC_ETH8 + uec_info = &eth8_uec_info; +#endif } else { printf("%s: index is illegal.\n", __FUNCTION__); return -EINVAL;

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 12/15] drivers/qe: add sgmii support in for UEC driver

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- drivers/qe/uec.c | 17 +++++++++++++++++ drivers/qe/uec.h | 31 +++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index deeb947..7649f9f 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -577,6 +577,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; upsmr |= (UPSMR_R10M | UPSMR_RMM); break; + case ENET_1000_SGMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + upsmr |= UPSMR_SGMM; + break; default: return -EINVAL; break; @@ -1276,6 +1280,18 @@ static int uec_startup(uec_private_t *uec)

out_be32(&uec_regs->utbipar, utbipar);

+ /* Configure the TBI for SGMII operation */ + if (uec->uec_info->enet_interface == ENET_1000_SGMII) { + uec_write_phy_reg(uec->dev, uec_regs->utbipar, + ENET_TBI_MII_ANA, TBIANA_SETTINGS); + + uec_write_phy_reg(uec->dev, uec_regs->utbipar, + ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); + + uec_write_phy_reg(uec->dev, uec_regs->utbipar, + ENET_TBI_MII_CR, TBICR_SETTINGS); + } + /* Allocate Tx BDs */ length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * @@ -1565,6 +1581,7 @@ int uec_initialize(int index) devlist[index] = dev;

uec->uec_info = uec_info; + uec->dev = dev;

sprintf(dev->name, "FSL UEC%d", index); dev->iobase = 0; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 411f0d2..5497b06 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * based on source code of Shlomi Gridish @@ -47,6 +47,7 @@ #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ #define UPSMR_BRO 0x00000200 /* Broadcast Address */ #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ +#define UPSMR_SGMM 0x00000020 /* SGMII mode */

#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)

@@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg { ENET_TBI_MII_TBICON = 0x11 } enet_tbi_mii_reg_e;

+/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) + +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + /* UEC number of threads */ typedef enum uec_num_of_threads { @@ -645,7 +671,8 @@ typedef enum enet_interface { ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, ENET_1000_TBI, - ENET_1000_RTBI + ENET_1000_RTBI, + ENET_1000_SGMII } enet_interface_e;

/* UEC initialization info struct

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 13/15] MPC85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS

On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we disable UEC6 and UEC8 by default.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- include/configs/MPC8569MDS.h | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 81df4c8..62507fe 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -366,6 +366,31 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ + +#undef CONFIG_UEC_ETH6 /* GETH6 */ +#define CONFIG_HAS_ETH5 + +#ifdef CONFIG_UEC_ETH6 +#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ +#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC6_PHY_ADDR 4 +#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH6 */ + +#undef CONFIG_UEC_ETH8 /* GETH8 */ +#define CONFIG_HAS_ETH7 + +#ifdef CONFIG_UEC_ETH8 +#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ +#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC8_PHY_ADDR 6 +#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH8 */ + #endif /* CONFIG_QE */

#if defined(CONFIG_PCI)

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 14/15] MPC85xx: Add README for MPC8569MDS

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- doc/README.mpc8569mds | 78 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 78 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8569mds

diff --git a/doc/README.mpc8569mds b/doc/README.mpc8569mds new file mode 100644 index 0000000..d9112b6 --- /dev/null +++ b/doc/README.mpc8569mds @@ -0,0 +1,78 @@ +Overview +-------- +MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform +I/O Board). The mpc8569 PowerTM processor is mounted on PB board. + +Building U-boot +----------- + make MPC8569MDS_config + make + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G +0xa000_0000 0xbfff_ffff PCIe MEM 512MB +0xe000_0000 0xe00f_ffff CCSRBAR 1M +0xe280_0000 0xe2ff_ffff PCIe I/O 8M +0xc000_0000 0xdfff_ffff SRIO 512MB +0xf000_0000 0xf3ff_ffff SDRAM 64MB +0xf800_0000 0xf800_7fff BCSR 32KB +0xf800_8000 0xf800_ffff PIB (CS4) 32KB +0xf801_0000 0xf801_7fff PIB (CS5) 32KB +0xfe00_0000 0xffff_ffff Flash 32MB + + +Flashing u-boot Images +--------------- + +Use the following commands to program u-boot image into flash: + + => tftp 1000000 u-boot.bin + => protect off all + => erase fff80000 ffffffff + => cp.b 1000000 fff80000 80000 + + +Setting the correct MAC addresses +----------------------- +The command - "mac", is introduced to set on-board system EEPROM in the format +defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC +addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when +we first get the board. The commands are as follows: + => mac i NXID /* Set NXID to this EEPROM */ + => mac e 01 /* Set Errata, this value is not defined by hardware + designer, we can set whatever we want */ + => mac n a0 /* Set Serial Number. This is not defined by hardware + designer, we can set whatever we want */ + => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */ + + => mac p 8 /* Set the number of mac ports, it should be 8 */ + => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac + address, you can refer to the value on + the sticker of the rear side of the board + */ + ..... + => mac 7 xx:xx:xx:xx:xx:xx + => mac read + => mac save + +After resetting the board, the ethxaddrs will be filled with the mac addresses +if such environment variables are blank(never been set before). If the ethxaddr +has been set but we want to update it, we can use the following commands: + => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */ + => save + => reset + + +Programming the ucode to flash +--------------------------------- +MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's +IRAM so that the QE can work. The ucode binary can be downloaded from +http://opensource.freescale.com/firmware/, and it must be programmed to +the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot +hangs at "Net:" + + +Please note the above two steps(setting mac addresses and programming ucode) are +very important to get the board booting up and working properly. +

-- 1.6.0.2

Haiying Wang

6:30 p.m.

New subject: [U-Boot] [PATCH 15/15] 85xx: Fix the wrong BCSR address of MPC8569MDS

From: Dave Liu daveliu@freescale.com

The BCSR17[7] = 1 will unlock the write protect of FLASH. The WP# pin only controls the write protect of top/bottom sector, That is why we can save env, but we can't write the first sector before the patch.

Signed-off-by: Dave Liu daveliu@freescale.com Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- board/freescale/mpc8569mds/bcsr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index b895b4e..a936edb 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -27,7 +27,7 @@

void enable_8569mds_flash_write() { - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); }

void disable_8569mds_flash_write()

-- 1.6.0.2

Wolfgang Denk

9:42 p.m.

New subject: [U-Boot] [PATCH 11/15] MPC85xx: update uec to support up to 8 UECs in QE

Dear Haiying Wang,

In message 1242837043-8243-11-git-send-email-Haiying.Wang@freescale.com you wrote:

...

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com

cpu/mpc85xx/cpu.c | 6 +++++ cpu/mpc85xx/fdt.c | 4 ++- drivers/qe/uec.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b812d88..eb2aeec 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -399,6 +399,12 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_UEC_ETH6) uec_initialize(5); #endif +#if defined(CONFIG_UEC_ETH7)

uec_initialize(6);

+#endif +#if defined(CONFIG_UEC_ETH8)

uec_initialize(7);

+#endif

This cries for using a loop instead. There are several places that contain similar code - would it make sense to initialize a variable with a bit files of used interfaces, so we can do this in a simple runtime loop?

...

#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\

defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)

defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\

defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) ||\

defined(CONFIG_HAS_ETH6) || defined(CONFIG_HAS_ETH7) fdt_fixup_ethernet(blob);

Ditto here.

...

#ifdef CONFIG_UEC_ETH6 uec_info = &eth6_uec_info; #endif

} else if (index == 6) {

+#ifdef CONFIG_UEC_ETH7
uec_info = &eth7_uec_info;
+#endif

} else if (index == 7) {

+#ifdef CONFIG_UEC_ETH8
uec_info = &eth8_uec_info;
+#endif

And here again.

Best regards,

Wolfgang Denk

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de A morsel of genuine history is a thing so rare as to be always valuable. - Thomas Jefferson

Wolfgang Denk

9:39 p.m.

New subject: [U-Boot] [PATCH 10/15] Update the number of ethxaddr in reading system eeprom

Dear Haiying Wang,

In message 1242837043-8243-10-git-send-email-Haiying.Wang@freescale.com you wrote:

...

We support up to 8 mac addresses in system eeprom, so we'd limit the mac_count to 8, and update the number of ethxaddr if there is more than 4 ethernet ports.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com

board/freescale/common/sys_eeprom.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 988cb94..d71a5e4 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -1,5 +1,5 @@ /*

Copyright 2006, 2008 Freescale Semiconductor

Copyright 2006, 2008-2009 Freescale Semiconductor

York Sun (yorksun@freescale.com)

Haiying Wang (haiying.wang@freescale.com)

Timur Tabi (timur@freescale.com)

@@ -404,7 +404,14 @@ int mac_read_from_eeprom(void) } }

for (i = 0; i < min(4, e.mac_count); i++) {
/* Check the number of MAC address which is limited to 8 */

if (e.mac_count > 8) {
printf("Warning: The number of MAC address is greater"
	" than 8, force it to 8.\n");
e.mac_count = 8;
}

Instead of repeatedly using the magic number 8 here, this should be a #define in som eheader file.

Best regards,

Wolfgang Denk

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de If you're not part of the solution, then you're part of the precipi- tate.

Wolfgang Denk

9:37 p.m.

New subject: [U-Boot] [PATCH 06/15] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs

Dear Haiying Wang,

In message 1242837043-8243-6-git-send-email-Haiying.Wang@freescale.com you wrote:

...

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Acked-by: Timur Tabi timur@freescale.com

...

+#if (MAX_QE_RISC == 4)

.riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,

.riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,

+#else .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, +#endif

Is there a chance to get rid of these camel-case identifiers? They violate the CodingStyle....

Best regards,

Wolfgang Denk

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de After a time, you may find that "having" is not so pleasing a thing, after all, as "wanting." It is not logical, but it is often true. -- Spock, "Amok Time", stardate 3372.7

Kumar Gala

12 Jun 12 Jun

7:11 a.m.

New subject: [U-Boot] [PATCH 05/15] MPC85xx: Add UART1 support for MPC8569MDS

On May 20, 2009, at 11:30 AM, Haiying Wang wrote:

...

MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define those pins before using UART1.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com

board/freescale/mpc8569mds/mpc8569mds.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

applied

- k

Kumar Gala

7:11 a.m.

New subject: [U-Boot] [PATCH 04/15] MPC85xx: Add PIB support at CS4/CS5 for MPC8569MDS

On May 20, 2009, at 11:30 AM, Haiying Wang wrote:

...

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Signed-off-by: Yu Liu Yu.Liu@freescale.com

include/configs/MPC8569MDS.h | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-)

applied

- k

Kumar Gala

7:10 a.m.

New subject: [U-Boot] [PATCH 02/15] MPC85xx: Fix MURAM size for MPC8569

On May 20, 2009, at 11:30 AM, Haiying Wang wrote:

...

MPC8569 has 128K bytes MURAM.

Signed-off-by: Haiying Wang Haiying.Wang@freescale.com

include/asm-ppc/immap_qe.h | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-)

applied

- k

5808

Age (days ago)

5831

Last active (days ago)

List overview

Download

20 comments

3 participants

tags (0)

participants (3)

Haiying Wang
Kumar Gala
Wolfgang Denk