[U-Boot] [PATCH v2 1/7] armv8: lx2160a: The lx2160a platform supports the I2C driver model.
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - No change.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 --- board/freescale/common/emc2305.c | 21 ++++++ board/freescale/common/qixis.c | 17 +++++ board/freescale/common/sys_eeprom.c | 84 +++++++++++++++++++++-- board/freescale/common/vid.c | 84 +++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 8 +++ drivers/ddr/fsl/main.c | 36 +++++++++- 7 files changed, 245 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a843c1eb65..f3eaab960b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -234,14 +234,6 @@ config ARCH_LX2160A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 - select SYS_I2C_MXC_I2C5 - select SYS_I2C_MXC_I2C6 - select SYS_I2C_MXC_I2C7 - select SYS_I2C_MXC_I2C8 imply DISTRO_DEFAULTS imply PANIC_HANG imply SCSI diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 8523084da9..b1ca051db2 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -24,10 +24,22 @@ void set_fan_speed(u8 data) I2C_EMC2305_FAN5};
for (index = 0; index < NUM_OF_FANS; index++) { +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) { printf("Error: failed to change fan speed @%x\n", Fan[index]); } +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + continue; + + if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#endif } }
@@ -36,6 +48,15 @@ void emc2305_init(void) u8 data;
data = I2C_EMC2305_CMD; +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0) printf("Error: failed to configure EMC2305\n"); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) + printf("Error: failed to configure EMC2305\n"); +#endif + } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index f1b98bcd2a..2c4c4ae108 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -24,13 +24,30 @@ #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { +#ifndef CONFIG_DM_I2C return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + return 0xff; + + return dm_i2c_reg_read(dev, reg); +#endif }
void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; +#ifndef CONFIG_DM_I2C i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + dm_i2c_reg_write(dev, reg, val); +#endif + } #endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ab0fe0baf1..ff76cef411 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -148,23 +148,42 @@ static int read_eeprom(void) { int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; +#endif #endif
if (has_been_read) return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif
- ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e, sizeof(e)); +#ifndef CONFIG_DM_I2C + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e, sizeof(e)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); +#endif
#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C i2c_set_bus_num(bus); #endif +#endif
#ifdef DEBUG show_eeprom(); @@ -198,7 +217,9 @@ static int prog_eeprom(void) int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; +#endif #endif
/* Set the reserved values to 0xFF */ @@ -210,9 +231,11 @@ static int prog_eeprom(void) #endif update_crc();
+#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif #endif
/* @@ -221,8 +244,26 @@ static int prog_eeprom(void) * complete a given write. */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { - ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, +#ifndef CONFIG_DM_I2C + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((int)(sizeof(e) - i), 8)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), + 8)); +#endif if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -232,14 +273,33 @@ static int prog_eeprom(void) /* Verify the write by reading back the EEPROM and comparing */ struct eeprom e2;
+#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e2, sizeof(e2)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); +#endif if (!ret && memcmp(&e, &e2, sizeof(e))) ret = -1; }
+#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); +#endif #endif
if (ret) { @@ -528,8 +588,24 @@ unsigned int get_cpu_board_revision(void) u8 minor; /* 0x05 Board revision, minor */ } be;
+#ifndef CONFIG_DM_I2C i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&be, sizeof(be)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev) +#endif + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); +#endif
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) return MPC85XX_CPU_BOARD_REV(0, 0); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 0ca389c9ae..49b4cd14f9 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -60,13 +60,23 @@ static int find_ir_chip_on_i2c(void) u8 byte; int i; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif
/* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_MFR_ID_OFFSET, 1, (void *)&byte, sizeof(byte)); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, + (void *)&byte, sizeof(byte)); +#endif if ((ret >= 0) && (byte == IR36021_MFR_ID)) return i2caddress; } @@ -102,11 +112,21 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif
for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&buf, 2); +#else + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -135,11 +155,21 @@ static int read_voltage_from_IR(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif
for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_LOOP1_VOUT_OFFSET, 1, (void *)&buf, 1); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read vcpu\n"); return ret; @@ -178,17 +208,33 @@ static int read_voltage_from_LTC(int i2caddress) int ret, vcode = 0; u8 chan = PWM_CHANNEL0;
+#ifndef CONFIG_DM_I2C /* select the PAGE 0 using PMBus commands PAGE for VDD*/ ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); +#endif if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; }
+#ifndef CONFIG_DM_I2C /*read the output voltage using PMBus command READ_VOUT*/ ret = i2c_read(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -293,8 +339,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif
+#ifndef CONFIG_DM_I2C ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, + (void *)&vid, sizeof(vid)); + +#endif if (ret) { printf("VID: failed to write VID\n"); return -1; @@ -330,8 +386,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -515,14 +580,24 @@ int adjust_vdd(ulong vdd_override) }
/* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; goto exit; } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { printf("VID: IR Chip is not used in Intel mode.\n"); ret = -1; @@ -687,9 +762,18 @@ int adjust_vdd(ulong vdd_override) }
/* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 6109b280c6..ea28bfb621 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret;
+#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index e1f69a1d25..ac0783b428 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -92,7 +92,10 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) uint8_t dummy = 0; #endif
+#ifndef CONFIG_DM_I2C i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); +#endif +
#ifdef CONFIG_SYS_FSL_DDR4 /* @@ -101,6 +104,7 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) * To access the upper 256 bytes, we need to set EE page address to 1 * See Jedec standar No. 21-C for detail */ +#ifndef CONFIG_DM_I2C i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); if (!ret) { @@ -111,8 +115,38 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) (int)sizeof(generic_spd_eeprom_t) - 256)); } #else + struct udevice *dev; + int read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256); + + ret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev); + if (!ret) + dm_i2c_write(dev, 0, &dummy, 1); + ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev); + if (!ret) { + if (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) { + if (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS, + 1, &dev)) + dm_i2c_write(dev, 0, &dummy, 1); + if (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev)) + ret = dm_i2c_read(dev, 0, + (uchar *)((ulong)spd + 256), + read_len); + } + } +#endif + +#else + +#ifndef CONFIG_DM_I2C ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); + sizeof(generic_spd_eeprom_t)); +#else + ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); +#endif + #endif
if (ret) {
Enable related configs to support pcf2127 rtc DM feature.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com Signed-off-by: Biwen Li biwen.li@nxp.com --- Changes in v2: - No change.
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 5 +++++ configs/lx2160ardb_tfa_defconfig | 5 +++++ 2 files changed, 10 insertions(+)
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 5cb29fd9ca..d56aa6d333 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -58,3 +58,8 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 94f58a832f..059e877b21 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -57,3 +57,8 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y
This patch solved the following compilation error:
1.Remove the definition of CONFIG_SYS_I2C to solve the following compilation issue: In file included from include/config.h:8:0, from include/common.h:20: include/config_fallbacks.h:51:4: error: #error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" # error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" ^~~~~ In file included from include/config.h:8:0, from include/common.h:20: include/config_fallbacks.h:51:4: error: #error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" # error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" ^~~~~
2.Remove the definition of CONFIG_SYS_I2C_EARLY_INIT to solve the following compilation issue: board/freescale/lx2160a/lx2160a.c: In function 'board_early_init_f': board/freescale/lx2160a/lx2160a.c:108:2: warning: implicit declaration of function 'i2c_early_init_f'; did you mean 'arch_early_init_r'? [-Wimplicit-function-declaration] i2c_early_init_f(); ^~~~~~~~~~~~~~~~ arch_early_init_r
3.Move the enable_i2c_clk function definition to resolve the following compilation issues: drivers/i2c/mxc_i2c.c: In function 'mxc_i2c_probe': drivers/i2c/mxc_i2c.c:824:8: warning: implicit declaration of function 'enable_i2c_clk'; did you mean 'enable_irq_wake'? [-Wimplicit-function-declaration] ret = enable_i2c_clk(1, bus->seq); ^~~~~~~~~~~~~~ enable_irq_wake
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 -- drivers/i2c/mxc_i2c.c | 15 ++++++++------- 2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index eb21c09e01..5f87499980 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -178,8 +178,6 @@ #elif defined(CONFIG_ARCH_LX2160A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_EARLY_INIT #define SRDS_MAX_LANES 8 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 23119cce65..73b9807598 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -558,6 +558,14 @@ static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, return 0; }
+int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{ + return 1; +} + +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) + __attribute__((weak, alias("__enable_i2c_clk"))); + #ifndef CONFIG_DM_I2C /* * Read data from I2C device @@ -723,13 +731,6 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); }
-int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) -{ - return 1; -} -int enable_i2c_clk(unsigned char enable, unsigned i2c_num) - __attribute__((weak, alias("__enable_i2c_clk"))); - void bus_i2c_init(int index, int speed, int unused, int (*idle_bus_fn)(void *p), void *idle_bus_data) {
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for arch ls2160a.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - No change.
arch/arm/include/asm/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 370031f2ac..f78b976e10 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,6 +1,7 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ + !defined(CONFIG_ARCH_LX2160A) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h>
In lx2160a soc, there are eight i2c controllers, this patch adds i2c nodes for lx2160a, and the gpio2 nodes on which the i2c4 controller depends.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - Delete unnecessary clockgen related attributes in the i2c controller node
arch/arm/dts/fsl-lx2160a.dtsi | 85 +++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 28220781d3..a189333e40 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -49,6 +49,80 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ };
+ i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 4>; + scl-gpio = <&gpio2 15 0>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 4>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 4>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 4>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 4>; + scl-gpio = <&gpio2 16 0>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 4>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 4>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 4>; + status = "disabled"; + }; + uart0: serial@21c0000 { compatible = "arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; @@ -102,6 +176,17 @@ num-cs = <6>; };
+ gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>;
This patch adds the pcf2127-rtc node under the i2c4 node.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - Delete unnecessary aliases about i2c.
arch/arm/dts/fsl-lx2160a-rdb.dts | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 4b526449a1..8180b86722 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -27,6 +27,15 @@ status = "okay"; };
+&i2c4 { + status = "okay"; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; +}; + &sata0 { status = "okay"; };
This patch adds some slave nodes to support the i2c dm on the device side under the i2c0 controller.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v2: - Add "u-boot,dm-pre-reloc" attribute to i2c0 node.
arch/arm/dts/fsl-lx2160a-rdb.dts | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 8180b86722..9f4f377c05 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -17,6 +17,14 @@ model = "NXP Layerscape LX2160ARDB Board"; compatible = "fsl,lx2160ardb", "fsl,lx2160a";
+ sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "MC34717-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; };
&esdhc0 { @@ -27,6 +35,48 @@ status = "okay"; };
+&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + + temperature-sensor@4d { + compatible = "nxp,sa56004"; + reg = <0x4d>; + vcc-supply = <&sb_3v3>; + }; + }; + }; +}; + &i2c4 { status = "okay";
participants (1)
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Chuanhua Han