[U-Boot] [PATCH 1/6] arm: socfpga: Define NAND reset bit
Define the NAND reset bit and fix the ordering of the macros.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd8..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
If the system boots from NAND, make sure to de-assert the NAND IP reset, otherwise the system will get stuck.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/spl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..98c16a0 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com --- arch/arm/mach-socfpga/misc.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index a54d2b9..9b43b92 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -359,6 +359,10 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); #endif
+#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + return 0; }
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
arch/arm/mach-socfpga/misc.c | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Chin Liang See clsee@altera.com
Thanks Chin Liang
It is not possible to compile MMC/SPI SPL if the respective DM_MMC/DM_SPI bits are not enabled. Secure the code with an ifdef to prevent compiler splat.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com --- include/configs/socfpga_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3a4df63..3d46330 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -294,8 +294,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_DM_MMC #define CONFIG_SPL_MMC_SUPPORT +#endif +#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT +#endif
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
It is not possible to compile MMC/SPI SPL if the respective DM_MMC/DM_SPI bits are not enabled. Secure the code with an ifdef to prevent compiler splat.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
Acked-by: Chin Liang See clsee@altera.com
Thanks Chin Liang
It is not possible to compile DFU MMC support if the MMC support is not compiled into U-Boot. Secure the code with an ifdef to prevent compiler splat.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3d46330..4124d8b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -249,7 +249,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_FUNCTION_DFU +#ifdef CONFIG_DM_MMC #define CONFIG_DFU_MMC +#endif #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
It is not possible to compile DFU MMC support if the MMC support is not compiled into U-Boot. Secure the code with an ifdef to prevent compiler splat.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
Acked-by: Chin Liang See clsee@altera.com
Thanks Chin Liang
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com --- include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@ #endif
/* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT #endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -324,6 +340,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif
+/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@ #endif
/*
- NAND Support
- */
+#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000
You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BA SE + 0x10) +#endif
+/*
- I2C support
*/ #define CONFIG_SYS_I2C @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT #endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -324,6 +340,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif
+/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
I believe this is need for U-Boot too, right?
Thanks Chin Liang
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif
/*
- Stack setup
*/
On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote:
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@
#endif
/*
- NAND Support
- */
+#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000
You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS
I would like to nuke these two altogether ;-) But they are not as critical as the USB, so OK.
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BA SE + 0x10) +#endif
+/*
- I2C support
*/
#define CONFIG_SYS_I2C
@@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT #endif
+#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -324,6 +340,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif
+/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
I believe this is need for U-Boot too, right?
It's only needed for the SPL, I double-checked.
On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote:
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@
#endif
/*
- NAND Support
- */
+#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000
You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS
Fixed and applied, thanks.
I believe we should be getting close to a good stable setup, so it's about time to start testing once I issue this last heftier PR.
Best regards, Marek Vasut
On Tue, 2015-12-22 at 21:23 +0100, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote:
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Chin Liang See clsee@altera.com
include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@
#endif
/*
- NAND Support
- */
+#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000
You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS
Fixed and applied, thanks.
Nice
Thanks Chin Liang
I believe we should be getting close to a good stable setup, so it's about time to start testing once I issue this last heftier PR.
Best regards, Marek Vasut
participants (2)
-
Chin Liang See -
Marek Vasut