[U-Boot] [PATCH 0/5] dm: clk: add BCM6345 gated clock controller support
Broadcom MIPS SoCs have gated clock controllers which only allow enabling and disabling each peripheral clock. Changing clock rates is not possible on these SoCs.
Álvaro Fernández Rojas (5): dm: clk: add BCM6345 clock driver mips: bmips: add bcm6345-clk driver support for BCM6358 mips: bmips: add bcm6345-clk driver support for BCM6328 mips: bmips: add bcm6345-clk driver support for BCM63268 mips: bmips: enable bcm6345-clk driver for all BMIPS boards
arch/mips/dts/brcm,bcm63268.dtsi | 13 +++++ arch/mips/dts/brcm,bcm6328.dtsi | 7 +++ arch/mips/dts/brcm,bcm6358.dtsi | 7 +++ configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 ++++++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 +++++++++ 13 files changed, 219 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c create mode 100644 include/dt-bindings/clock/bcm63268-clock.h create mode 100644 include/dt-bindings/clock/bcm6328-clock.h create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- drivers/clk/Kconfig | 8 +++++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5ca958c..fa3fbe2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,14 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper.
+config CLK_BCM6345 + bool "Enable clock driver support for BCM6345" + depends on CLK && ARCH_BMIPS + default y + help + This clock driver adds support for clock realted settings for + BCM6345. + config CLK_BOSTON def_bool y if TARGET_BOSTON depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 01a8cd6..2746a80 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ +obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c new file mode 100644 index 0000000..0b52079 --- /dev/null +++ b/drivers/clk/clk_bcm6345.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/bcm63xx/clk.c: + * Copyright (C) 2008 Maxime Bizon mbizon@freebox.fr + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <clk-uclass.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> + +#define MAX_CLKS 32 + +struct bcm6345_clk_priv { + void __iomem *regs; +}; + +static int bcm6345_clk_enable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + setbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static int bcm6345_clk_disable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + clrbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static struct clk_ops bcm6345_clk_ops = { + .disable = bcm6345_clk_disable, + .enable = bcm6345_clk_enable, +}; + +static const struct udevice_id bcm6345_clk_ids[] = { + { .compatible = "brcm,bcm6345-clk" }, + { /* sentinel */ } +}; + +static int bcm63xx_clk_probe(struct udevice *dev) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + return 0; +} + +U_BOOT_DRIVER(clk_bcm6345) = { + .name = "clk_bcm6345", + .id = UCLASS_CLK, + .of_match = bcm6345_clk_ids, + .ops = &bcm6345_clk_ops, + .probe = bcm63xx_clk_probe, + .priv_auto_alloc_size = sizeof(struct bcm6345_clk_priv), +};
Hi Alvarao,
On 3 May 2017 at 07:09, Álvaro Fernández Rojas noltari@gmail.com wrote:
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
drivers/clk/Kconfig | 8 +++++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c
Reviewed-by: Simon Glass sjg@chromium.org
nits below
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5ca958c..fa3fbe2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,14 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper.
+config CLK_BCM6345
bool "Enable clock driver support for BCM6345"depends on CLK && ARCH_BMIPSdefault yhelpThis clock driver adds support for clock realted settings forBCM6345.
Can you give a bit more detail here? Does it support all clocks?
config CLK_BOSTON def_bool y if TARGET_BOSTON depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 01a8cd6..2746a80 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ +obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c new file mode 100644 index 0000000..0b52079 --- /dev/null +++ b/drivers/clk/clk_bcm6345.c @@ -0,0 +1,78 @@ +/*
- Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
- Derived from linux/arch/mips/bcm63xx/clk.c:
Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <clk-uclass.h> +#include <common.h>
This should always go first.
Regards, Simon
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- arch/mips/dts/brcm,bcm6358.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index edd0002..369c240 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm6358-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; };
pflash: nor@1e000000 { diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 0000000..ff22321 --- /dev/null +++ b/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSL 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */
On 3 May 2017 at 07:09, Álvaro Fernández Rojas noltari@gmail.com wrote:
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
arch/mips/dts/brcm,bcm6358.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
Reviewed-by: Simon Glass sjg@chromium.org
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6328-clock.h
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a5b43ae..6b5c5dd 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm6328-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; };
ubus { diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 0000000..5d0fc11 --- /dev/null +++ b/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */
On 3 May 2017 at 07:09, Álvaro Fernández Rojas noltari@gmail.com wrote:
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6328-clock.h
Reviewed-by: Simon Glass sjg@chromium.org
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- arch/mips/dts/brcm,bcm63268.dtsi | 13 ++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/bcm63268-clock.h
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 11c6729..4d02024 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm63268-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,18 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; };
ubus { diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 0000000..23818da --- /dev/null +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WO_EPHY 5 +#define BCM63268_TCLK_WO_DSL 6 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXT 17 +#define BCM63268_TCLK_USB_REF 18 +#define BCM63268_TCLK_SW_RST 29 +#define BCM63268_TCLK_HW_RST 30 +#define BCM63268_TCLK_POR_RST 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
On 3 May 2017 at 07:09, Álvaro Fernández Rojas noltari@gmail.com wrote:
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
arch/mips/dts/brcm,bcm63268.dtsi | 13 ++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/bcm63268-clock.h
Reviewed-by: Simon Glass sjg@chromium.org
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + 4 files changed, 4 insertions(+)
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index f8656c4..55cb4bf 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_AR5387UN=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index a04b0e5..7f13d24 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_VR3032U=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index ccfdf1d..71e1163 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 8b885e3..cd6c4a2 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y
2017-05-03 7:09 GMT-06:00 Álvaro Fernández Rojas noltari@gmail.com:
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + 4 files changed, 4 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
You might consider adding an imply to your Kconfig somewhere.
Broadcom MIPS SoCs have gated clock controllers which only allow enabling and disabling each peripheral clock. Changing clock rates is not possible on these SoCs.
v2: Introduce changes suggested by Simon Glass
Álvaro Fernández Rojas (5): dm: clk: add BCM6345 clock driver mips: bmips: add bcm6345-clk driver support for BCM6358 mips: bmips: add bcm6345-clk driver support for BCM6328 mips: bmips: add bcm6345-clk driver support for BCM63268 mips: bmips: enable bcm6345-clk driver for all BMIPS boards
arch/mips/dts/brcm,bcm63268.dtsi | 13 +++++ arch/mips/dts/brcm,bcm6328.dtsi | 7 +++ arch/mips/dts/brcm,bcm6358.dtsi | 7 +++ configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 ++++++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 +++++++++ 13 files changed, 219 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c create mode 100644 include/dt-bindings/clock/bcm63268-clock.h create mode 100644 include/dt-bindings/clock/bcm6328-clock.h create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: Introduce changes suggested by Simon Glass: - Swap common.h include to the beginning. - Add a more detailed description. - Switch to fdtdec_get_bool().
drivers/clk/Kconfig | 8 +++++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5ca958c..44da716 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,14 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper.
+config CLK_BCM6345 + bool "Clock controller driver for BCM6345" + depends on CLK && ARCH_BMIPS + default y + help + This clock driver adds support for enabling and disabling peripheral + clocks on BCM6345 SoCs. HW has no rate changing capabilities. + config CLK_BOSTON def_bool y if TARGET_BOSTON depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 01a8cd6..2746a80 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ +obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c new file mode 100644 index 0000000..4c7a2df --- /dev/null +++ b/drivers/clk/clk_bcm6345.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/bcm63xx/clk.c: + * Copyright (C) 2008 Maxime Bizon mbizon@freebox.fr + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> + +#define MAX_CLKS 32 + +struct bcm6345_clk_priv { + void __iomem *regs; +}; + +static int bcm6345_clk_enable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + setbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static int bcm6345_clk_disable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + clrbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static struct clk_ops bcm6345_clk_ops = { + .disable = bcm6345_clk_disable, + .enable = bcm6345_clk_enable, +}; + +static const struct udevice_id bcm6345_clk_ids[] = { + { .compatible = "brcm,bcm6345-clk" }, + { /* sentinel */ } +}; + +static int bcm63xx_clk_probe(struct udevice *dev) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + return 0; +} + +U_BOOT_DRIVER(clk_bcm6345) = { + .name = "clk_bcm6345", + .id = UCLASS_CLK, + .of_match = bcm6345_clk_ids, + .ops = &bcm6345_clk_ops, + .probe = bcm63xx_clk_probe, + .priv_auto_alloc_size = sizeof(struct bcm6345_clk_priv), +};
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: no changes.
arch/mips/dts/brcm,bcm6358.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index edd0002..369c240 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm6358-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; };
pflash: nor@1e000000 { diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 0000000..ff22321 --- /dev/null +++ b/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSL 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: no changes.
arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6328-clock.h
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a5b43ae..6b5c5dd 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm6328-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; };
ubus { diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 0000000..5d0fc11 --- /dev/null +++ b/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: no changes.
arch/mips/dts/brcm,bcm63268.dtsi | 13 ++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/bcm63268-clock.h
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 11c6729..4d02024 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <dt-bindings/clock/bcm63268-clock.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi"
@@ -43,6 +44,18 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; };
ubus { diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 0000000..23818da --- /dev/null +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WO_EPHY 5 +#define BCM63268_TCLK_WO_DSL 6 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXT 17 +#define BCM63268_TCLK_USB_REF 18 +#define BCM63268_TCLK_SW_RST 29 +#define BCM63268_TCLK_HW_RST 30 +#define BCM63268_TCLK_POR_RST 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: no changes.
configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + 4 files changed, 4 insertions(+)
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index f8656c4..55cb4bf 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_AR5387UN=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index a04b0e5..7f13d24 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_VR3032U=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index ccfdf1d..71e1163 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 8b885e3..cd6c4a2 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y
Am 07.05.2017 um 20:13 schrieb Álvaro Fernández Rojas:
Broadcom MIPS SoCs have gated clock controllers which only allow enabling and disabling each peripheral clock. Changing clock rates is not possible on these SoCs.
v2: Introduce changes suggested by Simon Glass
Álvaro Fernández Rojas (5): dm: clk: add BCM6345 clock driver mips: bmips: add bcm6345-clk driver support for BCM6358 mips: bmips: add bcm6345-clk driver support for BCM6328 mips: bmips: add bcm6345-clk driver support for BCM63268 mips: bmips: enable bcm6345-clk driver for all BMIPS boards
arch/mips/dts/brcm,bcm63268.dtsi | 13 +++++ arch/mips/dts/brcm,bcm6328.dtsi | 7 +++ arch/mips/dts/brcm,bcm6358.dtsi | 7 +++ configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 ++++++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 +++++++++ 13 files changed, 219 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c create mode 100644 include/dt-bindings/clock/bcm63268-clock.h create mode 100644 include/dt-bindings/clock/bcm6328-clock.h create mode 100644 include/dt-bindings/clock/bcm6358-clock.h
series applied to u-boot-mips/next, thanks
participants (3)
-
Daniel Schwierzeck -
Simon Glass -
Álvaro Fernández Rojas