[U-Boot] [PATCH 1/2] spi: fsl_qspi: support i.MX6UL/7D
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly.
Add the compatible entry for 6ul/7d.
Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/spi/fsl_qspi.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 0f3f7d97f0..e37f4538e2 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80 -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7D) #define TX_BUFFER_SIZE 0x200 #else #define TX_BUFFER_SIZE 0x40 @@ -268,7 +268,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7D) /* * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. * So, Use IDATSZ in IPCR to determine the size and here set 0. @@ -905,6 +905,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, qspi->slave.max_write_size = TX_BUFFER_SIZE;
mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); + + /* Set endianness to LE for i.mx */ + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + mcr_val = QSPI_MCR_END_CFD_LE; + qspi_write32(qspi->priv.flags, ®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | (mcr_val & QSPI_MCR_END_CFD_MASK)); @@ -1023,6 +1028,11 @@ static int fsl_qspi_probe(struct udevice *bus) }
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); + + /* Set endianness to LE for i.mx */ + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + mcr_val = QSPI_MCR_END_CFD_LE; + qspi_write32(priv->flags, &priv->regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | (mcr_val & QSPI_MCR_END_CFD_MASK)); @@ -1227,6 +1237,8 @@ static const struct dm_spi_ops fsl_qspi_ops = { static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,vf610-qspi" }, { .compatible = "fsl,imx6sx-qspi" }, + { .compatible = "fsl,imx6ul-qspi" }, + { .compatible = "fsl,imx7d-qspi" }, { } };
To support QSPI DM driver - Add spi0 alias for qspi node. Which is used for bus number 0. - Modify the n25q256a@0 compatible property to "spi-flash". - Modify spi4 (gpio_spi) node to spi5 - Define DM SPI/QSPI related config to enable QSPI
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx6ull-14x14-evk.dts | 5 +++-- arch/arm/dts/imx6ull.dtsi | 9 +++++---- configs/mx6ull_14x14_evk_defconfig | 6 ++++++ configs/mx6ull_14x14_evk_plugin_defconfig | 6 ++++++ include/configs/mx6ullevk.h | 10 ++++++++++ 5 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 375bd4ea31..2a941bff1c 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -67,7 +67,7 @@ }; };
- spi4 { + spi5 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; @@ -455,7 +455,8 @@ flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q256a"; + /* compatible = "micron,n25q256a"; */ + compatible = "spi-flash"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; reg = <0>; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 65950e8019..ea882a7f14 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -38,10 +38,11 @@ serial5 = &uart6; serial6 = &uart7; serial7 = &uart8; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; + spi0 = &qspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 4960056fe4..5305c12fdb 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -10,6 +10,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y @@ -24,7 +25,12 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index d07be226f5..f1023b2aae 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -11,6 +11,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y @@ -25,7 +26,12 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 8787df4907..6a48742fd0 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -164,4 +164,14 @@
#define CONFIG_SOFT_SPI
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + #endif
Hi Peng,
On Tue, Jan 2, 2018 at 5:23 AM, Peng Fan peng.fan@nxp.com wrote:
-#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7D)
Please add defined(CONFIG_MX6ULL) as well.
participants (2)
-
Fabio Estevam -
Peng Fan