[U-Boot-Users] [REPOST][PATCH 1/4] 85xx: Cleanup L2 cache size detection
The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu_init.c | 47 ++++++++++++++++++++++++++++++----------------- 1 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 736aef1..4feb751 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -261,37 +261,50 @@ int cpu_init_r(void) volatile uint cache_ctl; uint svr, ver; uint l2srbar; + u32 l2siz_field;
svr = get_svr(); ver = SVR_SOC_VER(svr);
asm("msync;isync"); cache_ctl = l2cache->l2ctl; + l2siz_field = (cache_ctl >> 28) & 0x3;
- switch (cache_ctl & 0x30000000) { - case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E || - ver == SVR_8544 || ver == SVR_8568_E) { - puts ("512 KB "); - /* set L2E=1, L2I=1, & L2SRAM=0 */ - cache_ctl = 0xc0000000; + switch (l2siz_field) { + case 0x0: + printf(" unknown size (0x%08x)\n", cache_ctl); + return -1; + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) { + puts("128 KB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ + cache_ctl = 0xc4000000; } else { puts("256 KB "); + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) { + puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; + } else { + puts ("512 KB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } break; - case 0x10000000: - puts("256 KB "); - if (ver == SVR_8544 || ver == SVR_8544_E) { - cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ - } + case 0x3: + puts("1024 KB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; break; - case 0x30000000: - case 0x00000000: - default: - printf(" unknown size (0x%08x)\n", cache_ctl); - return -1; }
if (l2cache->l2ctl & 0x80000000) {
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8544ds/mpc8544ds.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 8c4b040..c39ce11 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -49,7 +49,10 @@ int checkboard (void) if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); } - printf ("Board: MPC8544DS\n"); + printf ("Board: MPC8544DS, System ID: 0x%02x, " + "System Version: 0x%02x, FPGA Version: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER));
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
Add new L1/L2 SPRs related to e500mc cache config and control.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- include/asm-ppc/processor.h | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 10fd478..581ef52 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -426,6 +426,7 @@ /* e500 definitions */ #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ +#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ @@ -434,6 +435,21 @@ #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ +#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ @@ -624,8 +640,12 @@ #define MCSRR1 SPRN_MCSRR1 #define L1CSR0 SPRN_L1CSR0 #define L1CSR1 SPRN_L1CSR1 +#define L1CSR2 SPRN_L1CSR2 #define L1CFG0 SPRN_L1CFG0 #define L1CFG1 SPRN_L1CFG1 +#define L2CFG0 SPRN_L2CFG0 +#define L2CSR0 SPRN_L2CSR0 +#define L2CSR1 SPRN_L2CSR1 #define MCSR SPRN_MCSR #define MMUCSR0 SPRN_MMUCSR0 #define BUCSR SPRN_BUCSR
Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8544ds/u-boot.lds | 1 + include/configs/MPC8544DS.h | 24 ++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index 785a006..c66c69f 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -71,6 +71,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) + drivers/bios_emulator/atibios.o (.text) *(.text) *(.fixup) *(.got1) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 669f4d7..a0e4df8 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -226,7 +226,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -314,6 +314,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
+/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS + +/*PCI video card used*/ +/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -382,7 +402,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if CFG_MONITOR_BASE > 0xfff80000 #define CFG_ENV_ADDR 0xfff80000 #else -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) #endif #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
On Mon, Jul 14, 2008 at 2:07 PM, Kumar Gala galak@kernel.crashing.org wrote:
Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
Applied, thanks
Andy
On Mon, Jul 14, 2008 at 2:07 PM, Kumar Gala galak@kernel.crashing.org wrote:
Add new L1/L2 SPRs related to e500mc cache config and control.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
Applied, thanks
Andy
On Mon, Jul 14, 2008 at 2:07 PM, Kumar Gala galak@kernel.crashing.org wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
Applied, thanks
Andy
On Mon, Jul 14, 2008 at 2:07 PM, Kumar Gala galak@kernel.crashing.org wrote:
The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
Applied, thanks
Andy
participants (2)
-
Andy Fleming -
Kumar Gala