[PATCH v2] net: designware: Support high memory nodes
Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux gilbsgilbert@gmail.com Cc: Andre Przywara andre.przywara@arm.com ---
Changes in v2: - explicitly define and handle ioaddr as a virtual address - use an intermediate variable to assign the PCI base address - use appropriate placeholder to print physical addresses --- drivers/net/designware.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3e..78bfce07f6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -678,8 +678,8 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev); - u32 iobase = pdata->iobase; - ulong ioaddr; + phys_addr_t iobase = pdata->iobase; + void *ioaddr; int ret, err; struct reset_ctl_bulk reset_bulk; #ifdef CONFIG_CLK @@ -740,16 +740,18 @@ int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in plat before we probe the hardware. */ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = dm_pci_mem_to_phys(dev, iobase); + u32 pcibase;
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase); + pcibase &= PCI_BASE_ADDRESS_MEM_MASK; + + iobase = dm_pci_mem_to_phys(dev, pcibase); pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; }
- debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); - ioaddr = iobase; + debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv); + ioaddr = phys_to_virt(iobase); priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface;
On Sat, 2 Dec 2023 10:39:49 +0100 Nils Le Roux gilbsgilbert@gmail.com wrote:
Hi Nils,
Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux gilbsgilbert@gmail.com Cc: Andre Przywara andre.przywara@arm.com
many thanks for the changes, that looks good to me now. I have compile-tested that for arm64 and arm.
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
Changes in v2:
- explicitly define and handle ioaddr as a virtual address
- use an intermediate variable to assign the PCI base address
- use appropriate placeholder to print physical addresses
drivers/net/designware.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3e..78bfce07f6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -678,8 +678,8 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev);
- u32 iobase = pdata->iobase;
- ulong ioaddr;
- phys_addr_t iobase = pdata->iobase;
- void *ioaddr; int ret, err; struct reset_ctl_bulk reset_bulk;
#ifdef CONFIG_CLK @@ -740,16 +740,18 @@ int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in plat before we probe the hardware. */ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);iobase &= PCI_BASE_ADDRESS_MEM_MASK;iobase = dm_pci_mem_to_phys(dev, iobase);
u32 pcibase;dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase);pcibase &= PCI_BASE_ADDRESS_MEM_MASK;iobase = dm_pci_mem_to_phys(dev, pcibase);pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; }
- debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
- ioaddr = iobase;
- debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv);
- ioaddr = phys_to_virt(iobase); priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface;
On Mon, 4 Dec 2023 01:09:30 +0000 Andre Przywara andre.przywara@arm.com wrote:
Hi Joe, Ramon, Tom,
for some reason patchwork put this on my plate, but it looks like genuine network code to me, and the problem definitely doesn't affect sunxi. As tagged below, I am happy with this change, so if there are no objections, can one of you take this patch, please?
Cheers, Andre
On Sat, 2 Dec 2023 10:39:49 +0100 Nils Le Roux gilbsgilbert@gmail.com wrote:
Hi Nils,
Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux gilbsgilbert@gmail.com Cc: Andre Przywara andre.przywara@arm.com
many thanks for the changes, that looks good to me now. I have compile-tested that for arm64 and arm.
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
Changes in v2:
- explicitly define and handle ioaddr as a virtual address
- use an intermediate variable to assign the PCI base address
- use appropriate placeholder to print physical addresses
drivers/net/designware.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3e..78bfce07f6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -678,8 +678,8 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev);
- u32 iobase = pdata->iobase;
- ulong ioaddr;
- phys_addr_t iobase = pdata->iobase;
- void *ioaddr; int ret, err; struct reset_ctl_bulk reset_bulk;
#ifdef CONFIG_CLK @@ -740,16 +740,18 @@ int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in plat before we probe the hardware. */ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);iobase &= PCI_BASE_ADDRESS_MEM_MASK;iobase = dm_pci_mem_to_phys(dev, iobase);
u32 pcibase;dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase);pcibase &= PCI_BASE_ADDRESS_MEM_MASK;iobase = dm_pci_mem_to_phys(dev, pcibase);pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; }
- debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
- ioaddr = iobase;
- debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv);
- ioaddr = phys_to_virt(iobase); priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface;
On Sat, Feb 10, 2024 at 05:37:03PM +0000, Andre Przywara wrote:
On Mon, 4 Dec 2023 01:09:30 +0000 Andre Przywara andre.przywara@arm.com wrote:
Hi Joe, Ramon, Tom,
for some reason patchwork put this on my plate, but it looks like genuine network code to me, and the problem definitely doesn't affect sunxi. As tagged below, I am happy with this change, so if there are no objections, can one of you take this patch, please?
I believe I delegated it to you since Ramon doesn't often have time to put together a PR, and since it seems otherwise fine and relevant to platforms you're the custodian for, I was fine with you grabbing it. But yes, I can pick it up directly instead.
On Mon, 12 Feb 2024 13:40:31 -0500 Tom Rini trini@konsulko.com wrote:
On Sat, Feb 10, 2024 at 05:37:03PM +0000, Andre Przywara wrote:
On Mon, 4 Dec 2023 01:09:30 +0000 Andre Przywara andre.przywara@arm.com wrote:
Hi Joe, Ramon, Tom,
for some reason patchwork put this on my plate, but it looks like genuine network code to me, and the problem definitely doesn't affect sunxi. As tagged below, I am happy with this change, so if there are no objections, can one of you take this patch, please?
I believe I delegated it to you since Ramon doesn't often have time to put together a PR, and since it seems otherwise fine and relevant to platforms you're the custodian for, I was fine with you grabbing it. But yes, I can pick it up directly instead.
Ah, that's fine, I just didn't know and didn't want to interfere with any other ongoing merges. I am preparing a pull request for this week, and can surely put in there, unless you want to beat me to it.
Cheers, Andre
On Mon, Feb 12, 2024 at 07:56:40PM +0000, Andre Przywara wrote:
On Mon, 12 Feb 2024 13:40:31 -0500 Tom Rini trini@konsulko.com wrote:
On Sat, Feb 10, 2024 at 05:37:03PM +0000, Andre Przywara wrote:
On Mon, 4 Dec 2023 01:09:30 +0000 Andre Przywara andre.przywara@arm.com wrote:
Hi Joe, Ramon, Tom,
for some reason patchwork put this on my plate, but it looks like genuine network code to me, and the problem definitely doesn't affect sunxi. As tagged below, I am happy with this change, so if there are no objections, can one of you take this patch, please?
I believe I delegated it to you since Ramon doesn't often have time to put together a PR, and since it seems otherwise fine and relevant to platforms you're the custodian for, I was fine with you grabbing it. But yes, I can pick it up directly instead.
Ah, that's fine, I just didn't know and didn't want to interfere with any other ongoing merges. I am preparing a pull request for this week, and can surely put in there, unless you want to beat me to it.
I've already thrown it through CI just now, so no big deal.
On Sat, 02 Dec 2023 10:39:49 +0100, Nils Le Roux wrote:
Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
[...]
Applied to u-boot/master, thanks!
participants (3)
-
Andre Przywara -
Nils Le Roux -
Tom Rini