[U-Boot] [PATCH v3 0/7] Enable falcon boot for LS1043ARDB
This is the 3rd version to enable falcon boot for LS1043ARDB. With SPL FIT patches merged, enabling falcon boot for this board is straight forward after fixing some errors introduced by other commits.
Falcon boot is not enabled by default due to a conflict with recent PPA image update, which takes over entire OCRAM after being loaded. With a compatible PPA image (older version or future update), falcon boot can be enabled as described in commit message.
Secure boot is dropped in this set due to SPL image size issue. Recent changes made the SPL image bigger and the secure boot image doesn't fit any more. A follow-up patch set will enable secure boot if the image can be future trimmed to fit.
Changes in v3: Create new function to fill gd->bd for spl. Use git commit description style when mentioning previous commit. Fix typo in subject and other cosmetic fix. Drop defconfig change Not to enable falcon boot by default due to a conflict with recent PPA
Changes in v2: New patch to fix spl after rebasing to latest master. New patch to fix compiling error after rebasing to latest mater. New patch to fix gd->ram_size error after rebasing to latest mater. Drop checking secure boot in this patch after rebasing to latest mater. Recent change in SPL makes the image size bigger. Relace getenv_f() with env_get_f() after rebasing to latet master.
York Sun (7): spl: fix assignment of board info to global data cmd: spl: fix compiling error when CONFIG_CMD_SPL_WRITE_SIZE not defined armv8: fsl-layerscape: Avoid running dram_init_banksize again armv8: ls1043ardb: Use static DDR setting for SPL boot armv8: layerscape: Enable falcon boot armv8: ls1043ardb: Enable spl_board_init() function armv8: ls1043ardb_sdcard: prepare falcon boot
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 ++- .../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 30 +++++ arch/arm/include/asm/system.h | 4 +- arch/arm/lib/spl.c | 11 ++ board/freescale/ls1043ardb/ddr.c | 46 +++++++ board/freescale/ls1043ardb/ddr.h | 69 ++++++++++ cmd/spl.c | 2 + common/spl/spl.c | 10 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 2 + include/configs/ls1043a_common.h | 7 +- include/configs/ls1043ardb.h | 11 +- include/spl.h | 1 + 16 files changed, 344 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to global data") intended to move assignment of board info earlier, into board_init_r(). However, function preload_console_init() is called either from spl_board_init() or from board_init_f(). For the latter case, the board info assignment is much earlier than proposed board_init_r(). Create a new function to fill gd->bd and call this function when needed.
Signed-off-by: York Sun york.sun@nxp.com CC: Lokesh Vutla lokeshvutla@ti.com CC: Ravi Babu ravibabu@ti.com CC: Lukasz Majewski lukma@denx.de CC: Tom Rini trini@konsulko.com
---
Changes in v3: Create new function to fill gd->bd for spl. Use git commit description style when mentioning previous commit.
Changes in v2: New patch to fix spl after rebasing to latest master.
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 1 + common/spl/spl.c | 10 +++++++++- include/spl.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 2776240..2534b4b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -80,6 +80,7 @@ void board_init_f(ulong dummy) get_clocks();
preloader_console_init(); + spl_set_bd();
#ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); diff --git a/common/spl/spl.c b/common/spl/spl.c index 4afbe97..aaddddd 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -258,6 +258,12 @@ static int spl_common_init(bool setup_malloc) return 0; }
+void spl_set_bd(void) +{ + if (!gd->bd) + gd->bd = &bdata; +} + int spl_early_init(void) { int ret; @@ -365,7 +371,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) struct spl_image_info spl_image;
debug(">>spl:board_init_r()\n"); - gd->bd = &bdata; + + spl_set_bd(); + #ifdef CONFIG_SPL_OS_BOOT dram_init_banksize(); #endif diff --git a/include/spl.h b/include/spl.h index ce4cf0a..b14a29c 100644 --- a/include/spl.h +++ b/include/spl.h @@ -68,6 +68,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(const u32 boot_device); +void spl_set_bd(void);
/** * spl_set_header_raw_uboot() - Set up a standard SPL image structure
On 09/28/2017 08:42 AM, York Sun wrote:
Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to global data") intended to move assignment of board info earlier, into board_init_r(). However, function preload_console_init() is called either from spl_board_init() or from board_init_f(). For the latter case, the board info assignment is much earlier than proposed board_init_r(). Create a new function to fill gd->bd and call this function when needed.
Signed-off-by: York Sun york.sun@nxp.com CC: Lokesh Vutla lokeshvutla@ti.com CC: Ravi Babu ravibabu@ti.com CC: Lukasz Majewski lukma@denx.de CC: Tom Rini trini@konsulko.com
Changes in v3: Create new function to fill gd->bd for spl. Use git commit description style when mentioning previous commit.
Simon,
Is this version OK?
York
On 28 September 2017 at 09:42, York Sun york.sun@nxp.com wrote:
Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to global data") intended to move assignment of board info earlier, into board_init_r(). However, function preload_console_init() is called either from spl_board_init() or from board_init_f(). For the latter case, the board info assignment is much earlier than proposed board_init_r(). Create a new function to fill gd->bd and call this function when needed.
Signed-off-by: York Sun york.sun@nxp.com CC: Lokesh Vutla lokeshvutla@ti.com CC: Ravi Babu ravibabu@ti.com CC: Lukasz Majewski lukma@denx.de CC: Tom Rini trini@konsulko.com
Changes in v3: Create new function to fill gd->bd for spl. Use git commit description style when mentioning previous commit.
Changes in v2: New patch to fix spl after rebasing to latest master.
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 1 + common/spl/spl.c | 10 +++++++++- include/spl.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 09/28/2017 08:42 AM, York Sun wrote:
Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to global data") intended to move assignment of board info earlier, into board_init_r(). However, function preload_console_init() is called either from spl_board_init() or from board_init_f(). For the latter case, the board info assignment is much earlier than proposed board_init_r(). Create a new function to fill gd->bd and call this function when needed.
Signed-off-by: York Sun york.sun@nxp.com CC: Lokesh Vutla lokeshvutla@ti.com CC: Ravi Babu ravibabu@ti.com CC: Lukasz Majewski lukma@denx.de CC: Tom Rini trini@konsulko.com
Changes in v3: Create new function to fill gd->bd for spl. Use git commit description style when mentioning previous commit.
Changes in v2: New patch to fix spl after rebasing to latest master.
This set is applied to fsl-qoriq master.
York
CONFIG_CMD_SPL_WRITE_SIZE is used for writing parameters to non-volatile storage. So far it is only used for NAND. Fix compiling error when this macro is not used for SD.
Signed-off-by: York Sun york.sun@nxp.com CC: Anatolij Gustschin agust@denx.de
---
Changes in v3: None Changes in v2: New patch to fix compiling error after rebasing to latest mater.
cmd/spl.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/cmd/spl.c b/cmd/spl.c index 4d84492..3b8992a 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -121,9 +121,11 @@ static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (void *)images.ft_addr); env_set_addr("fdtargsaddr", images.ft_addr); env_set_hex("fdtargslen", fdt_totalsize(images.ft_addr)); +#ifdef CONFIG_CMD_SPL_WRITE_SIZE if (fdt_totalsize(images.ft_addr) > CONFIG_CMD_SPL_WRITE_SIZE) puts("WARN: FDT size > CMD_SPL_WRITE_SIZE\n"); +#endif break; #endif case SPL_EXPORT_ATAGS:
gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling.
Signed-off-by: York Sun york.sun@nxp.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v3: None Changes in v2: New patch to fix gd->ram_size error after rebasing to latest mater.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d21a494..fe5f4a9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -698,8 +698,19 @@ int dram_init_banksize(void) * memory. The DDR extends from low region to high region(s) presuming * no hole is created with DDR configuration. gd->arch.secure_ram tracks * the location of secure memory. gd->arch.resv_ram tracks the location - * of reserved memory for Management Complex (MC). + * of reserved memory for Management Complex (MC). Because gd->ram_size + * is reduced by this function if secure memory is reserved, checking + * gd->arch.secure_ram should be done to avoid running it repeatedly. */ + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { + debug("No need to run again, skip %s\n", __func__); + + return 0; + } +#endif + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; @@ -797,6 +808,11 @@ int dram_init_banksize(void) } #endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + debug("%s is called. gd->ram_size is reduced to %lu\n", + __func__, (ulong)gd->ram_size); +#endif + return 0; }
This board has soldered DDR chips. To reduce the SPL image size, use static DDR setting instead of dynamic DDR driver.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v3: Minor cosmetic fix.
Changes in v2: Drop checking secure boot in this patch after rebasing to latest mater. Recent change in SPL makes the image size bigger.
board/freescale/ls1043ardb/ddr.c | 46 +++++++++++++++++++++++++++ board/freescale/ls1043ardb/ddr.h | 69 ++++++++++++++++++++++++++++++++++++++++ include/configs/ls1043ardb.h | 6 ++-- 3 files changed, 118 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 354b864..fc0c1f6 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -169,18 +169,64 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0; } +#else + +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t)2048 * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + return ddr_size; +} #endif
int fsl_initdram(void) { phys_size_t dram_size;
+#ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif +#else +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) + puts("Initialzing DDR using fixed setting\n"); + dram_size = fixed_sdram(); +#else + gd->ram_size = 0x80000000; + + return 0; +#endif +#endif erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index a77ddf3..6bc0eb6 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -45,4 +45,73 @@ static const struct board_specific_parameters *udimms[] = { udimm0, };
+#ifndef CONFIG_SYS_DDR_RAW_TIMING +fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = { + .cs[0].bnds = 0x0000007F, + .cs[1].bnds = 0, + .cs[2].bnds = 0, + .cs[3].bnds = 0, + .cs[0].config = 0x80040322, + .cs[0].config_2 = 0, + .cs[1].config = 0, + .cs[1].config_2 = 0, + .cs[2].config = 0, + .cs[3].config = 0, + .timing_cfg_3 = 0x010C1000, + .timing_cfg_0 = 0x91550018, + .timing_cfg_1 = 0xBBB48C42, + .timing_cfg_2 = 0x0048C111, + .ddr_sdram_cfg = 0xC50C0008, + .ddr_sdram_cfg_2 = 0x00401100, + .ddr_sdram_cfg_3 = 0, + .ddr_sdram_mode = 0x03010210, + .ddr_sdram_mode_2 = 0, + .ddr_sdram_mode_3 = 0x00010210, + .ddr_sdram_mode_4 = 0, + .ddr_sdram_mode_5 = 0x00010210, + .ddr_sdram_mode_6 = 0, + .ddr_sdram_mode_7 = 0x00010210, + .ddr_sdram_mode_8 = 0, + .ddr_sdram_mode_9 = 0x00000500, + .ddr_sdram_mode_10 = 0x04000000, + .ddr_sdram_mode_11 = 0x00000400, + .ddr_sdram_mode_12 = 0x04000000, + .ddr_sdram_mode_13 = 0x00000400, + .ddr_sdram_mode_14 = 0x04000000, + .ddr_sdram_mode_15 = 0x00000400, + .ddr_sdram_mode_16 = 0x04000000, + .ddr_sdram_interval = 0x18600618, + .ddr_data_init = 0xDEADBEEF, + .ddr_sdram_clk_cntl = 0x03000000, + .ddr_init_addr = 0, + .ddr_init_ext_addr = 0, + .timing_cfg_4 = 0x00000002, + .timing_cfg_5 = 0x03401400, + .timing_cfg_6 = 0, + .timing_cfg_7 = 0x13300000, + .timing_cfg_8 = 0x02115600, + .timing_cfg_9 = 0, + .ddr_zq_cntl = 0x8A090705, + .ddr_wrlvl_cntl = 0x8675F607, + .ddr_wrlvl_cntl_2 = 0x07090800, + .ddr_wrlvl_cntl_3 = 0, + .ddr_sr_cntr = 0, + .ddr_sdram_rcw_1 = 0, + .ddr_sdram_rcw_2 = 0, + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x0000A181, + .dq_map_0 = 0, + .dq_map_1 = 0, + .dq_map_2 = 0, + .dq_map_3 = 0, + .debug[28] = 0x00700046, + +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {1550, 1650, &ddr_cfg_regs_1600}, + {0, 0, NULL} +}; + +#endif #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index ca1d862..da87497 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -28,13 +28,13 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_FSL_DDR_BIST #ifndef CONFIG_SPL -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#endif #define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_FSL_DDR_BIST #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif
#ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
Hi York,
This board has soldered DDR chips. To reduce the SPL image size, use static DDR setting instead of dynamic DDR driver.
I'm just wondering - since your board supports FIT in SPL, maybe it would be good to have a binary blob with DDR RAM settings embedded into it?
Then you would be able to provide "hardcoded" SDRAM setup via it? In this way it could be easily replaceable?
Signed-off-by: York Sun york.sun@nxp.com
Changes in v3: Minor cosmetic fix.
Changes in v2: Drop checking secure boot in this patch after rebasing to latest mater. Recent change in SPL makes the image size bigger.
board/freescale/ls1043ardb/ddr.c | 46 +++++++++++++++++++++++++++ board/freescale/ls1043ardb/ddr.h | 69 ++++++++++++++++++++++++++++++++++++++++ include/configs/ls1043ardb.h | 6 ++-- 3 files changed, 118 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 354b864..fc0c1f6 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -169,18 +169,64 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0; } +#else
+phys_size_t fixed_sdram(void) +{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
- printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {memcpy(&ddr_cfg_regs,fixed_ddr_parm_0[i].ddr_settings,sizeof(ddr_cfg_regs));break;}- }
- if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",strmhz(buf, ddr_freq));- ddr_size = (phys_size_t)2048 * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
- return ddr_size;
+} #endif
int fsl_initdram(void) { phys_size_t dram_size;
+#ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif +#else +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- puts("Initialzing DDR using fixed setting\n");
- dram_size = fixed_sdram();
+#else
- gd->ram_size = 0x80000000;
- return 0;
+#endif +#endif erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index a77ddf3..6bc0eb6 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -45,4 +45,73 @@ static const struct board_specific_parameters *udimms[] = { udimm0, };
+#ifndef CONFIG_SYS_DDR_RAW_TIMING +fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
- .cs[0].bnds = 0x0000007F,
- .cs[1].bnds = 0,
- .cs[2].bnds = 0,
- .cs[3].bnds = 0,
- .cs[0].config = 0x80040322,
- .cs[0].config_2 = 0,
- .cs[1].config = 0,
- .cs[1].config_2 = 0,
- .cs[2].config = 0,
- .cs[3].config = 0,
- .timing_cfg_3 = 0x010C1000,
- .timing_cfg_0 = 0x91550018,
- .timing_cfg_1 = 0xBBB48C42,
- .timing_cfg_2 = 0x0048C111,
- .ddr_sdram_cfg = 0xC50C0008,
- .ddr_sdram_cfg_2 = 0x00401100,
- .ddr_sdram_cfg_3 = 0,
- .ddr_sdram_mode = 0x03010210,
- .ddr_sdram_mode_2 = 0,
- .ddr_sdram_mode_3 = 0x00010210,
- .ddr_sdram_mode_4 = 0,
- .ddr_sdram_mode_5 = 0x00010210,
- .ddr_sdram_mode_6 = 0,
- .ddr_sdram_mode_7 = 0x00010210,
- .ddr_sdram_mode_8 = 0,
- .ddr_sdram_mode_9 = 0x00000500,
- .ddr_sdram_mode_10 = 0x04000000,
- .ddr_sdram_mode_11 = 0x00000400,
- .ddr_sdram_mode_12 = 0x04000000,
- .ddr_sdram_mode_13 = 0x00000400,
- .ddr_sdram_mode_14 = 0x04000000,
- .ddr_sdram_mode_15 = 0x00000400,
- .ddr_sdram_mode_16 = 0x04000000,
- .ddr_sdram_interval = 0x18600618,
- .ddr_data_init = 0xDEADBEEF,
- .ddr_sdram_clk_cntl = 0x03000000,
- .ddr_init_addr = 0,
- .ddr_init_ext_addr = 0,
- .timing_cfg_4 = 0x00000002,
- .timing_cfg_5 = 0x03401400,
- .timing_cfg_6 = 0,
- .timing_cfg_7 = 0x13300000,
- .timing_cfg_8 = 0x02115600,
- .timing_cfg_9 = 0,
- .ddr_zq_cntl = 0x8A090705,
- .ddr_wrlvl_cntl = 0x8675F607,
- .ddr_wrlvl_cntl_2 = 0x07090800,
- .ddr_wrlvl_cntl_3 = 0,
- .ddr_sr_cntr = 0,
- .ddr_sdram_rcw_1 = 0,
- .ddr_sdram_rcw_2 = 0,
- .ddr_cdr1 = 0x80040000,
- .ddr_cdr2 = 0x0000A181,
- .dq_map_0 = 0,
- .dq_map_1 = 0,
- .dq_map_2 = 0,
- .dq_map_3 = 0,
- .debug[28] = 0x00700046,
+};
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {1550, 1650, &ddr_cfg_regs_1600},
- {0, 0, NULL}
+};
+#endif #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index ca1d862..da87497 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -28,13 +28,13 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_FSL_DDR_BIST #ifndef CONFIG_SPL -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#endif #define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_FSL_DDR_BIST #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif
#ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
On 09/29/2017 12:44 AM, Łukasz Majewski wrote:
Hi York,
This board has soldered DDR chips. To reduce the SPL image size, use static DDR setting instead of dynamic DDR driver.
I'm just wondering - since your board supports FIT in SPL, maybe it would be good to have a binary blob with DDR RAM settings embedded into it?
Then you would be able to provide "hardcoded" SDRAM setup via it? In this way it could be easily replaceable?
Lukasz,
It sounds reasonable but doesn't work for our platforms. The limitation is the static RAM. In order to load anything, we need to have some memory. Lacking of memory is the exact reason I have to use static DDR setting. I have to make room for other drivers in SPL.
York
Hi York,
On 09/29/2017 12:44 AM, Łukasz Majewski wrote:
Hi York,
This board has soldered DDR chips. To reduce the SPL image size, use static DDR setting instead of dynamic DDR driver.
I'm just wondering - since your board supports FIT in SPL, maybe it would be good to have a binary blob with DDR RAM settings embedded into it?
Then you would be able to provide "hardcoded" SDRAM setup via it? In this way it could be easily replaceable?
Lukasz,
It sounds reasonable but doesn't work for our platforms. The limitation is the static RAM. In order to load anything, we need to have some memory. Lacking of memory is the exact reason I have to use static DDR setting. I have to make room for other drivers in SPL.
I rather thought about:
Creating FIT image with firmware property, in which you will have 1:1 binary image for DDR controller registers (e.g. 256B).
Then you could store this image to non-volatile memory and read it from SPL (just copy values to registers).
In that way you would be able to switch different configurations for different memories (DDR2/DDR3/, 1066, 1333 MHz) without the need to replace u-boot/SPL.
York
On 09/29/2017 09:06 AM, Łukasz Majewski wrote:
Hi York,
On 09/29/2017 12:44 AM, Łukasz Majewski wrote:
Hi York,
This board has soldered DDR chips. To reduce the SPL image size, use static DDR setting instead of dynamic DDR driver.
I'm just wondering - since your board supports FIT in SPL, maybe it would be good to have a binary blob with DDR RAM settings embedded into it?
Then you would be able to provide "hardcoded" SDRAM setup via it? In this way it could be easily replaceable?
Lukasz,
It sounds reasonable but doesn't work for our platforms. The limitation is the static RAM. In order to load anything, we need to have some memory. Lacking of memory is the exact reason I have to use static DDR setting. I have to make room for other drivers in SPL.
I rather thought about:
Creating FIT image with firmware property, in which you will have 1:1 binary image for DDR controller registers (e.g. 256B).
Then you could store this image to non-volatile memory and read it from SPL (just copy values to registers).
In that way you would be able to switch different configurations for different memories (DDR2/DDR3/, 1066, 1333 MHz) without the need to replace u-boot/SPL.
Lukasz,
I understand your suggestion. I was trying to say that I don't have any spare room to load the FIT into before I have DDR initialized. I only have limited SRAM.
York
Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot.
Signed-off-by: York Sun york.sun@nxp.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v3: Fix typo in subject and other cosmetic fix.
Changes in v2: Relace getenv_f() with env_get_f() after rebasing to latet master.
.../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 29 +++++ arch/arm/include/asm/system.h | 4 +- arch/arm/lib/spl.c | 11 ++ 4 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon new file mode 100644 index 0000000..282b19f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon @@ -0,0 +1,140 @@ +Falcon boot option +------------------ +Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the +RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux. +CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT +image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally +CONFIG_SPL_GZIP). + +To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate +booting U-Boot is not the first choice. The kernel FIT image needs to be put +at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to +determine if this is a FIT image. If true, FIT image components are parsed and +copied or decompressed (if applicable) to their desitinations. If FIT image is +not found, normal U-Boot flow will follow. + +An important part of falcon boot is to prepare the device tree. A normal U-Boot +does FDT fixups when booting Linux. For falcon boot, Linux boots directly from +SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. +A command "spl export" should be called under the normal RAM version U-Boot. +It is equivalent to go through "bootm" step-by-step until device tree fixup is +done. The device tree in memory is the one needed for falcon boot. Falcon boot +flow suggests to save this image to SD/eMMC at the location pointed by macro +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, with maximum size specified by macro +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS. However, when FIT image is used for +Linux, the device tree stored in FIT image overwrites the memory loaded by spl +driver from these sectors. We could change this loading order to favor the +stored sectors. But when secure boot is enabled, these sectors are used for +signature header and needs to be loaded before the FIT image. So it is important +to understand the device tree in FIT image should be the one actually used, or +leave it abscent to favor the stored sectors. It is easier to deploy the FIT +image with embedded static device tree to multiple boards. + +Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load +the stored sectors to. Normally this is the static device tree. The second +purpose is the memory location of signature header for secure boot. After the +FIT image is loaded into memory, it is validated against the signature header +before individual components are extracted (and optionally decompressed) into +their final memory locations, respectivelly. After the validation, the header +is no longer used. The static device tree is copied into this location. So +this macro is passed as the location of device tree when booting Linux. + +Steps to prepare static device tree +----------------------------------- +To prepare the static device tree for Layerscape boards, it is important to +understand the fixups in U-Boot. Memory size and location, as well as reserved +memory blocks are added/updated. Ethernet MAC addressed are updated. FMan +microcode (if used) is embedded in the device tree. Kernel command line and +initrd information are embedded. Others including CPU status, boot method, +Ethernet port status, etc. are also updated. + +Following normal booting process, all variables are set, all images are loaded +before "bootm" command would be issued to boot, run command + +spl export fdt <address> + +where the address is the location of FIT image. U-Boot goes through the booting +process as if "bootm start", "bootm loados", "bootm ramdisk"... commands but +stops before "bootm go". There we have the fixed-up device tree in memory. +We can check the device tree header by these commands + +fdt addr <fdt address> +fdt header + +Where the fdt address is the device tree in memory. It is printed by U-Boot. +It is useful to know the exact size. One way to extract this static device +tree is to save it to eMMC/SD using command in U-Boot, and extract under Linux +with these commands, repectivelly + +mmc write <address> <sector> <sectors> +dd if=/dev/mmcblk0 of=<filename> bs=512 skip=<sector> count=<sectors> + +Note, U-Boot takes values as hexadecimals while Linux takes them as decimals by +default. If using NAND or other storage, the commands are slightly different. +When we have the static device tree image, we can re-make the FIT image with +it. It is important to specify the load addresses in FIT image for every +components. Otherwise U-Boot cannot load them correctly. + +Generate FIT image with static device tree +------------------------------------------ +Example: + +/dts-v1/; + +/ { + description = "Image file for the LS1043A Linux Kernel"; + #address-cells = <1>; + + images { + kernel@1 { + description = "ARM64 Linux kernel"; + data = /incbin/("./arch/arm64/boot/Image.gz"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0x80080000>; + entry = <0x80080000>; + }; + fdt@1 { + description = "Flattened Device Tree blob"; + data = /incbin/("./fsl-ls1043ardb-static.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x90000000>; + }; + ramdisk@1 { + description = "LS1043 Ramdisk"; + data = /incbin/("./rootfs.cpio.gz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0xa0000000>; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot Linux kernel"; + kernel = "kernel@1"; + fdt = "fdt@1"; + ramdisk = "ramdisk@1"; + loadables = "fdt", "ramdisk"; + }; + }; +}; + +The "loadables" is not optional. It tells SPL which images to load into memory. + +Other things to consider +----------------------- +Falcon boot skips a lot of initialization in U-Boot. If Linux expects the +hardware to be initialized by U-Boot, the related code should be ported to SPL +build. For example, if Linux expect Ethernet PHY to be initialized in U-Boot +(which is not a common case), the PHY initialization has to be included in +falcon boot. This increases the SPL image size and should be handled carefully. +If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup +in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 2534b4b..bbb9ab1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -117,4 +117,33 @@ void board_init_f(ulong dummy) gd->arch.tlb_allocated = gd->arch.tlb_addr; #endif /* CONFIG_SPL_FSL_LS_PPA */ } + +#ifdef CONFIG_SPL_OS_BOOT +/* + * Return + * 0 if booting into OS is selected + * 1 if booting into U-Boot is selected + */ +int spl_start_uboot(void) +{ + char s[8]; + + env_init(); + env_get_f("boot_os", s, sizeof(s)); + if (s && (*s != '0' && *s != 'n' && *s != 'N' && + *s != 'f' && *s != 'F')) + return 0; + + return 1; +} +#endif /* CONFIG_SPL_OS_BOOT */ +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 79bd19a..1d7d4f3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -215,8 +215,8 @@ void __asm_switch_ttbr(u64 new_ttbr); * @entry_point: kernel entry point * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 */ -void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, - u64 arg4, u64 entry_point, u64 es_flag); +void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); /* * Switch from EL2 to EL1 for ARMv8 * diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 27d6682..ab5d227 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -7,6 +7,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #include <common.h> #include <config.h> #include <spl.h> @@ -47,6 +48,15 @@ void __weak board_init_f(ulong dummy) * image. */ #ifdef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_ARM64 +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) +{ + debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg); + cleanup_before_linux(); + armv8_switch_to_el2((u64)spl_image->arg, 0, 0, 0, + spl_image->entry_point, ES_TO_AARCH64); +} +#else void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) { unsigned long machid = 0xffffffff; @@ -62,4 +72,5 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) cleanup_before_linux(); image_entry(0, machid, spl_image->arg); } +#endif /* CONFIG_ARM64 */ #endif
Hi York,
Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot.
Signed-off-by: York Sun york.sun@nxp.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v3: Fix typo in subject and other cosmetic fix.
Changes in v2: Relace getenv_f() with env_get_f() after rebasing to latet master.
.../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 29 +++++ arch/arm/include/asm/system.h | 4 +- arch/arm/lib/spl.c | 11 ++ 4 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon new file mode 100644 index 0000000..282b19f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon @@ -0,0 +1,140 @@ +Falcon boot option +------------------ +Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the +RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux. +CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT +image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally +CONFIG_SPL_GZIP).
+To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate +booting U-Boot is not the first choice. The kernel FIT image needs to be put +at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to +determine if this is a FIT image. If true, FIT image components are parsed and +copied or decompressed (if applicable) to their desitinations. If FIT image is
^^^^^ - destinations
+not found, normal U-Boot flow will follow.
+An important part of falcon boot is to prepare the device tree. A normal U-Boot +does FDT fixups when booting Linux. For falcon boot, Linux boots directly from +SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. +A command "spl export" should be called under the normal RAM version U-Boot. +It is equivalent to go through "bootm" step-by-step until device tree fixup is +done. The device tree in memory is the one needed for falcon boot. Falcon boot +flow suggests to save this image to SD/eMMC at the location pointed by macro +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, with maximum size specified by macro +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS. However, when FIT image is used for +Linux, the device tree stored in FIT image overwrites the memory loaded by spl +driver from these sectors. We could change this loading order to favor the +stored sectors. But when secure boot is enabled, these sectors are used for +signature header and needs to be loaded before the FIT image. So it is important +to understand the device tree in FIT image should be the one actually used, or +leave it abscent to favor the stored sectors. It is easier to deploy the FIT
^^^^^^ absent
+image with embedded static device tree to multiple boards.
I would also add: "The decision if CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR loaded DTB is override is based on presence of "loadables" property in fitImage. If present the 'static' dtb from fitImage takes precedence.
+Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load +the stored sectors to. Normally this is the static device tree. The second +purpose is the memory location of signature header for secure boot. After the +FIT image is loaded into memory, it is validated against the signature header +before individual components are extracted (and optionally decompressed) into +their final memory locations, respectivelly. After the validation, the header
^^^^ respectively
+is no longer used. The static device tree is copied into this location. So +this macro is passed as the location of device tree when booting Linux.
+Steps to prepare static device tree +----------------------------------- +To prepare the static device tree for Layerscape boards, it is important to +understand the fixups in U-Boot. Memory size and location, as well as reserved +memory blocks are added/updated. Ethernet MAC addressed are updated. FMan +microcode (if used) is embedded in the device tree. Kernel command line and +initrd information are embedded. Others including CPU status, boot method, +Ethernet port status, etc. are also updated.
+Following normal booting process, all variables are set, all images are loaded +before "bootm" command would be issued to boot, run command
+spl export fdt <address>
+where the address is the location of FIT image. U-Boot goes through the booting +process as if "bootm start", "bootm loados", "bootm ramdisk"... commands but +stops before "bootm go". There we have the fixed-up device tree in memory. +We can check the device tree header by these commands
+fdt addr <fdt address> +fdt header
+Where the fdt address is the device tree in memory. It is printed by U-Boot. +It is useful to know the exact size. One way to extract this static device +tree is to save it to eMMC/SD using command in U-Boot, and extract under Linux +with these commands, repectivelly
^^^^ respectively
+mmc write <address> <sector> <sectors> +dd if=/dev/mmcblk0 of=<filename> bs=512 skip=<sector> count=<sectors>
+Note, U-Boot takes values as hexadecimals while Linux takes them as decimals by +default. If using NAND or other storage, the commands are slightly different. +When we have the static device tree image, we can re-make the FIT image with +it. It is important to specify the load addresses in FIT image for every +components. Otherwise U-Boot cannot load them correctly.
+Generate FIT image with static device tree +------------------------------------------ +Example:
+/dts-v1/;
+/ {
- description = "Image file for the LS1043A Linux Kernel";
- #address-cells = <1>;
- images {
kernel@1 {description = "ARM64 Linux kernel";data = /incbin/("./arch/arm64/boot/Image.gz");type = "kernel";arch = "arm64";os = "linux";compression = "gzip";load = <0x80080000>;entry = <0x80080000>;};fdt@1 {description = "Flattened Device Tree blob";data = /incbin/("./fsl-ls1043ardb-static.dtb");type = "flat_dt";arch = "arm64";compression = "none";load = <0x90000000>;};ramdisk@1 {description = "LS1043 Ramdisk";data = /incbin/("./rootfs.cpio.gz");type = "ramdisk";arch = "arm64";os = "linux";compression = "gzip";load = <0xa0000000>;};- };
- configurations {
default = "config@1";config@1 {description = "Boot Linux kernel";kernel = "kernel@1";fdt = "fdt@1";ramdisk = "ramdisk@1";loadables = "fdt", "ramdisk";};- };
+};
+The "loadables" is not optional. It tells SPL which images to load into memory
"as well as allows overriding the "falcon mode" created and loaded DTB".
+Other things to consider +----------------------- +Falcon boot skips a lot of initialization in U-Boot. If Linux expects the +hardware to be initialized by U-Boot, the related code should be ported to SPL +build. For example, if Linux expect Ethernet PHY to be initialized in U-Boot +(which is not a common case), the PHY initialization has to be included in +falcon boot. This increases the SPL image size and should be handled carefully. +If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup +in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 2534b4b..bbb9ab1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -117,4 +117,33 @@ void board_init_f(ulong dummy) gd->arch.tlb_allocated = gd->arch.tlb_addr; #endif /* CONFIG_SPL_FSL_LS_PPA */ }
+#ifdef CONFIG_SPL_OS_BOOT +/*
- Return
- 0 if booting into OS is selected
- 1 if booting into U-Boot is selected
- */
+int spl_start_uboot(void) +{
- char s[8];
- env_init();
- env_get_f("boot_os", s, sizeof(s));
You may consider using env_get_yesno("boot_os") instead.
- if (s && (*s != '0' && *s != 'n' && *s != 'N' &&
*s != 'f' && *s != 'F'))return 0;- return 1;
+} +#endif /* CONFIG_SPL_OS_BOOT */ +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- return 0;
+} +#endif #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 79bd19a..1d7d4f3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -215,8 +215,8 @@ void __asm_switch_ttbr(u64 new_ttbr);
- @entry_point: kernel entry point
- @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
*/ -void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
u64 arg4, u64 entry_point, u64 es_flag);+void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
u64 arg4, u64 entry_point, u64 es_flag);
- Switch from EL2 to EL1 for ARMv8
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 27d6682..ab5d227 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -7,6 +7,7 @@
- SPDX-License-Identifier: GPL-2.0+
*/
- #include <common.h> #include <config.h> #include <spl.h>
@@ -47,6 +48,15 @@ void __weak board_init_f(ulong dummy)
- image.
*/ #ifdef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_ARM64 +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) +{
- debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg);
- cleanup_before_linux();
- armv8_switch_to_el2((u64)spl_image->arg, 0, 0, 0,
spl_image->entry_point, ES_TO_AARCH64);+} +#else void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) { unsigned long machid = 0xffffffff; @@ -62,4 +72,5 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) cleanup_before_linux(); image_entry(0, machid, spl_image->arg); } +#endif /* CONFIG_ARM64 */ #endif
I can confirm that your changes already available in master branch work. I'm able to boot fitImage from SPL, with using falcon boot mode.
Reviewed-by: Łukasz Majewski lukma@denx.de Tested-by: Łukasz Majewski lukma@denx.de
On 09/29/2017 01:02 AM, Łukasz Majewski wrote:
Hi York,
Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot.
Signed-off-by: York Sun york.sun@nxp.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v3: Fix typo in subject and other cosmetic fix.
Changes in v2: Relace getenv_f() with env_get_f() after rebasing to latet master.
.../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 29 +++++ arch/arm/include/asm/system.h | 4 +- arch/arm/lib/spl.c | 11 ++ 4 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon new file mode 100644 index 0000000..282b19f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon @@ -0,0 +1,140 @@ +Falcon boot option +------------------ +Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the +RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux. +CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT +image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally +CONFIG_SPL_GZIP).
+To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate +booting U-Boot is not the first choice. The kernel FIT image needs to be put +at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to +determine if this is a FIT image. If true, FIT image components are parsed and +copied or decompressed (if applicable) to their desitinations. If FIT image is
^^^^^ - destinations
Thanks for catching them. I will fix them with another spin, or when applying it. I need to setup the spelling check.
York
CONFIG_SPL_BOARD_INIT is used for SPL boot. Enable it in defconfig for LS1043ARDB SPL targets.
Signed-off-by: York Sun york.sun@nxp.com ---
Changes in v3: None Changes in v2: None
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + 4 files changed, 4 insertions(+)
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 5c8599e..416182a 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_CRYPTO_SUPPORT=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index e5310fe..d680d93 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index bdd7ea7..b2144f3 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_CRYPTO_SUPPORT=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index f6ea06b..0e9d168 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
Due to a conflict with recent Primary Protected Application (PPA), PPA cannot be loaded for SPL stage, falcon boot is not enabled by default. With compatible PPA image, to enable falcon boot, activate these Kconfig options in defconfig CONFIG_SPL_FIT=y CONFIG_SPL_FSL_LS_PPA=y CONFIG_SPL_GZIP=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_OF_LIBFDT=y
Because environment variables are not avaiable during SPL stage for SD boot, set "boot_os=y" as default.
Signed-off-by: York Sun york.sun@nxp.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v3: Drop defconfig change Not to enable falcon boot by default due to a conflict with recent PPA
Changes in v2: None
configs/ls1043ardb_sdcard_defconfig | 1 + include/configs/ls1043a_common.h | 7 ++++--- include/configs/ls1043ardb.h | 5 +++++ 3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 0e9d168..2ce2aba 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_FSL_LS_PPA=y +CONFIG_SPL_FSL_LS_PPA=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1f9efff..a297134 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -73,10 +73,10 @@ #define CONFIG_SPL_STACK 0x1001e000 #define CONFIG_SPL_PAD_TO 0x1d000
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#ifdef CONFIG_SECURE_BOOT @@ -280,6 +280,7 @@ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "console=ttyS0,115200\0" \ + "boot_os=y\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1043ardb_boot.scr\0" \ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index da87497..f9843f5 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -46,6 +46,11 @@
#ifdef CONFIG_SD_BOOT #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +#define CONFIG_CMD_SPL +#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 #endif
/*
participants (3)
-
Simon Glass -
York Sun -
Łukasz Majewski