[U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de ---
Resend v2: Rebased on latest rc. Link to v2:https://patchwork.ozlabs.org/patch/698614/
drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index df6a91fc9f7b..5d5b6f0d350b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */ @@ -724,6 +725,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; + struct bounce_buffer bb; + u8 *bb_txbuf; + + /* + * Handle non-4-byte aligned accesses via bounce buffer to + * avoid data abort. + */ + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + if (ret) + return ret; + bb_txbuf = bb.bounce_buffer;
/* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -734,11 +746,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) - writesb(plat->ahbbase, txbuf, write_bytes); - else - writesl(plat->ahbbase, txbuf, write_bytes >> 2); + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); + if (write_bytes % 4) + writesb(plat->ahbbase, + bb_txbuf + rounddown(write_bytes, 4), + write_bytes % 4);
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -748,7 +760,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; }
- txbuf += write_bytes; + bb_txbuf += write_bytes; remaining -= write_bytes; }
@@ -759,6 +771,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } + bounce_buffer_stop(&bb);
/* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, @@ -769,6 +782,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR); + bounce_buffer_stop(&bb); return ret; }
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 2da0d8dd7f00..4f9c42abac7e 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -78,6 +78,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif
#endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a655084491..e50c2fac8d99 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER
/* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER
#endif
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface reads until the last word of an indirect transfer So, make sure that QSPI indirect reads are 32 bit sized except for the final read. If the rxbuf is unaligned then use bounce buffer, so that readsl() can be used instead of readsb() to avoid non 32-bit accesses.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de ---
v2: rebase on top of latest rc Link to v1: https://patchwork.ozlabs.org/patch/700990/
drivers/spi/cadence_qspi_apb.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 5d5b6f0d350b..e02f2217f45f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -634,6 +634,8 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, { unsigned int remaining = n_rx; unsigned int bytes_to_read = 0; + struct bounce_buffer bb; + u8 *bb_rxbuf; int ret;
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); @@ -642,6 +644,11 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, writel(CQSPI_REG_INDIRECTRD_START, plat->regbase + CQSPI_REG_INDIRECTRD);
+ ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE); + if (ret) + return ret; + bb_rxbuf = bb.bounce_buffer; + while (remaining > 0) { ret = cadence_qspi_wait_for_data(plat); if (ret < 0) { @@ -655,12 +662,13 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, bytes_to_read *= CQSPI_FIFO_WIDTH; bytes_to_read = bytes_to_read > remaining ? remaining : bytes_to_read; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4)) - readsb(plat->ahbbase, rxbuf, bytes_to_read); - else - readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2); - rxbuf += bytes_to_read; + readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2); + if (bytes_to_read % 4) + readsb(plat->ahbbase, + bb_rxbuf + rounddown(bytes_to_read, 4), + bytes_to_read % 4); + + bb_rxbuf += bytes_to_read; remaining -= bytes_to_read; bytes_to_read = cadence_qspi_get_rd_sram_level(plat); } @@ -677,6 +685,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + bounce_buffer_stop(&bb);
return 0;
@@ -684,6 +693,7 @@ failrd: /* Cancel the indirect read */ writel(CQSPI_REG_INDIRECTRD_CANCEL, plat->regbase + CQSPI_REG_INDIRECTRD); + bounce_buffer_stop(&bb); return ret; }
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Resend v2: Rebased on latest rc. Link to v2:https://patchwork.ozlabs.org/patch/698614/
drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index df6a91fc9f7b..5d5b6f0d350b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */ @@ -724,6 +725,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret;
struct bounce_buffer bb;
u8 *bb_txbuf;
/*
* Handle non-4-byte aligned accesses via bounce buffer to* avoid data abort.*/ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
if (ret)
return ret;bb_txbuf = bb.bounce_buffer;
/* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
@@ -734,11 +746,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining;
/* Handle non-4-byte aligned access to avoid data abort. */if (((uintptr_t)txbuf % 4) || (write_bytes % 4))writesb(plat->ahbbase, txbuf, write_bytes);elsewritesl(plat->ahbbase, txbuf, write_bytes >> 2);
writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);if (write_bytes % 4)writesb(plat->ahbbase,bb_txbuf + rounddown(write_bytes, 4),write_bytes % 4);ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK <<
@@ -748,7 +760,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; }
txbuf += write_bytes;
bb_txbuf += write_bytes;@@ -759,6 +771,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; }
bounce_buffer_stop(&bb);
/* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE,
@@ -769,6 +782,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR);
- bounce_buffer_stop(&bb); return ret;
}
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 2da0d8dd7f00..4f9c42abac7e 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -78,6 +78,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif
#endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a655084491..e50c2fac8d99 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER
/*
- Designware SPI support
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER
#endif
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
On 01/04/2017 04:53 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
I believe you mean next, right ?
On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 04:53 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote:
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
I believe you mean next, right ?
master, Since the patch thread start before MW
On 01/04/2017 05:40 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 04:53 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote:
On 12/21/2016 10:42 AM, Vignesh R wrote: > According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC > TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit > data interface writes until the last word of an indirect transfer > otherwise indirect writes is known to fails sometimes. So, make sure > that QSPI indirect writes are 32 bit sized except for the last write. If > the txbuf is unaligned then use bounce buffer to avoid data aborts. > > So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER > for all boards that use Cadence QSPI driver. > > [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf > > Signed-off-by: Vignesh R vigneshr@ti.com > Reviewed-by: Marek Vasut marex@denx.de
Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
I believe you mean next, right ?
master, Since the patch thread start before MW
I just hope you don't plan to push this into 2017.01 ...
On Wed, Jan 4, 2017 at 5:43 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 05:40 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 04:53 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote:
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote: > > > On 12/21/2016 10:42 AM, Vignesh R wrote: >> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC >> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit >> data interface writes until the last word of an indirect transfer >> otherwise indirect writes is known to fails sometimes. So, make sure >> that QSPI indirect writes are 32 bit sized except for the last write. If >> the txbuf is unaligned then use bounce buffer to avoid data aborts. >> >> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER >> for all boards that use Cadence QSPI driver. >> >> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf >> >> Signed-off-by: Vignesh R vigneshr@ti.com >> Reviewed-by: Marek Vasut marex@denx.de > > Gentle ping on the series...
Please link to other one, I couldn't find it on patchwork.
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
I believe you mean next, right ?
master, Since the patch thread start before MW
I just hope you don't plan to push this into 2017.01 ...
I already send PR for these, since these were sitting so-long. any issues?
On 01/04/2017 05:54 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:43 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 05:40 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut marex@denx.de wrote:
On 01/04/2017 04:53 PM, Jagan Teki wrote:
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R vigneshr@ti.com wrote:
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: > On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh vigneshr@ti.com wrote: >> >> >> On 12/21/2016 10:42 AM, Vignesh R wrote: >>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC >>> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit >>> data interface writes until the last word of an indirect transfer >>> otherwise indirect writes is known to fails sometimes. So, make sure >>> that QSPI indirect writes are 32 bit sized except for the last write. If >>> the txbuf is unaligned then use bounce buffer to avoid data aborts. >>> >>> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER >>> for all boards that use Cadence QSPI driver. >>> >>> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf >>> >>> Signed-off-by: Vignesh R vigneshr@ti.com >>> Reviewed-by: Marek Vasut marex@denx.de >> >> Gentle ping on the series... > > Please link to other one, I couldn't find it on patchwork. >
Here are the two patches of the series: https://patchwork.ozlabs.org/patch/707648/ https://patchwork.ozlabs.org/patch/707647/
Applied to u-boot-spi/master
I believe you mean next, right ?
master, Since the patch thread start before MW
I just hope you don't plan to push this into 2017.01 ...
I already send PR for these, since these were sitting so-long. any issues?
Hm, let's see, the release is in 5 days and this affects multiple boards from different SoC vendors. Therefore, there will likely be no testing of this patchset and we will find latent bugs only after release, when they cannot be fixed anymore. There is a reason for those multiple RC cycles ...
participants (4)
-
Jagan Teki -
Marek Vasut -
R, Vignesh -
Vignesh R