* insert AT91 SoC access using c-stuctures

Signed-off-by: Jens Scharsig js_at_ng@scharsoft.de --- diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..274a135 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -23,6 +23,10 @@ */

#include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> @@ -30,29 +34,29 @@

void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIN_PB19, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIN_PB18, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); }

void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIN_PB4, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIN_PB5, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); }

void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIN_PD6, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIN_PD7, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); }

void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ + at91_set_a_periph(AT91_PIN_PB12, 0); /* DRXD */ + at91_set_a_periph(AT91_PIN_PB13, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; }

@@ -78,24 +82,24 @@ void at91_serial_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */

/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);

if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB3, 0); + at91_set_a_periph(AT91_PIN_PB3, 0); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PB18, 0); + at91_set_b_periph(AT91_PIN_PB18, 0); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PB19, 0); + at91_set_b_periph(AT91_PIN_PB19, 0); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD27, 0); + at91_set_b_periph(AT91_PIN_PD27, 0); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PB3, 0); @@ -113,24 +117,24 @@ void at91_spi0_hw_init(unsigned long cs_mask)

void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */

/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);

if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB17, 0); + at91_set_a_periph(AT91_PIN_PB17, 0); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PD28, 0); + at91_set_b_periph(AT91_PIN_PD28, 0); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PD18, 0); + at91_set_a_periph(AT91_PIN_PD18, 0); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PD19, 0); + at91_set_a_periph(AT91_PIN_PD19, 0); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PB17, 0); @@ -151,25 +155,25 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ + at91_set_a_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIN_PA15, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIN_PA12, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIN_PA13, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIN_PA16, 0); /* ERXER */ + at91_set_a_periph(AT91_PIN_PA14, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIN_PA10, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIN_PA11, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIN_PA19, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIN_PA18, 0); /* EMDC */ #ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ + at91_set_b_periph(AT91_PIN_PA29, 0); /* ECRS */ + at91_set_b_periph(AT91_PIN_PA30, 0); /* ECOL */ + at91_set_b_periph(AT91_PIN_PA8, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIN_PA9, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIN_PA28, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIN_PA6, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIN_PA7, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIN_PA27, 0); /* ETXER */ #endif } #endif diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..86864dd 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -23,6 +23,10 @@ */

#include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> @@ -30,29 +34,29 @@

void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIN_PA6, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIN_PA7, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); }

void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIN_PA11, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIN_PA12, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); }

void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIN_PA13, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIN_PA14, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); }

void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ + at91_set_a_periph(AT91_PIN_PA21, 0); /* DRXD */ + at91_set_a_periph(AT91_PIN_PA22, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); }

@@ -78,24 +82,24 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */

/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);

if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA28, 1); + at91_set_a_periph(AT91_PIN_PA28, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PB7, 1); + at91_set_b_periph(AT91_PIN_PB7, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PD8, 1); + at91_set_a_periph(AT91_PIN_PD8, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD9, 1); + at91_set_b_periph(AT91_PIN_PD9, 1); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PA28, 1); diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 574f488..b3a5d78 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -13,9 +13,9 @@

#include <config.h> #include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h>

static unsigned long cpu_clk_rate_hz; static unsigned long main_clk_rate_hz; @@ -57,13 +57,13 @@ u32 get_pllb_init(void) static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { - case AT91_PMC_CSS_SLOW: + case AT91_PMC_MCKR_CSS_SLOW: return AT91_SLOW_CLOCK; - case AT91_PMC_CSS_MAIN: + case AT91_PMC_MCKR_CSS_MAIN: return main_clk_rate_hz; - case AT91_PMC_CSS_PLLA: + case AT91_PMC_MCKR_CSS_PLLA: return plla_rate_hz; - case AT91_PMC_CSS_PLLB: + case AT91_PMC_MCKR_CSS_PLLB: return pllb_rate_hz; }

@@ -146,6 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; #ifndef AT91_MAIN_CLOCK unsigned tmp; /* @@ -164,7 +165,7 @@ int at91_clock_init(unsigned long main_clock) main_clk_rate_hz = main_clock;

/* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));

#ifdef CONFIG_USB_ATMEL /* @@ -174,7 +175,7 @@ int at91_clock_init(unsigned long main_clock) * REVISIT: assumes MCK doesn't derive from PLLB! */ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_USB96M; + AT91_PMC_PLLBR_USBDIV_2; pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); #endif

@@ -182,28 +183,32 @@ int at91_clock_init(unsigned long main_clock) * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = readl(&pmc->mckr); #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* plla divisor by 2 */ plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif - freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = mck_rate_hz;

- freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* mdiv */ + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #elif defined(CONFIG_AT91SAM9G20) - mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? - freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #endif cpu_clk_rate_hz = freq;

- return 0; + return 0; } diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..993b299 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -22,6 +22,10 @@ */

#include <common.h> +#ifdef CONFIG_AT91_LEGACY +#warning Your board is using legacy SoC access. Please update! +#endif + #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c index be68f59..0a0bb57 100644 --- a/cpu/arm926ejs/at91/led.c +++ b/cpu/arm926ejs/at91/led.c @@ -23,7 +23,14 @@ */

#include <common.h> +/* +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif +*/ #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h>

diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index f11ebc6..d9aec1b 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -27,15 +27,20 @@ */

#include <config.h> -#include <version.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_wdt.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_matrix.h> #include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_rstc.h> +#ifdef CONFIG_AT91_LEGACY +#include <asm/arch/at91sam9_matrix.h> +#endif +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#endif

_TEXT_BASE: .word TEXT_BASE @@ -75,7 +80,7 @@ POS1: * - Check if the PLL is already initialized * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) ldr r0, [r1] and r0, r0, #3 cmp r0, #0 @@ -85,18 +90,18 @@ POS1: * - Enable the Main Oscillator * --------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r1, =(AT91_ASM_PMC_MOR) + ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1]

/* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS + mov r4, #AT91_PMC_IxR_MOSCS MOSCS_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS + cmp r3, #AT91_PMC_IxR_MOSCS bne MOSCS_Loop

/* ---------------------------------------------------------------------------- @@ -105,56 +110,71 @@ MOSCS_Loop: * Setup PLLA * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r1, =(AT91_ASM_PMC_PLLAR) ldr r0, =CONFIG_SYS_PLLAR_VAL str r0, [r1]

/* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA + mov r4, #AT91_PMC_IxR_LOCKA MOSCS_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA + cmp r3, #AT91_PMC_IxR_LOCKA bne MOSCS_Loop1

+#ifdef CONFIG_SYS_PLLBR_VAL + ldr r1, =(AT91_ASM_PMC_PLLBR) + ldr r0, =CONFIG_SYS_PLLBR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLB is locked */ + mov r4, #AT91_PMC_IxR_LOCKB +PLLB_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IxR_LOCKB + bne PLLB_Loop +#endif + /* ---------------------------------------------------------------------------- * PMC Init Step 3. * ---------------------------------------------------------------------------- * - Switch on the Main Oscillator * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR)

/* -Master Clock Controller register PMC_MCKR */ ldr r0, =CONFIG_SYS_MCKR1_VAL str r0, [r1]

/* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IxR_MCKRDY MCKRDY_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IxR_MCKRDY bne MCKRDY_Loop

ldr r0, =CONFIG_SYS_MCKR2_VAL str r0, [r1]

/* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IxR_MCKRDY MCKRDY_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IxR_MCKRDY bne MCKRDY_Loop1 - PLL_setup_end:

/* ---------------------------------------------------------------------------- * - memory control configuration 2 * ---------------------------------------------------------------------------- */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + + ldr r0, =(AT91_ASM_SDRAMC_TR) + ldr r1, [r0] cmp r1, #0 bne SDRAM_setup_end @@ -183,60 +203,52 @@ SDRAM_setup_end: .ltorg

SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) + .word AT91_ASM_WDT_MR .word CONFIG_SYS_WDTC_WDMR_VAL - /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word AT91_ASM_PIOD_PDR .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word AT91_ASM_PIOD_PUDR .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word AT91_ASM_PIOD_ASR .word CONFIG_SYS_PIOD_PPUDR_VAL -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ - || defined(CONFIG_AT91SAM9G20) - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) + .word AT91_ASM_PIOC_PDR .word CONFIG_SYS_PIOC_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word AT91_ASM_PIOC_PUDR .word CONFIG_SYS_PIOC_PPUDR_VAL #endif - -#if defined(AT91_MATRIX_EBI0CSA) - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL -#else /* AT91_MATRIX_EBICSA */ - .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word AT91_ASM_MATRIX_CSA0 .word CONFIG_SYS_MATRIX_EBICSA_VAL -#endif

/* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word AT91_ASM_SMC_MODE0 .word CONFIG_SYS_SMC0_MODE0_VAL

- .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word AT91_ASM_SMC_CYCLE0 .word CONFIG_SYS_SMC0_CYCLE0_VAL

- .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word AT91_ASM_SMC_PULSE0 .word CONFIG_SYS_SMC0_PULSE0_VAL

- .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word AT91_ASM_SMC_SETUP0 .word CONFIG_SYS_SMC0_SETUP0_VAL

SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word AT91_ASM_SDRAMC_CR .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word AT91_ASM_SDRAMC_MDR .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 @@ -254,26 +266,25 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL8 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word AT91_ASM_MATRIX_MCFG .word 0x1FF #endif - SMRDATA2: .word 0 diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c index f963e14..1b67e77 100644 --- a/cpu/arm926ejs/at91/reset.c +++ b/cpu/arm926ejs/at91/reset.c @@ -32,10 +32,12 @@ */ void reset_cpu(ulong ignored) { + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + /* this is the way Linux does it */ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | - AT91_RSTC_PROCRST | - AT91_RSTC_PERRST); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, + &rstc->cr);

while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index 7352b5c..5449dfb 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -35,8 +35,6 @@ * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) -#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)

static ulong timestamp; static ulong lastinc; @@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) /* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer);

/* Enable PITC */ - at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

reset_timer_masked();

@@ -82,7 +82,9 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + ulong now = readl(&pit->piir);

if (now >= lastinc) /* normal mode (non roll) */ /* move stamp forward with absolut diff ticks */ @@ -96,7 +98,9 @@ unsigned long long get_ticks(void) void reset_timer_masked(void) { /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + lastinc = readl(&pit->piir); /* capture current incrementer value time */ timestamp = 0; /* start "advancing" time stamp from 0 */ }

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index acba56c..d966082 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk

LIB := $(obj)libgpio.a

+COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 9a48783..e0cf1e1 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -30,14 +30,15 @@ #include <ioports.h> #include <asm/io.h> #endif -#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ +#if defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263) #include <asm/io.h> #include <asm/arch/hardware.h> -#endif -#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ -#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#ifdef CONFIG_AT91_LEGACY #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#endif #endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fc9887b..3899052 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a

COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o diff --git a/drivers/serial/at91rm9200_usart.c b/drivers/serial/at91rm9200_usart.c index 858bde9..05ebbc3 100644 --- a/drivers/serial/at91rm9200_usart.c +++ b/drivers/serial/at91rm9200_usart.c @@ -30,8 +30,16 @@ */

#include <common.h> + +#ifndef CONFIG_AT91_LEGACY #include <asm/io.h> #include <asm/arch/hardware.h> +#define CONFIG_AT91_LEGACY +#include <asm/arch-at91rm9200/AT91RM9200.h> +#warning Please update to use C structur SoC access ! +#else +#include <asm/arch/AT91RM9200.h> +#endif

DECLARE_GLOBAL_DATA_PTR;

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f50552a..cad3412 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -16,6 +16,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <watchdog.h>

#include <asm/io.h> diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 3a648e6..4a5c4aa 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -20,6 +20,10 @@ */

#include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/hardware.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 226859a..29f3ba1 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,6 +25,11 @@

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)

+#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif + #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 7726bb3..4d54a17 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -31,9 +31,26 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE));

#ifdef CONFIG_AT91RM9200 #include <asm/arch/hardware.h> + #include <asm/arch/at91_pio.h> + #ifndef VCBITMASK #define VCBITMASK(bitno) (0x0001 << (bitno % 16)) #endif +#ifndef CONFIG_AT91_LEGACY +at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; +#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ + writel(PIN, &pio->PORT.per); \ + writel(PIN, &pio->PORT.DDR); \ + writel(PIN, &pio->PORT.mddr); \ + if (!I0O1) writel(PIN, &pio->PORT.puer); + +#define VCXK_SET_PIN(PORT, PIN) writel(PIN,&pio->PORT.sodr); +#define VCXK_CLR_PIN(PORT, PIN) writel(PIN,&pio->PORT.codr); + +#define VCXK_ACKNOWLEDGE \ + (!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \ + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) +#else #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ ((AT91PS_PIO) PORT)->PIO_PER = PIN; \ ((AT91PS_PIO) PORT)->DDR = PIN; \ @@ -46,7 +63,7 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #define VCXK_ACKNOWLEDGE \ (!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\ PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) - +#endif #elif defined(CONFIG_MCF52x2) #include <asm/m5282.h> #ifndef VCBITMASK diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h index f6ce1f9..af598f2 100644 --- a/include/asm-arm/arch-at91/at91_pio.h +++ b/include/asm-arm/arch-at91/at91_pio.h @@ -7,6 +7,9 @@ * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. * + * C stuct access by Jens Scharsig 2009 based on + * AT91RM9200 datasheet revision I and AT91SAM9263 datasheet revision G + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -16,6 +19,109 @@ #ifndef AT91_PIO_H #define AT91_PIO_H

+#ifdef __ASSEMBLY__ + +#define AT91_ASM_PIO_RANGE 0x200 +#define AT91_ASM_PIOC_PDR \ + (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04) +#define AT91_ASM_PIOC_PUDR \ + (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60) + +#define AT91_ASM_PIOD_PDR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04) +#define AT91_ASM_PIOD_PUDR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60) +#define AT91_ASM_PIOD_ASR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70) + +#else + +typedef struct at91_port { + u32 per; /* 0x00 PIO Enable Register */ + u32 pdr; /* 0x04 PIO Disable Register */ + u32 psr; /* 0x08 PIO Status Register */ + u32 reserved0; + u32 oer; /* 0x10 Output Enable Register */ + u32 odr; /* 0x14 Output Disable Registerr */ + u32 osr; /* 0x18 Output Status Register */ + u32 reserved1; + u32 ifer; /* 0x20 Input Filter Enable Register */ + u32 ifdr; /* 0x24 Input Filter Disable Register */ + u32 ifsr; /* 0x28 Input Filter Status Register */ + u32 reserved2; + u32 sodr; /* 0x30 Set Output Data Register */ + u32 codr; /* 0x34 Clear Output Data Register */ + u32 odsr; /* 0x38 Output Data Status Register */ + u32 pdsr; /* 0x3C Pin Data Status Register */ + u32 ier; /* 0x40 Interrupt Enable Register */ + u32 idr; /* 0x44 Interrupt Disable Register */ + u32 imr; /* 0x48 Interrupt Mask Register */ + u32 isr; /* 0x4C Interrupt Status Register */ + u32 mder; /* 0x50 Multi-driver Enable Register */ + u32 mddr; /* 0x54 Multi-driver Disable Register */ + u32 mdsr; /* 0x58 Multi-driver Status Register */ + u32 reserved3; + u32 pudr; /* 0x60 Pull-up Disable Register */ + u32 puer; /* 0x64 Pull-up Enable Register */ + u32 pusr; /* 0x68 Pad Pull-up Status Register */ + u32 reserved4; + u32 asr; /* 0x70 Select A Register */ + u32 bsr; /* 0x74 Select B Register */ + u32 absr; /* 0x78 AB Select Status Register */ + u32 reserved5[9]; /* */ + u32 ower; /* 0xA0 Output Write Enable Register */ + u32 owdr; /* 0xA4 Output Write Disable Register */ + u32 owsr; /* OxA8 utput Write Status Register */ + u32 reserved6[85]; +} at91_port_t; + +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) +#define AT91_PIO_PORTS 3 +#elif defined(CONFIG_AT91SAM9263) +#define AT91_PIO_PORTS 5 +#else +#define AT91_PIO_PORTS 4 +#endif + +typedef union at91_pio { + struct { + at91_port_t pioa; + at91_port_t piob; + at91_port_t pioc; + #if (AT91_PIO_PORTS > 3) + at91_port_t piod; + #endif + #if (AT91_PIO_PORTS > 4) + at91_port_t pioe; + #endif + } ; + at91_port_t port[AT91_PIO_PORTS]; +} at91_pio_t; + +#ifdef CONFIG_AT91_GPIO +int at91_set_gpio_periph(u32 pin, int use_pullup); +int at91_set_a_periph(u32 pin, int use_pullup); +int at91_set_b_periph(u32 pin, int use_pullup); +int at91_set_gpio_input(u32 pin, int use_pullup); +int at91_set_gpio_output(u32 pin, int value); +int at91_set_deglitch(u32 pin, int is_on); +int at91_set_multi_drive(u32 pin, int is_on); +int at91_set_gpio_value(u32 pin, int value); +int at91_get_gpio_value(u32 pin); +#endif + +#endif + +#define AT91_PIN_TO_MASK(x) (1<<x) +#define AT91_PORTPIN(PORT, PIN) ((0x0##PORT - 9) * 32 + ((PIN) & 0x1F)) +#define AT91_PIO_PORTA 0x0 +#define AT91_PIO_PORTB 0x1 +#define AT91_PIO_PORTC 0x2 +#define AT91_PIO_PORTD 0x3 +#define AT91_PIO_PORTE 0x4 + +#ifdef CONFIG_AT91_LEGACY + #define PIO_PER 0x00 /* Enable Register */ #define PIO_PDR 0x04 /* Disable Register */ #define PIO_PSR 0x08 /* Status Register */ @@ -45,5 +151,6 @@ #define PIO_OWER 0xa0 /* Output Write Enable Register */ #define PIO_OWDR 0xa4 /* Output Write Disable Register */ #define PIO_OWSR 0xa8 /* Output Write Status Register */ +#endif

#endif diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h index 94dd242..5615a02 100644 --- a/include/asm-arm/arch-at91/at91_pit.h +++ b/include/asm-arm/arch-at91/at91_pit.h @@ -16,6 +16,20 @@ #ifndef AT91_PIT_H #define AT91_PIT_H

+typedef struct at91_pit { + u32 mr; /* 0x00 Mode Register */ + u32 sr; /* 0x04 Status Register */ + u32 pivr; /* 0x08 Periodic Interval Value Register */ + u32 piir; /* 0x0C Periodic Interval Image Register */ +} at91_pit_t; + +#define AT91_PIT_MR_IEN 0x02000000 +#define AT91_PIT_MR_EN 0x01000000 +#define AT91_PIT_MR_PIV_MASK (x & 0x000fffff) +#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) + +#ifdef CONFIG_AT91_LEGACY + #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ @@ -29,4 +43,5 @@ #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */

+#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 9fe94c7..8f0421a 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -7,6 +7,10 @@ * Power Management Controller (PMC) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. * + * C stuct access by Jens Scharsig 2009 based on + * AT91RM9200 datasheet revision I and AT91SAM9263 datasheet revision G + * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -16,6 +20,103 @@ #ifndef AT91_PMC_H #define AT91_PMC_H

+#ifdef __ASSEMBLY__ + +#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) +#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) +#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) +#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) +#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) + +#else + +typedef struct at91_pmc { + u32 scer; /* 0x00 System Clock Enable Register */ + u32 scdr; /* 0x04 System Clock Disable Register */ + u32 scsr; /* 0x08 System Clock Status Register */ + u32 reserved0; + u32 pcer; /* 0x10 Peripheral Clock Enable Register */ + u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ + u32 pcsr; /* 0x18 Peripheral Clock Status Register */ + u32 reserved1; + u32 mor; /* 0x20 Main Oscilator Register */ + u32 mcfr; /* 0x24 Main Clock Frequency Register */ + u32 pllar; /* 0x28 PLL A Register */ + u32 pllbr; /* 0x2C PLL B Register */ + u32 mckr; /* 0x30 Master Clock Register */ + u32 reserved2[3]; + u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ + u32 reserved3[4]; + u32 ier; /* 0x60 Interrupt Enable Register */ + u32 idr; /* 0x64 Interrupt Disable Register */ + u32 sr; /* 0x68 Status Register */ + u32 imr; /* 0x6C Interrupt Mask Register */ + u32 reserved4[4]; +#ifdef CONFIG_AT91SAM9 + u32 pllicpr; /* 0x80 Change Pump Current Register */ +#else + u32 reserved5; +#endif + u32 reserved6[21]; +#ifdef CONFIG_AT91CAP9 + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE8 Write Protect Status Register */ +#else + u32 reserved7[2]; +#endif + u32 reserved8[5]; +} at91_pmc_t; + +#endif /* end assembly */ + +#define AT91_PMC_MOR_MOSCEN 0x01 +#define AT91_PMC_MOR_OSCBYPASS 0x02 +#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) + +#define AT91_PMC_PLLxR_DIV(x) (x & 0xFF) +#define AT91_PMC_PLLxR_PLLCOUNT(x) ((x & 0x3F) << 8) +#define AT91_PMC_PLLxR_OUT(x) ((x & 0x03) << 14) +#define AT91_PMC_PLLxR_MUL(x) ((x & 0x7FF) << 16) +#define AT91_PMC_PLLAR_29 0x20000000 +#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 +#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 +#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 + +#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 +#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 +#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 +#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 +#define AT91_PMC_MCKR_CSS_MASK 0x00000003 + +#define AT91_PMC_MCKR_PRES_1 0x00000000 +#define AT91_PMC_MCKR_PRES_2 0x00000004 +#define AT91_PMC_MCKR_PRES_4 0x00000008 +#define AT91_PMC_MCKR_PRES_8 0x0000000C +#define AT91_PMC_MCKR_PRES_16 0x00000010 +#define AT91_PMC_MCKR_PRES_32 0x00000014 +#define AT91_PMC_MCKR_PRES_64 0x00000018 +#define AT91_PMC_MCKR_PRES_MASK 0x0000001C + +#define AT91_PMC_MCKR_MDIV_1 0x00000000 +#define AT91_PMC_MCKR_MDIV_2 0x00000100 +#define AT91_PMC_MCKR_MDIV_4 0x00000200 +#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 + +#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 + +#define AT91_PMC_IxR_MOSCS 0x00000001 +#define AT91_PMC_IxR_LOCKA 0x00000002 +#define AT91_PMC_IxR_LOCKB 0x00000004 +#define AT91_PMC_IxR_MCKRDY 0x00000008 +#define AT91_PMC_IxR_LOCKU 0x00000040 +#define AT91_PMC_IxR_PCKRDY0 0x00000100 +#define AT91_PMC_IxR_PCKRDY1 0x00000200 +#define AT91_PMC_IxR_PCKRDY2 0x00000400 +#define AT91_PMC_IxR_PCKRDY3 0x00000800 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */

@@ -117,4 +218,5 @@

#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */

+#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h index e49caef..86f4ffb 100644 --- a/include/asm-arm/arch-at91/at91_rstc.h +++ b/include/asm-arm/arch-at91/at91_rstc.h @@ -16,11 +16,37 @@ #ifndef AT91_RSTC_H #define AT91_RSTC_H

+#ifdef __ASSEMBLY__ +#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) +#else + +typedef struct at91_rstc { + u32 cr; /* Reset Controller Control Register */ + u32 sr; /* Reset Controller Status Register */ + u32 mr; /* Reset Controller Mode Register */ +} at91_rstc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_RSTC_KEY 0xA5000000 + +#define AT91_RSTC_CR_PROCRST 0x00000001 +#define AT91_RSTC_CR_PERRST 0x00000004 +#define AT91_RSTC_CR_EXTRST 0x00000008 + +#define AT91_RSTC_MR_URSTEN 0x00000001 +#define AT91_RSTC_MR_URSTIEN 0x00000010 +#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) +#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 + +#define AT91_RSTC_SR_NRSTL 0x00010000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */

#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ @@ -38,4 +64,6 @@ #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */

+#endif /* CONFIG_AT91_LEGACY */ + #endif diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h index 30643c6..c520e89 100644 --- a/include/asm-arm/arch-at91/at91_spi.h +++ b/include/asm-arm/arch-at91/at91_spi.h @@ -16,6 +16,25 @@ #ifndef AT91_SPI_H #define AT91_SPI_H

+#include <asm/arch/at91_pdc.h> + +typedef struct at91_spi { + u32 cr; /* 0x00 Control Register */ + u32 mr; /* 0x04 Mode Register */ + u32 rdr; /* 0x08 Receive Data Register */ + u32 tdr; /* 0x0C Transmit Data Register */ + u32 sr; /* 0x10 Status Register */ + u32 ier; /* 0x14 Interrupt Enable Register */ + u32 idr; /* 0x18 Interrupt Disable Register */ + u32 imr; /* 0x1C Interrupt Mask Register */ + u32 reserve1[4]; + u32 csr[4]; /* 0x30 Chip Select Register 0-3 */ + u32 reserve2[48]; + at91_pdc_t pdc; +} at91_spi_t; + +#ifdef CONFIG_AT91_LEGACY + #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ @@ -102,4 +121,6 @@

#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */

+#endif /* CONFIG_AT91_LEGACY */ + #endif diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h index 7e18537..cf08daf 100644 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -17,6 +17,34 @@ #ifndef AT91_WDT_H #define AT91_WDT_H

+#ifdef __ASSEMBLY__ + +#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) + +#else + +typedef struct at91_wdt { + u32 cr; + u32 mr; + u32 sr; +} at91_wdt_t; + +#endif + +#define AT91_WDT_CR_WDRSTT 1 +#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ + +#define AT91_WDT_MR_WDV(x) (x & 0xfff) +#define AT91_WDT_MR_WDFIEN 0x00001000 +#define AT91_WDT_MR_WDRSTEN 0x00002000 +#define AT91_WDT_MR_WDRPROC 0x00004000 +#define AT91_WDT_MR_WDDIS 0x00008000 +#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) +#define AT91_WDT_MR_WDDBGHLT 0x10000000 +#define AT91_WDT_MR_WDIDLEHLT 0x20000000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ @@ -35,4 +63,5 @@ #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */

+#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index b128ac5..c825710 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -53,6 +53,14 @@ #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */

+#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -119,6 +127,7 @@ #define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) #define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)

+#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 73975f4..fd38fab 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -49,6 +49,21 @@ #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */

+#define AT91_EMAC_BASE 0xfffc4000 + +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 + +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -105,6 +120,8 @@ #define AT91_USART4 AT91SAM9260_BASE_US4 #define AT91_USART5 AT91SAM9260_BASE_US5

+#endif /* CONFIG_AT91_LEGACY */ + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index b303e07..2fe9d17 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -43,6 +43,18 @@ #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */

+#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 + +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY

/* * User Peripheral physical base addresses. @@ -64,7 +76,6 @@ #define AT91SAM9261_BASE_SPI1 0xfffcc000 #define AT91_BASE_SYS 0xffffea00

- /* * System Peripherals (offset from AT91_BASE_SYS) */ @@ -88,6 +99,7 @@ #define AT91_USART1 AT91SAM9261_BASE_US1 #define AT91_USART2 AT91SAM9261_BASE_US2

+#endif /* CONFIG_AT91_LEGACY */

/* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 966a683..e52c297 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -47,6 +47,26 @@ #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */

+#define AT91_EMAC_BASE 0xfffbc000 + +#define AT91_ECC0_BASE 0xffffe000 +#define AT91_SDRAMC0_BASE 0xffffe200 +#define AT91_SMC0_BASE 0xffffe400 +#define AT91_ECC1_BASE 0xffffe600 +#define AT91_SDRAMC1_BASE 0xffffe800 +#define AT91_SMC1_BASE 0xffffea00 +#define AT91_MATRIX_BASE 0xffffec00 +#define AT91_CCFG_BASE 0xffffed10 +#define AT91_DBGU_BASE 0xffffee00 +#define AT91_AIC_BASE 0xfffff000 +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY

/* * User Peripheral physical base addresses. @@ -108,6 +128,8 @@ #define AT91_SMC AT91_SMC0 #define AT91_SDRAMC AT91_SDRAMC0

+#endif /* CONFIG_AT91_LEGACY */ + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h index 5af2b54..c3da3a6 100644 --- a/include/asm-arm/arch-at91/at91sam9_sdramc.h +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h @@ -17,6 +17,19 @@ #ifndef AT91SAM9_SDRAMC_H #define AT91SAM9_SDRAMC_H

+#ifdef __ASSEMBLY__ + +#ifndef AT91_SDRAMC_BASE +#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE +#endif + +#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE +#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) +#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) +#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) + +#endif + /* SDRAM Controller (SDRAMC) registers */ #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h index d64511b..cd143b1 100644 --- a/include/asm-arm/arch-at91/at91sam9_smc.h +++ b/include/asm-arm/arch-at91/at91sam9_smc.h @@ -16,6 +16,68 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H

+#ifdef __ASSEMBLY__ + +#ifndef AT91_SMC_BASE +#define AT91_SMC_BASE AT91_SMC0_BASE +#endif + +#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE +#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) +#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) +#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) + +#else + +typedef struct at91_cs { + u32 setup; /* 0x00 SMC Setup Register */ + u32 pulse; /* 0x04 SMC Pulse Register */ + u32 cycle; /* 0x08 SMC Cycle Register */ + u32 mode; /* 0x0C SMC Mode Register */ +} at91_cs_t; + +typedef struct at91_smc { + at91_cs_t cs[8]; +} at91_smc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ #define AT91_SMC_NWESETUP_(x) ((x) << 0) @@ -74,3 +136,4 @@ #endif

#endif +#endif