Hi Niklaus,

On Monday 14 January 2008, Niklaus Giger wrote:

I added POST (including POST_SPR) to my PPC440EPx based hcu5 board.

After running I did see by executin "log show" <..> <4>POST spr The value of DVLIM special register is incorrect: 0x00000000 <4>FAILED

I close inspection revealed that DVLIM is set to the correct value in _start_440, but afterwards reset to 0 in dflush.

I'm pretty sure you are not using the latest version here. I recently committed a patch from Larry to fix this problem by saving and restoring the DVLIM register in this routine. Please give the current version in the official U-Boot repo a try and let me know if the problem still exists.

Are there any special reasons, why dflush should manipulate DVLIM?

DVLIM can be modified for a locked d-cache for example.

Or would it be okay to submit a patch like: diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a730604..b8c33cc 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1700,8 +1700,6 @@ trap_reloc: rlwinm r8,r9,0,15,13 rlwinm r8,r8,0,17,15 mtmsr r8

• addi r3,r0,0x0000
• mtspr dvlim,r3

I'm wondering right now, if setting DVLIM to 0 is correct here. Shouldn't it be set to the default value 0x0001f800?

Any comments?

Thanks.

Best regards, Stefan

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