[RESEND PATCH v1 0/4] riscv: Initial support for Lichee PI 4A board
Sipeed's Lichee PI 4A board is based on T-HEAD's TH1520 SoC which consists of quad core XuanTie C910 CPU, plus one C906 CPU and one E902 CPU.
In this series, the UART, basic device tree, CPU, PLIC are enabled, making it capable of running in serial console mode.
Please note that, we rely on pre shipped vendor u-boot which run in M-Mode to chain load this mainline u-boot either via eMMC storage or from tftp, thus the pinctrl and clock setting are not implemented in this series, which certainly can be improved later accordingly.
Also the device tree is coming from kernel which is submitted by Jisheng Zhang in his patch V2 [1], it's still under review, so may change in the future.
[1] https://lore.kernel.org/all/20230518184541.2627-1-jszhang@kernel.org
Yixun Lan (4): riscv: t-head: licheepi4a: initial support added riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board configs: th1520_lpi4a_defconfig: Add initial config doc: t-head: lpi4a: document Lichee PI 4A board
arch/riscv/Kconfig | 5 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ board/thead/th1520_lpi4a/Kconfig | 42 ++ board/thead/th1520_lpi4a/MAINTAINERS | 7 + board/thead/th1520_lpi4a/Makefile | 5 + board/thead/th1520_lpi4a/board.c | 14 + configs/th1520_lpi4a_defconfig | 82 ++++ doc/board/index.rst | 1 + doc/board/thead/index.rst | 9 + doc/board/thead/lpi4a.rst | 112 +++++ include/configs/th1520_lpi4a.h | 22 + 14 files changed, 801 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 configs/th1520_lpi4a_defconfig create mode 100644 doc/board/thead/index.rst create mode 100644 doc/board/thead/lpi4a.rst create mode 100644 include/configs/th1520_lpi4a.h
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org --- arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A + bool "Support Sipeed's TH1520 Lichee PI 4A Board" + select SYS_CACHE_SHIFT_6 + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A + +config ARCH_THEAD + bool + default y + +config SYS_BOARD + default "th1520_lpi4a" + +config SYS_VENDOR + default "thead" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "th1520_lpi4a" + +config TEXT_BASE + default 0x01b00000 if SPL + default 0x01c00000 if !RISCV_SMODE + default 0x01c00000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if RISCV_SMODE + imply CMD_CPU + imply SMP + imply SUPPORT_OF_CONTROL + imply OF_CONTROL + imply OF_REAL + +endif diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS new file mode 100644 index 0000000000..36c7ab7cc3 --- /dev/null +++ b/board/thead/th1520_lpi4a/MAINTAINERS @@ -0,0 +1,7 @@ +Lichee PI 4A +M: Wei Fu wefu@redhat.com +M: Yixun Lan dlan@gentoo.org +S: Maintained +F: board/thead/th1520_lpi4a/ +F: configs/th1520_lpi4a_defconfig +F: doc/board/thead/lpi4a.rst diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile new file mode 100644 index 0000000000..9671b3bbb0 --- /dev/null +++ b/board/thead/th1520_lpi4a/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023, Yixun Lan dlan@gentoo.org + +obj-y += board.o diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023, Yixun Lan dlan@gentoo.org + * + */ + +#include <common.h> + +int board_init(void) +{ + enable_caches(); + + return 0; +} diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 0000000000..87496a52c4 --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Yixun Lan dlan@gentoo.org + * + */ + +#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H + +#include <linux/sizes.h> + +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32 + +/* Environment options */ + +#define CFG_EXTRA_ENV_SETTINGS \ + "PS1=[LPi4A]# \0" + +#endif /* __TH1520_LPI4A_H */
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"+config SYS_VENDOR
default "thead"+config SYS_CPU
default "generic"+config SYS_CONFIG_NAME
default "th1520_lpi4a"+config TEXT_BASE
default 0x01b00000 if SPLdefault 0x01c00000 if !RISCV_SMODEdefault 0x01c00000 if RISCV_SMODE+config SPL_TEXT_BASE
default 0x08000000+config SPL_OPENSBI_LOAD_ADDR
default 0x80000000+config BOARD_SPECIFIC_OPTIONS
def_bool yselect ARCH_EARLY_INIT_Rimply CPUimply CPU_RISCVimply RISCV_TIMER if RISCV_SMODEimply CMD_CPUimply SMPimply SUPPORT_OF_CONTROLimply OF_CONTROLimply OF_REAL+endif diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS new file mode 100644 index 0000000000..36c7ab7cc3 --- /dev/null +++ b/board/thead/th1520_lpi4a/MAINTAINERS @@ -0,0 +1,7 @@ +Lichee PI 4A +M: Wei Fu wefu@redhat.com +M: Yixun Lan dlan@gentoo.org +S: Maintained +F: board/thead/th1520_lpi4a/ +F: configs/th1520_lpi4a_defconfig +F: doc/board/thead/lpi4a.rst diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile new file mode 100644 index 0000000000..9671b3bbb0 --- /dev/null +++ b/board/thead/th1520_lpi4a/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023, Yixun Lan dlan@gentoo.org
+obj-y += board.o diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
enable_caches();return 0;+} diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 0000000000..87496a52c4 --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (c) 2023 Yixun Lan dlan@gentoo.org
- */
+#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H
+#include <linux/sizes.h>
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32
why couldn't we get it from dts? just like opensbi.
+/* Environment options */
+#define CFG_EXTRA_ENV_SETTINGS \
"PS1=[LPi4A]# \0"+#endif /* __TH1520_LPI4A_H */
2.40.0
Hi Guo:
On 09:45 Sat 27 May , Guo Ren wrote:
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"+config SYS_VENDOR
default "thead"+config SYS_CPU
default "generic"+config SYS_CONFIG_NAME
default "th1520_lpi4a"+config TEXT_BASE
default 0x01b00000 if SPLdefault 0x01c00000 if !RISCV_SMODEdefault 0x01c00000 if RISCV_SMODE+config SPL_TEXT_BASE
default 0x08000000+config SPL_OPENSBI_LOAD_ADDR
default 0x80000000+config BOARD_SPECIFIC_OPTIONS
def_bool yselect ARCH_EARLY_INIT_Rimply CPUimply CPU_RISCVimply RISCV_TIMER if RISCV_SMODEimply CMD_CPUimply SMPimply SUPPORT_OF_CONTROLimply OF_CONTROLimply OF_REAL+endif diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS new file mode 100644 index 0000000000..36c7ab7cc3 --- /dev/null +++ b/board/thead/th1520_lpi4a/MAINTAINERS @@ -0,0 +1,7 @@ +Lichee PI 4A +M: Wei Fu wefu@redhat.com +M: Yixun Lan dlan@gentoo.org +S: Maintained +F: board/thead/th1520_lpi4a/ +F: configs/th1520_lpi4a_defconfig +F: doc/board/thead/lpi4a.rst diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile new file mode 100644 index 0000000000..9671b3bbb0 --- /dev/null +++ b/board/thead/th1520_lpi4a/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023, Yixun Lan dlan@gentoo.org
+obj-y += board.o diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
enable_caches();return 0;+} diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 0000000000..87496a52c4 --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (c) 2023 Yixun Lan dlan@gentoo.org
- */
+#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H
+#include <linux/sizes.h>
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32
why couldn't we get it from dts? just like opensbi.
good catch! exactly these can be removed, I will fix in v2
+/* Environment options */
+#define CFG_EXTRA_ENV_SETTINGS \
"PS1=[LPi4A]# \0"+#endif /* __TH1520_LPI4A_H */
2.40.0
-- Best Regards Guo Ren
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"+config SYS_VENDOR
default "thread"
default "T-HEAD"
Thx
+config SYS_CPU
default "generic"+config SYS_CONFIG_NAME
default "th1520_lpi4a"+config TEXT_BASE
default 0x01b00000 if SPLdefault 0x01c00000 if !RISCV_SMODEdefault 0x01c00000 if RISCV_SMODE+config SPL_TEXT_BASE
default 0x08000000+config SPL_OPENSBI_LOAD_ADDR
default 0x80000000+config BOARD_SPECIFIC_OPTIONS
def_bool yselect ARCH_EARLY_INIT_Rimply CPUimply CPU_RISCVimply RISCV_TIMER if RISCV_SMODEimply CMD_CPUimply SMPimply SUPPORT_OF_CONTROLimply OF_CONTROLimply OF_REAL+endif diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS new file mode 100644 index 0000000000..36c7ab7cc3 --- /dev/null +++ b/board/thead/th1520_lpi4a/MAINTAINERS @@ -0,0 +1,7 @@ +Lichee PI 4A +M: Wei Fu wefu@redhat.com +M: Yixun Lan dlan@gentoo.org +S: Maintained +F: board/thead/th1520_lpi4a/ +F: configs/th1520_lpi4a_defconfig +F: doc/board/thead/lpi4a.rst diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile new file mode 100644 index 0000000000..9671b3bbb0 --- /dev/null +++ b/board/thead/th1520_lpi4a/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023, Yixun Lan dlan@gentoo.org
+obj-y += board.o diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
enable_caches();return 0;+} diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 0000000000..87496a52c4 --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (c) 2023 Yixun Lan dlan@gentoo.org
- */
+#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H
+#include <linux/sizes.h>
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32
+/* Environment options */
+#define CFG_EXTRA_ENV_SETTINGS \
"PS1=[LPi4A]# \0"+#endif /* __TH1520_LPI4A_H */
2.40.0
Hi Guo, Jisheng:
On 11:36 Sat 27 May , Guo Ren wrote:
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"
for the board, I'm not sure whether people will prefer to keep the 'th1520_' prefix, otherwise we could make it shorter, leave only 'lpi4a'? thoughts?
+config SYS_VENDOR
default "thread"
~~~~~~~ notice, in my original patch, it's 'thead'
default "T-HEAD"
No, here should be 'thead', since the CONFIG_SYS_VENDOR will form board/${CONFIG_SYS_VENDOR}, please consult arch/Kconfig for reference.
I personally would prefer 't-head' which probably cause less confusion.. but since kernel use 'thead'[1], so I just follow it to keep them aligned.
[1] in kernel, the dts path consist of 'thead', e.g. arch/riscv/boot/dts/thead/
Thx
+config SYS_CPU
default "generic"+config SYS_CONFIG_NAME
default "th1520_lpi4a"+config TEXT_BASE
default 0x01b00000 if SPLdefault 0x01c00000 if !RISCV_SMODEdefault 0x01c00000 if RISCV_SMODE+config SPL_TEXT_BASE
default 0x08000000+config SPL_OPENSBI_LOAD_ADDR
default 0x80000000+config BOARD_SPECIFIC_OPTIONS
def_bool yselect ARCH_EARLY_INIT_Rimply CPUimply CPU_RISCVimply RISCV_TIMER if RISCV_SMODEimply CMD_CPUimply SMPimply SUPPORT_OF_CONTROLimply OF_CONTROLimply OF_REAL+endif diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS new file mode 100644 index 0000000000..36c7ab7cc3 --- /dev/null +++ b/board/thead/th1520_lpi4a/MAINTAINERS @@ -0,0 +1,7 @@ +Lichee PI 4A +M: Wei Fu wefu@redhat.com +M: Yixun Lan dlan@gentoo.org +S: Maintained +F: board/thead/th1520_lpi4a/ +F: configs/th1520_lpi4a_defconfig +F: doc/board/thead/lpi4a.rst diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile new file mode 100644 index 0000000000..9671b3bbb0 --- /dev/null +++ b/board/thead/th1520_lpi4a/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023, Yixun Lan dlan@gentoo.org
+obj-y += board.o diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
enable_caches();return 0;+} diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 0000000000..87496a52c4 --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (c) 2023 Yixun Lan dlan@gentoo.org
- */
+#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H
+#include <linux/sizes.h>
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32
+/* Environment options */
+#define CFG_EXTRA_ENV_SETTINGS \
"PS1=[LPi4A]# \0"+#endif /* __TH1520_LPI4A_H */
2.40.0
-- Best Regards Guo Ren
On Sat, May 27, 2023 at 9:41 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo, Jisheng:
On 11:36 Sat 27 May , Guo Ren wrote:
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"for the board, I'm not sure whether people will prefer to keep the 'th1520_' prefix, otherwise we could make it shorter, leave only 'lpi4a'? thoughts?
+config SYS_VENDOR
default "thread"~~~~~~~ notice, in my original patch, it's 'thead'default "T-HEAD"
No, here should be 'thead', since the CONFIG_SYS_VENDOR will form board/${CONFIG_SYS_VENDOR}, please consult arch/Kconfig for reference.
I personally would prefer 't-head' which probably cause less confusion.. but since kernel use 'thead'[1], so I just follow it to keep them aligned.
But you have a typo here :)
[1] in kernel, the dts path consist of 'thead', e.g. arch/riscv/boot/dts/thead/
Regards, Bin
Hi Bin:
On 09:12 Mon 29 May , Bin Meng wrote:
On Sat, May 27, 2023 at 9:41 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo, Jisheng:
On 11:36 Sat 27 May , Guo Ren wrote:
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"for the board, I'm not sure whether people will prefer to keep the 'th1520_' prefix, otherwise we could make it shorter, leave only 'lpi4a'? thoughts?
+config SYS_VENDOR
default "thread"~~~~~~~ notice, in my original patch, it's 'thead'default "T-HEAD"
No, here should be 'thead', since the CONFIG_SYS_VENDOR will form board/${CONFIG_SYS_VENDOR}, please consult arch/Kconfig for reference.
I personally would prefer 't-head' which probably cause less confusion.. but since kernel use 'thead'[1], so I just follow it to keep them aligned.
But you have a typo here :)
do you mean 'thread'? It's 'thead' actually in my original patch, so no typo.. I was already trying to clarify this.
It's probably a grammar correction when Guo reply the email
https://lore.kernel.org/all/20230526124107.894-2-dlan@gentoo.org/
[1] in kernel, the dts path consist of 'thead', e.g. arch/riscv/boot/dts/thead/
Regards, Bin
On Mon, May 29, 2023 at 11:10 AM Yixun Lan dlan@gentoo.org wrote:
Hi Bin:
On 09:12 Mon 29 May , Bin Meng wrote:
On Sat, May 27, 2023 at 9:41 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo, Jisheng:
On 11:36 Sat 27 May , Guo Ren wrote:
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 5 ++++ board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++ board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++ board/thead/th1520_lpi4a/Makefile | 5 ++++ board/thead/th1520_lpi4a/board.c | 14 ++++++++++ include/configs/th1520_lpi4a.h | 22 +++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/thead/th1520_lpi4a/Kconfig create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS create mode 100644 board/thead/th1520_lpi4a/Makefile create mode 100644 board/thead/th1520_lpi4a/board.c create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..419b6171a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"select SYS_CACHE_SHIFT_6config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig new file mode 100644 index 0000000000..622246127c --- /dev/null +++ b/board/thead/th1520_lpi4a/Kconfig @@ -0,0 +1,42 @@ +if TARGET_TH1520_LPI4A
+config ARCH_THEAD
booldefault y+config SYS_BOARD
default "th1520_lpi4a"for the board, I'm not sure whether people will prefer to keep the 'th1520_' prefix, otherwise we could make it shorter, leave only 'lpi4a'? thoughts?
+config SYS_VENDOR
default "thread"~~~~~~~ notice, in my original patch, it's 'thead'default "T-HEAD"
No, here should be 'thead', since the CONFIG_SYS_VENDOR will form board/${CONFIG_SYS_VENDOR}, please consult arch/Kconfig for reference.
I personally would prefer 't-head' which probably cause less confusion.. but since kernel use 'thead'[1], so I just follow it to keep them aligned.
But you have a typo here :)
do you mean 'thread'? It's 'thead' actually in my original patch, so no typo.. I was already trying to clarify this.
It's probably a grammar correction when Guo reply the email
https://lore.kernel.org/all/20230526124107.894-2-dlan@gentoo.org/
[1] in kernel, the dts path consist of 'thead', e.g. arch/riscv/boot/dts/thead/
I see. Thanks for the clarification!
Regards, Bin
Hi YiXun, On Fri, May 26, 2023 at 08:41:04PM +0800, Yixun Lan wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org ... diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
- enable_caches();
There is a compilation warining here at "enable_caches" (probably due to cpu_func.h not being included to provide this function)
Best regards, Leo
- return 0;
+}
Hi Leo
On 02:55 Thu 29 Jun , Leo Liang wrote:
Hi YiXun, On Fri, May 26, 2023 at 08:41:04PM +0800, Yixun Lan wrote:
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org ... diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c new file mode 100644 index 0000000000..378bab098b --- /dev/null +++ b/board/thead/th1520_lpi4a/board.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023, Yixun Lan dlan@gentoo.org
- */
+#include <common.h>
+int board_init(void) +{
- enable_caches();
There is a compilation warining here at "enable_caches" (probably due to cpu_func.h not being included to provide this function)
thanks, will fix in v2
Best regards, Leo
- return 0;
+}
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "thead,th1520"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&c910_0>; + }; + + core1 { + cpu = <&c910_1>; + }; + + core2 { + cpu = <&c910_2>; + }; + + core3 { + cpu = <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpurst: cpurst { + compatible = "thead,reset-th1520"; + entry-reg = <0xff 0xff019050>; + entry-cnt = <4>; + control-reg = <0xff 0xff015004>; + control-val = <0x1c>; + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,th1520-plic", "thead,c900-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <240>; + }; + + clint: timer@ffdc000000 { + compatible = "thead,th1520-clint", "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x4000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +};
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
We shouldn't put it with two places, that would be bad for maintanice.
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};
This part has been changed.
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};This part has been changed.
noted, will update accordingly
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
-- Best Regards Guo Ren
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};This part has been changed.
noted, will update accordingly
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
Hi Guo:
see my comment below.
On 09:19 Mon 29 May , Guo Ren wrote:
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
I'd like to include dts in the first series, otherwise it won't be a complete working series, e.g. - not only it's unable to build, also can't do run-time test
I'm totally fine with kernel dts merged first, then submit this later, so no push..
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};This part has been changed.
noted, will update accordingly
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
On Mon, May 29, 2023 at 11:01 AM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
see my comment below.
On 09:19 Mon 29 May , Guo Ren wrote:
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
I'd like to include dts in the first series, otherwise it won't be a complete working series, e.g. - not only it's unable to build, also can't do run-time test
I couldn't make sense how it block your build, The build operation is controlled by you Makefile modification. right?
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
I'm totally fine with kernel dts merged first, then submit this later, so no push..
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};This part has been changed.
noted, will update accordingly
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
Hi Guo:
On 14:50 Mon 29 May , Guo Ren wrote:
On Mon, May 29, 2023 at 11:01 AM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
see my comment below.
On 09:19 Mon 29 May , Guo Ren wrote:
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
I'd like to include dts in the first series, otherwise it won't be a complete working series, e.g. - not only it's unable to build, also can't do run-time test
I couldn't make sense how it block your build, The build operation is controlled by you Makefile modification. right?
you mostly right, but in patch "[ 3/4 ] configs: th1520_lpi4a_defconfig: Add initial config", we will enable device tree, and require CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a.dtb" to be provided, also since UART's base register is parsed from dts (run time), so I see no reason why the dts patch should be separated
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
I'm totally fine with kernel dts merged first, then submit this later, so no push..
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote:
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ 4 files changed, 502 insertions(+) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000..dc00e3dfa0 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+/dts-v1/;
+#include "th1520.dtsi"
+/ {
model = "Sipeed Lichee Module 4A";compatible = "sipeed,lichee-module-4a", "thead,th1520";memory@0 {device_type = "memory";reg = <0x0 0x00000000 0x2 0x00000000>;};+};
+&osc {
clock-frequency = <24000000>;+};
+&osc_32k {
clock-frequency = <32768>;+};
+&apb_clk {
clock-frequency = <62500000>;+};
+&uart_sclk {
clock-frequency = <100000000>;+}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000..a1248b2ee3 --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include "th1520-lichee-module-4a.dtsi"
+/ {
model = "Sipeed Lichee Pi 4A";compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";aliases {gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;serial0 = &uart0;serial1 = &uart1;serial2 = &uart2;serial3 = &uart3;serial4 = &uart4;serial5 = &uart5;};chosen {stdout-path = "serial0:115200n8";};+};
+&uart0 {
status = "okay";+}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi new file mode 100644 index 0000000000..f62a62da6e --- /dev/null +++ b/arch/riscv/dts/th1520.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2021 Alibaba Group Holding Limited.
- Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org
- */
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
compatible = "thead,th1520";#address-cells = <2>;#size-cells = <2>;cpus: cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <3000000>;c910_0: cpu@0 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <0>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu0_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_1: cpu@1 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <1>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu1_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_2: cpu@2 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <2>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu2_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};c910_3: cpu@3 {compatible = "thead,c910", "riscv";device_type = "cpu";riscv,isa = "rv64imafdc";reg = <3>;i-cache-block-size = <64>;i-cache-size = <65536>;i-cache-sets = <512>;d-cache-block-size = <64>;d-cache-size = <65536>;d-cache-sets = <512>;next-level-cache = <&l2_cache>;mmu-type = "riscv,sv39";cpu3_intc: interrupt-controller {compatible = "riscv,cpu-intc";interrupt-controller;#interrupt-cells = <1>;};};cpu-map {cluster0 {core0 {cpu = <&c910_0>;};core1 {cpu = <&c910_1>;};core2 {cpu = <&c910_2>;};core3 {cpu = <&c910_3>;};};};l2_cache: l2-cache {compatible = "cache";cache-block-size = <64>;cache-level = <2>;cache-size = <1048576>;cache-sets = <1024>;cache-unified;};};osc: oscillator {compatible = "fixed-clock";clock-output-names = "osc_24m";#clock-cells = <0>;};osc_32k: 32k-oscillator {compatible = "fixed-clock";clock-output-names = "osc_32k";#clock-cells = <0>;};apb_clk: apb-clk-clock {compatible = "fixed-clock";clock-output-names = "apb_clk";#clock-cells = <0>;};uart_sclk: uart-sclk-clock {compatible = "fixed-clock";clock-output-names = "uart_sclk";#clock-cells = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&plic>;#address-cells = <2>;#size-cells = <2>;ranges;cpurst: cpurst {compatible = "thead,reset-th1520";entry-reg = <0xff 0xff019050>;entry-cnt = <4>;control-reg = <0xff 0xff015004>;control-val = <0x1c>;csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;};This part has been changed.
noted, will update accordingly
plic: interrupt-controller@ffd8000000 {compatible = "thead,th1520-plic", "thead,c900-plic";reg = <0xff 0xd8000000 0x0 0x01000000>;interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,<&cpu1_intc 11>, <&cpu1_intc 9>,<&cpu2_intc 11>, <&cpu2_intc 9>,<&cpu3_intc 11>, <&cpu3_intc 9>;interrupt-controller;#address-cells = <0>;#interrupt-cells = <2>;riscv,ndev = <240>;};clint: timer@ffdc000000 {compatible = "thead,th1520-clint", "thead,c900-clint";reg = <0xff 0xdc000000 0x0 0x00010000>;interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,<&cpu1_intc 3>, <&cpu1_intc 7>,<&cpu2_intc 3>, <&cpu2_intc 7>,<&cpu3_intc 3>, <&cpu3_intc 7>;};uart0: serial@ffe7014000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7014000 0x0 0x4000>;interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart1: serial@ffe7f00000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f00000 0x0 0x4000>;interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart3: serial@ffe7f04000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xe7f04000 0x0 0x4000>;interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};gpio2: gpio@ffe7f34000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f34000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portc: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;};};gpio3: gpio@ffe7f38000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xe7f38000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portd: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;};};gpio0: gpio@ffec005000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec005000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;};};gpio1: gpio@ffec006000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xec006000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;};};uart2: serial@ffec010000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xec010000 0x0 0x4000>;interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer0: timer@ffefc32000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer1: timer@ffefc32014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer2: timer@ffefc32028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc32028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer3: timer@ffefc3203c {compatible = "snps,dw-apb-timer";reg = <0xff 0xefc3203c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};uart4: serial@fff7f08000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f08000 0x0 0x4000>;interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};uart5: serial@fff7f0c000 {compatible = "snps,dw-apb-uart";reg = <0xff 0xf7f0c000 0x0 0x4000>;interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;clocks = <&uart_sclk>;reg-shift = <2>;reg-io-width = <4>;status = "disabled";};timer4: timer@ffffc33000 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33000 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer5: timer@ffffc33014 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33014 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer6: timer@ffffc33028 {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc33028 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};timer7: timer@ffffc3303c {compatible = "snps,dw-apb-timer";reg = <0xff 0xffc3303c 0x0 0x14>;clocks = <&apb_clk>;clock-names = "timer";interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};ao_gpio0: gpio@fffff41000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff41000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;porte: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;};};ao_gpio1: gpio@fffff52000 {compatible = "snps,dw-apb-gpio";reg = <0xff 0xfff52000 0x0 0x1000>;#address-cells = <1>;#size-cells = <0>;portf: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;ngpios = <32>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;};};};+};
2.40.0
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
On Mon, May 29, 2023 at 3:54 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 14:50 Mon 29 May , Guo Ren wrote:
On Mon, May 29, 2023 at 11:01 AM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
see my comment below.
On 09:19 Mon 29 May , Guo Ren wrote:
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote:
Sorry, why we need dts here? If we put dts here, we could delete the one in Linux.
No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
We shouldn't put it with two places, that would be bad for maintanice.
I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
I'd like to include dts in the first series, otherwise it won't be a complete working series, e.g. - not only it's unable to build, also can't do run-time test
I couldn't make sense how it block your build, The build operation is controlled by you Makefile modification. right?
you mostly right, but in patch "[ 3/4 ] configs: th1520_lpi4a_defconfig: Add initial config", we will enable device tree, and require CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a.dtb" to be provided, also since UART's base register is parsed from dts (run time), so I see no reason why the dts patch should be separated
Oh, I see; u-boot needs a seperate dtb to boot indepedent. Maybe, we just keep a minimum dts here, then we needn't syncronize with the kernel side.
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
I'm totally fine with kernel dts merged first, then submit this later, so no push..
On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote: > > Only add basic support for CPU, PLIC UART and Timer. > > Reviewed-by: Wei Fu wefu@redhat.com > Signed-off-by: Yixun Lan dlan@gentoo.org > --- > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ > 4 files changed, 502 insertions(+) > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > create mode 100644 arch/riscv/dts/th1520.dtsi > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > index 79a58694f5..72fd815a40 100644 > --- a/arch/riscv/dts/Makefile > +++ b/arch/riscv/dts/Makefile > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb > include $(srctree)/scripts/Makefile.dts > > targets += $(dtb-y) > diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > new file mode 100644 > index 0000000000..dc00e3dfa0 > --- /dev/null > +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > + */ > + > +/dts-v1/; > + > +#include "th1520.dtsi" > + > +/ { > + model = "Sipeed Lichee Module 4A"; > + compatible = "sipeed,lichee-module-4a", "thead,th1520"; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x2 0x00000000>; > + }; > +}; > + > +&osc { > + clock-frequency = <24000000>; > +}; > + > +&osc_32k { > + clock-frequency = <32768>; > +}; > + > +&apb_clk { > + clock-frequency = <62500000>; > +}; > + > +&uart_sclk { > + clock-frequency = <100000000>; > +}; > diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts > new file mode 100644 > index 0000000000..a1248b2ee3 > --- /dev/null > +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > + */ > + > +#include "th1520-lichee-module-4a.dtsi" > + > +/ { > + model = "Sipeed Lichee Pi 4A"; > + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; > + > + aliases { > + gpio0 = &gpio0; > + gpio1 = &gpio1; > + gpio2 = &gpio2; > + gpio3 = &gpio3; > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi > new file mode 100644 > index 0000000000..f62a62da6e > --- /dev/null > +++ b/arch/riscv/dts/th1520.dtsi > @@ -0,0 +1,435 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Alibaba Group Holding Limited. > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "thead,th1520"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus: cpus {
We needn't multi-cpus definitions.
> + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <3000000>; > + > + c910_0: cpu@0 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <0>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_1: cpu@1 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <1>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_2: cpu@2 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <2>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_3: cpu@3 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <3>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&c910_0>; > + }; > + > + core1 { > + cpu = <&c910_1>; > + }; > + > + core2 { > + cpu = <&c910_2>; > + }; > + > + core3 { > + cpu = <&c910_3>; > + }; > + }; > + }; > + > + l2_cache: l2-cache {
We also needn't l2_cache description for u-boot.
> + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-size = <1048576>; > + cache-sets = <1024>; > + cache-unified; > + }; > + }; > + > + osc: oscillator {
Does u-boot need it?
> + compatible = "fixed-clock"; > + clock-output-names = "osc_24m"; > + #clock-cells = <0>; > + }; > + > + osc_32k: 32k-oscillator {
Does u-boot need it?
> + compatible = "fixed-clock"; > + clock-output-names = "osc_32k"; > + #clock-cells = <0>; > + }; > + > + apb_clk: apb-clk-clock {
Does u-boot need it?
> + compatible = "fixed-clock"; > + clock-output-names = "apb_clk"; > + #clock-cells = <0>; > + }; > + > + uart_sclk: uart-sclk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "uart_sclk"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + cpurst: cpurst {
The u-boot needn't it
> + compatible = "thead,reset-th1520"; > + entry-reg = <0xff 0xff019050>; > + entry-cnt = <4>; > + control-reg = <0xff 0xff015004>; > + control-val = <0x1c>; > + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; > + }; This part has been changed.
noted, will update accordingly
> + > + plic: interrupt-controller@ffd8000000 { > + compatible = "thead,th1520-plic", "thead,c900-plic"; > + reg = <0xff 0xd8000000 0x0 0x01000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <240>; > + }; > + > + clint: timer@ffdc000000 { > + compatible = "thead,th1520-clint", "thead,c900-clint"; > + reg = <0xff 0xdc000000 0x0 0x00010000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>; > + }; > + > + uart0: serial@ffe7014000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7014000 0x0 0x4000>; > + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: serial@ffe7f00000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f00000 0x0 0x4000>; > + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@ffe7f04000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f04000 0x0 0x4000>; > + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + gpio2: gpio@ffe7f34000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f34000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portc: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio3: gpio@ffe7f38000 {
Do we enable the gpio driver in u-boot?
> + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f38000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portd: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio0: gpio@ffec005000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec005000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porta: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio1: gpio@ffec006000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec006000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + uart2: serial@ffec010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xec010000 0x0 0x4000>; > + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + timer0: timer@ffefc32000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer1: timer@ffefc32014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer2: timer@ffefc32028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer3: timer@ffefc3203c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc3203c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + uart4: serial@fff7f08000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f08000 0x0 0x4000>; > + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart5: serial@fff7f0c000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f0c000 0x0 0x4000>; > + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + timer4: timer@ffffc33000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer5: timer@ffffc33014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer6: timer@ffffc33028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer7: timer@ffffc3303c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc3303c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + ao_gpio0: gpio@fffff41000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff41000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porte: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + ao_gpio1: gpio@fffff52000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff52000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portf: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > +}; > -- > 2.40.0 >
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
Hi Guo:
On 16:22 Mon 29 May , Guo Ren wrote:
On Mon, May 29, 2023 at 3:54 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 14:50 Mon 29 May , Guo Ren wrote:
On Mon, May 29, 2023 at 11:01 AM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
see my comment below.
On 09:19 Mon 29 May , Guo Ren wrote:
On Sat, May 27, 2023 at 5:17 PM Yixun Lan dlan@gentoo.org wrote:
Hi Guo:
On 09:43 Sat 27 May , Guo Ren wrote: > Sorry, why we need dts here? If we put dts here, we could delete the > one in Linux. No, I think it's more than a historical reason for why we have two dts both in u-boot and kernel. And this dts here is merely used by u-boot, it could be a simplified version comparing to kernel's dts.
> > We shouldn't put it with two places, that would be bad for maintanice. I can totally understand your concern, in fact, we are trying to keep them sync, so I will probably wait the dts of kernel settle down, before take action here. so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
I'd like to include dts in the first series, otherwise it won't be a complete working series, e.g. - not only it's unable to build, also can't do run-time test
I couldn't make sense how it block your build, The build operation is controlled by you Makefile modification. right?
you mostly right, but in patch "[ 3/4 ] configs: th1520_lpi4a_defconfig: Add initial config", we will enable device tree, and require CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a.dtb" to be provided, also since UART's base register is parsed from dts (run time), so I see no reason why the dts patch should be separated
Oh, I see; u-boot needs a seperate dtb to boot indepedent. Maybe, we just keep a minimum dts here, then we needn't syncronize with the kernel side.
yes, that's the plan, we will keep necessary dts here, and try to keep it sync with kernel when needed..
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts
I'm totally fine with kernel dts merged first, then submit this later, so no push..
> > On Fri, May 26, 2023 at 8:41 PM Yixun Lan dlan@gentoo.org wrote: > > > > Only add basic support for CPU, PLIC UART and Timer. > > > > Reviewed-by: Wei Fu wefu@redhat.com > > Signed-off-by: Yixun Lan dlan@gentoo.org > > --- > > arch/riscv/dts/Makefile | 1 + > > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > > arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++++ > > 4 files changed, 502 insertions(+) > > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > > create mode 100644 arch/riscv/dts/th1520.dtsi > > > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > > index 79a58694f5..72fd815a40 100644 > > --- a/arch/riscv/dts/Makefile > > +++ b/arch/riscv/dts/Makefile > > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb > > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb > > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb > > include $(srctree)/scripts/Makefile.dts > > > > targets += $(dtb-y) > > diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > new file mode 100644 > > index 0000000000..dc00e3dfa0 > > --- /dev/null > > +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > @@ -0,0 +1,34 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > > + */ > > + > > +/dts-v1/; > > + > > +#include "th1520.dtsi" > > + > > +/ { > > + model = "Sipeed Lichee Module 4A"; > > + compatible = "sipeed,lichee-module-4a", "thead,th1520"; > > + > > + memory@0 { > > + device_type = "memory"; > > + reg = <0x0 0x00000000 0x2 0x00000000>; > > + }; > > +}; > > + > > +&osc { > > + clock-frequency = <24000000>; > > +}; > > + > > +&osc_32k { > > + clock-frequency = <32768>; > > +}; > > + > > +&apb_clk { > > + clock-frequency = <62500000>; > > +}; > > + > > +&uart_sclk { > > + clock-frequency = <100000000>; > > +}; > > diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts > > new file mode 100644 > > index 0000000000..a1248b2ee3 > > --- /dev/null > > +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts > > @@ -0,0 +1,32 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > > + */ > > + > > +#include "th1520-lichee-module-4a.dtsi" > > + > > +/ { > > + model = "Sipeed Lichee Pi 4A"; > > + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; > > + > > + aliases { > > + gpio0 = &gpio0; > > + gpio1 = &gpio1; > > + gpio2 = &gpio2; > > + gpio3 = &gpio3; > > + serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + serial4 = &uart4; > > + serial5 = &uart5; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi > > new file mode 100644 > > index 0000000000..f62a62da6e > > --- /dev/null > > +++ b/arch/riscv/dts/th1520.dtsi > > @@ -0,0 +1,435 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Alibaba Group Holding Limited. > > + * Copyright (C) 2023 Jisheng Zhang jszhang@kernel.org > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "thead,th1520"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus: cpus {
We needn't multi-cpus definitions.
> > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <3000000>; > > + > > + c910_0: cpu@0 { > > + compatible = "thead,c910", "riscv"; > > + device_type = "cpu"; > > + riscv,isa = "rv64imafdc"; > > + reg = <0>; > > + i-cache-block-size = <64>; > > + i-cache-size = <65536>; > > + i-cache-sets = <512>; > > + d-cache-block-size = <64>; > > + d-cache-size = <65536>; > > + d-cache-sets = <512>; > > + next-level-cache = <&l2_cache>; > > + mmu-type = "riscv,sv39"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + c910_1: cpu@1 { > > + compatible = "thead,c910", "riscv"; > > + device_type = "cpu"; > > + riscv,isa = "rv64imafdc"; > > + reg = <1>; > > + i-cache-block-size = <64>; > > + i-cache-size = <65536>; > > + i-cache-sets = <512>; > > + d-cache-block-size = <64>; > > + d-cache-size = <65536>; > > + d-cache-sets = <512>; > > + next-level-cache = <&l2_cache>; > > + mmu-type = "riscv,sv39"; > > + > > + cpu1_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + c910_2: cpu@2 { > > + compatible = "thead,c910", "riscv"; > > + device_type = "cpu"; > > + riscv,isa = "rv64imafdc"; > > + reg = <2>; > > + i-cache-block-size = <64>; > > + i-cache-size = <65536>; > > + i-cache-sets = <512>; > > + d-cache-block-size = <64>; > > + d-cache-size = <65536>; > > + d-cache-sets = <512>; > > + next-level-cache = <&l2_cache>; > > + mmu-type = "riscv,sv39"; > > + > > + cpu2_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + c910_3: cpu@3 { > > + compatible = "thead,c910", "riscv"; > > + device_type = "cpu"; > > + riscv,isa = "rv64imafdc"; > > + reg = <3>; > > + i-cache-block-size = <64>; > > + i-cache-size = <65536>; > > + i-cache-sets = <512>; > > + d-cache-block-size = <64>; > > + d-cache-size = <65536>; > > + d-cache-sets = <512>; > > + next-level-cache = <&l2_cache>; > > + mmu-type = "riscv,sv39"; > > + > > + cpu3_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&c910_0>; > > + }; > > + > > + core1 { > > + cpu = <&c910_1>; > > + }; > > + > > + core2 { > > + cpu = <&c910_2>; > > + }; > > + > > + core3 { > > + cpu = <&c910_3>; > > + }; > > + }; > > + }; > > + > > + l2_cache: l2-cache {
We also needn't l2_cache description for u-boot.
> > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-size = <1048576>; > > + cache-sets = <1024>; > > + cache-unified; > > + }; > > + }; > > + > > + osc: oscillator {
Does u-boot need it?
> > + compatible = "fixed-clock"; > > + clock-output-names = "osc_24m"; > > + #clock-cells = <0>; > > + }; > > + > > + osc_32k: 32k-oscillator {
Does u-boot need it?
> > + compatible = "fixed-clock"; > > + clock-output-names = "osc_32k"; > > + #clock-cells = <0>; > > + }; > > + > > + apb_clk: apb-clk-clock {
Does u-boot need it?
> > + compatible = "fixed-clock"; > > + clock-output-names = "apb_clk"; > > + #clock-cells = <0>; > > + }; > > + > > + uart_sclk: uart-sclk-clock { > > + compatible = "fixed-clock"; > > + clock-output-names = "uart_sclk"; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + cpurst: cpurst {
The u-boot needn't it
> > + compatible = "thead,reset-th1520"; > > + entry-reg = <0xff 0xff019050>; > > + entry-cnt = <4>; > > + control-reg = <0xff 0xff015004>; > > + control-val = <0x1c>; > > + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; > > + }; > This part has been changed. > noted, will update accordingly
> > + > > + plic: interrupt-controller@ffd8000000 { > > + compatible = "thead,th1520-plic", "thead,c900-plic"; > > + reg = <0xff 0xd8000000 0x0 0x01000000>; > > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, > > + <&cpu1_intc 11>, <&cpu1_intc 9>, > > + <&cpu2_intc 11>, <&cpu2_intc 9>, > > + <&cpu3_intc 11>, <&cpu3_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <240>; > > + }; > > + > > + clint: timer@ffdc000000 { > > + compatible = "thead,th1520-clint", "thead,c900-clint"; > > + reg = <0xff 0xdc000000 0x0 0x00010000>; > > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > > + <&cpu1_intc 3>, <&cpu1_intc 7>, > > + <&cpu2_intc 3>, <&cpu2_intc 7>, > > + <&cpu3_intc 3>, <&cpu3_intc 7>; > > + }; > > + > > + uart0: serial@ffe7014000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xe7014000 0x0 0x4000>; > > + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@ffe7f00000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xe7f00000 0x0 0x4000>; > > + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + uart3: serial@ffe7f04000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xe7f04000 0x0 0x4000>; > > + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + gpio2: gpio@ffe7f34000 { > > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xe7f34000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + portc: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + gpio3: gpio@ffe7f38000 {
Do we enable the gpio driver in u-boot?
> > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xe7f38000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + portd: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + gpio0: gpio@ffec005000 { > > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xec005000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + porta: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + gpio1: gpio@ffec006000 { > > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xec006000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + portb: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + uart2: serial@ffec010000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xec010000 0x0 0x4000>; > > + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + timer0: timer@ffefc32000 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xefc32000 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer1: timer@ffefc32014 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xefc32014 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer2: timer@ffefc32028 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xefc32028 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer3: timer@ffefc3203c { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xefc3203c 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + uart4: serial@fff7f08000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xf7f08000 0x0 0x4000>; > > + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + uart5: serial@fff7f0c000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xff 0xf7f0c000 0x0 0x4000>; > > + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&uart_sclk>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + > > + timer4: timer@ffffc33000 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xffc33000 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer5: timer@ffffc33014 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xffc33014 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer6: timer@ffffc33028 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xffc33028 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + timer7: timer@ffffc3303c { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xff 0xffc3303c 0x0 0x14>; > > + clocks = <&apb_clk>; > > + clock-names = "timer"; > > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + ao_gpio0: gpio@fffff41000 { > > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xfff41000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + porte: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + ao_gpio1: gpio@fffff52000 { > > + compatible = "snps,dw-apb-gpio"; > > + reg = <0xff 0xfff52000 0x0 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + portf: gpio-controller@0 { > > + compatible = "snps,dw-apb-gpio-port"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + ngpios = <32>; > > + reg = <0>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + }; > > +}; > > -- > > 2.40.0 > > > > > -- > Best Regards > Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
-- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55
-- Best Regards Guo Ren
Add basic config for Sipeed Lichee PI 4A board which make it capable of booting into serial console.
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org --- configs/th1520_lpi4a_defconfig | 82 ++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 configs/th1520_lpi4a_defconfig
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig new file mode 100644 index 0000000000..710ec6abf5 --- /dev/null +++ b/configs/th1520_lpi4a_defconfig @@ -0,0 +1,82 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a" +CONFIG_SYS_PROMPT="LPI4A=> " +CONFIG_SYS_LOAD_ADDR=0x80200000 +# CONFIG_SMP is not set +CONFIG_TARGET_TH1520_LPI4A=y +CONFIG_ARCH_RV64I=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_FIT=y +# CONFIG_FIT_FULL_CHECK is not set +# CONFIG_FIT_PRINT is not set +# CONFIG_BOOTSTD is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTARGS_SUBST=y +CONFIG_BOOTCOMMAND="" +CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a.dtb" +CONFIG_LOG=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_CONFIG=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +# CONFIG_BLOCK_CACHE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_DM_MMC is not set +# CONFIG_MTD is not set +# CONFIG_POWER is not set +CONFIG_SYS_NS16550=y +CONFIG_RISCV_TIMER=y +CONFIG_AES=y +CONFIG_BLAKE2=y +CONFIG_SHA512=y +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_LZO=y +CONFIG_ZLIB_UNCOMPRESS=y +CONFIG_BZIP2=y +CONFIG_ZSTD=y +CONFIG_LIB_RATIONAL=y +# CONFIG_EFI_LOADER is not set +# CONFIG_LMB_USE_MAX_REGIONS is not set
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org --- doc/board/index.rst | 1 + doc/board/thead/index.rst | 9 +++ doc/board/thead/lpi4a.rst | 112 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 doc/board/thead/index.rst create mode 100644 doc/board/thead/lpi4a.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst index 9ef25b1091..aadc90af89 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -45,6 +45,7 @@ Board-specific doc starfive/index ste/index tbs/index + thead/index ti/index toradex/index variscite/index diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst new file mode 100644 index 0000000000..41566d3a36 --- /dev/null +++ b/doc/board/thead/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +T-HEAD +======== + +.. toctree:: + :maxdepth: 1 + + lpi4a diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst new file mode 100644 index 0000000000..3764e732af --- /dev/null +++ b/doc/board/thead/lpi4a.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sipeed's Lichee PI 4A based on T-HEAD TH1520 SoC +==================== + +TH1520 RISC-V SoC +--------------------- +The TH1520 is 4+2 core 64-bit RISC-V SoC from Alibaba T-HEAD, it's capable of +running highest CPU frequency at 2.5 GHz, integrate Imagination GPU for graphics, +also with 4 TOPS NPU for AI acceleration. + +Mainline support +---------------- + +The support for following drivers are already enabled: + +1. ns16550 UART Driver. + +Building +~~~~~~~~ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + +The U-Boot is capable of running in M-Mode, so we can directly build it. + +.. code-block:: console + + cd <U-Boot-dir> + make th1520_lpi4a_defconfig + make + +This will generate u-boot-dtb.bin + +Booting +~~~~~~~ + +Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem, +and chain load the mainline u-boot image either via tftp or emmc storage, +then bootup from it. + +Sample boot log from Lichee PI 4A board via tftp +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: none + + brom_ver 8 + [APP][E] protocol_connect failed, exit. + + U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000) + FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init + ddr initialized, jump to uboot + image has no header + + + U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000) + + CPU: rv64imafdcvsu + Model: T-HEAD c910 light + DRAM: 8 GiB + C910 CPU FREQ: 750MHz + AHB2_CPUSYS_HCLK FREQ: 250MHz + AHB3_CPUSYS_PCLK FREQ: 125MHz + PERISYS_AHB_HCLK FREQ: 250MHz + PERISYS_APB_PCLK FREQ: 62MHz + GMAC PLL POSTDIV FREQ: 1000MHZ + DPU0 PLL POSTDIV FREQ: 1188MHZ + DPU1 PLL POSTDIV FREQ: 1188MHZ + MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1 + Loading Environment from MMC... OK + Error reading output register + Warning: cannot get lcd-en GPIO + LCD panel cannot be found : -121 + splash screen startup cost 16 ms + In: serial + Out: serial + Err: serial + Net: + Warning: ethernet@ffe7070000 using MAC address from ROM + eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000 + + Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc + , eth1: ethernet@ffe7060000 + Hit any key to stop autoboot: 2 + ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done + Speed: 1000, full duplex + Using ethernet@ffe7070000 device + TFTP from server 192.168.8.50; our IP address is 192.168.8.45 + Filename 'u-boot-dtb.bin'. + Load address: 0x1c00000 + Loading: * ######################### + 8 MiB/s + done + Bytes transferred = 376686 (5bf6e hex) + ## Starting application at 0x01C00000 ... + + U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800) + + CPU: rv64imafdc + Model: Sipeed Lichee Pi 4A + DRAM: 8 GiB + Core: 13 devices, 6 uclasses, devicetree: separate + Loading Environment from <NULL>... OK + In: serial@ffe7014000 + Out: serial@ffe7014000 + Err: serial@ffe7014000 + Model: Sipeed Lichee Pi 4A + LPI4A=>
Hi YiXun,
On Fri, May 26, 2023 at 08:41:07PM +0800, Yixun Lan wrote:
Reviewed-by: Wei Fu wefu@redhat.com Signed-off-by: Yixun Lan dlan@gentoo.org
doc/board/index.rst | 1 + doc/board/thead/index.rst | 9 +++ doc/board/thead/lpi4a.rst | 112 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 doc/board/thead/index.rst create mode 100644 doc/board/thead/lpi4a.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst index 9ef25b1091..aadc90af89 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -45,6 +45,7 @@ Board-specific doc starfive/index ste/index tbs/index
- thead/index ti/index toradex/index variscite/index
diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst new file mode 100644 index 0000000000..41566d3a36 --- /dev/null +++ b/doc/board/thead/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+
+T-HEAD +========
+.. toctree::
- :maxdepth: 1
- lpi4a
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst new file mode 100644 index 0000000000..3764e732af --- /dev/null +++ b/doc/board/thead/lpi4a.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+
+Sipeed's Lichee PI 4A based on T-HEAD TH1520 SoC +====================
The underline is too short and would cause error when building docs.
Best regards, Leo
+TH1520 RISC-V SoC +--------------------- +The TH1520 is 4+2 core 64-bit RISC-V SoC from Alibaba T-HEAD, it's capable of +running highest CPU frequency at 2.5 GHz, integrate Imagination GPU for graphics, +also with 4 TOPS NPU for AI acceleration.
+Mainline support +----------------
+The support for following drivers are already enabled:
+1. ns16550 UART Driver.
+Building +~~~~~~~~
+1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable:
+.. code-block:: none
- export CROSS_COMPILE=<riscv64 toolchain prefix>
+The U-Boot is capable of running in M-Mode, so we can directly build it.
+.. code-block:: console
- cd <U-Boot-dir>
- make th1520_lpi4a_defconfig
- make
+This will generate u-boot-dtb.bin
+Booting +~~~~~~~
+Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem, +and chain load the mainline u-boot image either via tftp or emmc storage, +then bootup from it.
+Sample boot log from Lichee PI 4A board via tftp +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. code-block:: none
- brom_ver 8
- [APP][E] protocol_connect failed, exit.
- U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
- FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
- ddr initialized, jump to uboot
- image has no header
- U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
- CPU: rv64imafdcvsu
- Model: T-HEAD c910 light
- DRAM: 8 GiB
- C910 CPU FREQ: 750MHz
- AHB2_CPUSYS_HCLK FREQ: 250MHz
- AHB3_CPUSYS_PCLK FREQ: 125MHz
- PERISYS_AHB_HCLK FREQ: 250MHz
- PERISYS_APB_PCLK FREQ: 62MHz
- GMAC PLL POSTDIV FREQ: 1000MHZ
- DPU0 PLL POSTDIV FREQ: 1188MHZ
- DPU1 PLL POSTDIV FREQ: 1188MHZ
- MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1
- Loading Environment from MMC... OK
- Error reading output register
- Warning: cannot get lcd-en GPIO
- LCD panel cannot be found : -121
- splash screen startup cost 16 ms
- In: serial
- Out: serial
- Err: serial
- Net:
- Warning: ethernet@ffe7070000 using MAC address from ROM
- eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000
- Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc
- , eth1: ethernet@ffe7060000
- Hit any key to stop autoboot: 2
- ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done
- Speed: 1000, full duplex
- Using ethernet@ffe7070000 device
- TFTP from server 192.168.8.50; our IP address is 192.168.8.45
- Filename 'u-boot-dtb.bin'.
- Load address: 0x1c00000
- Loading: * #########################
8 MiB/s- done
- Bytes transferred = 376686 (5bf6e hex)
- ## Starting application at 0x01C00000 ...
U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800)CPU: rv64imafdcModel: Sipeed Lichee Pi 4ADRAM: 8 GiBCore: 13 devices, 6 uclasses, devicetree: separateLoading Environment from <NULL>... OKIn: serial@ffe7014000Out: serial@ffe7014000Err: serial@ffe7014000Model: Sipeed Lichee Pi 4ALPI4A=>-- 2.40.0
participants (4)
-
Bin Meng -
Guo Ren -
Leo Liang -
Yixun Lan