Wolfgang Denk wrote:

Dear Tom,

In message 902963.84935.qm@web15002.mail.cnb.yahoo.com =?utf-8?B?6Zu3IOmrmA==?= wrote:

...

In u-boot-2009.08/cpu/arm920t/start.S, the instruction of line 158 is "ldr r1, x3ff", but the effective bits in INTSUBMSK register of S3C2410 are [10...0]. So I think "0x3ff" is not right. The right value should be "0x7ff".

What do you think?

I am looking into this. git log is unhelpful. The commit happened in the initial import in 2002 (or 3?) How does one look into the ancient history of u-boot? Is there still a cvs version of the old src?

On the change, someone is wrong.. Does someone have the s3c2410 manual? I have made a document request. If someone could look this up and verify the bit extent is 11 or 10 bits that would be helpful.

Tom

Best regards,

Wolfgang Denk

Alessandro Rubini wrote:

...

Does someone have the s3c2410 manual?

2410UserManual.pdf:

USER'S MANUAL S3C2410A ­ 200MHz & 266MHz 32-Bit RISC Microprocessor Revision 1.0

[...]

INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. [...]

Bits 0..10 are valid, and Bit 10 is "INT_ADC".

Yes

I have the manual now.

INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.

Actually, I think masking all 32 bits can't have any adverse effect.

No. These are marked are resevered. As reserved, we can not assume what the future meaning of these bits will be.

Also, reset value is documented to be 0x7FF (all masked).

Yes, the reset value is 7ff. So I think this is a problem.

Please send a patch. Thanks for finding this problem. Tom

/alessandro