[U-Boot] Ideas on implementing bootcount limit support on non PPC?
Hi,
I have been searching the archives and I've seen posts that suggest that the bootcount feature is trivial to implement in non PPC cpu's but haven't seen a discussion of what would be involved or ideas on how to go about it.
I have flash (where the u-boot env. vars are stored) and EEPROM via I2c. My ARM926ejs variant has SRAM on chip, but I'm not sure of its state on reset yet.
So should I use flash or eeprom to store the bootcount? I know it was originally intended to increment only on reset (not power cycle) but I don't know how I can accomplish since I asked chip vendor if any registers survive reset and the answer was "no".
Looking for ideas on the best way to go about implementing this feature for a ARM926ejs based core. Actual chip is picoChip PC205.
Regards,
Brian
Hi,
I did some experiments with my hardware (picoChip PC205) and it looks like the contents of the internal SRAM are kept during reset so I think making bootcount_load and bootcount_store to access a section in SRAM is the way to go rather than use EEPROM or NOR Flash for the counter (don't want to add wear to the parts).
Regards,
Brian
Dear Brian Hutchinson,
In message 3d1967ab0912150803p1de72a6coa438d53d12e258e7@mail.gmail.com you wrote:
I have been searching the archives and I've seen posts that suggest that the bootcount feature is trivial to implement in non PPC cpu's but haven't seen a discussion of what would be involved or ideas on how to go about it.
Well, basicly you need a CPU register or memory location (SRAM) that is guaranteed not to change it's value during a system reset.
I have flash (where the u-boot env. vars are stored) and EEPROM via I2c. My ARM926ejs variant has SRAM on chip, but I'm not sure of its state on reset yet.
You need to find out.
So should I use flash or eeprom to store the bootcount? I know it was
That's probably not a good idea. It would delay booting a lot, and cause high wear of the flash (or the eeprom).
originally intended to increment only on reset (not power cycle) but I don't know how I can accomplish since I asked chip vendor if any registers survive reset and the answer was "no".
If there is on-chip-memory this might work, but again this is something that only the chip manufacturer will know for sure. Alternatively, use some small external SRAM device (for example, some RTCs feature a small, usually ultra-low power SRAM device [for example, search for "timekeeper"]).
Looking for ideas on the best way to go about implementing this feature for a ARM926ejs based core. Actual chip is picoChip PC205.
Sorry, I don;t know this particular device at all.
Best regards,
Wolfgang Denk
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Brian Hutchinson -
Wolfgang Denk