[PATCH u-boot-marvell v2 1/2] arm: mvebu: spl: Add option to reset the board on DDR training failure
From: Marek Behún marek.behun@nic.cz
Some boards may occacionally fail DDR training. Currently we hang() in this case. Add an option that makes the board do an immediate reset in such a case, so that a new training is tried as soon as possible, instead of hanging and possibly waiting for watchdog to reset the board.
(If the DDR training fails while booting the image via UART, we will still hang - it doesn't make sense to reset in such a case, because after reset the board will try booting from another medium, and the UART booting utility does not expect that.)
Signed-off-by: Marek Behún marek.behun@nic.cz --- Changes since v1: - dont reset if booting via UART, as suggested by Pali --- arch/arm/mach-mvebu/Kconfig | 13 +++++++++++++ arch/arm/mach-mvebu/spl.c | 7 ++++++- 2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d23cc0c760..7d487f270b 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -213,6 +213,19 @@ config DDR_LOG_LEVEL At level 3, rovides the windows margin of each DQ as a results of DQS centeralization.
+config DDR_RESET_ON_TRAINING_FAILURE + bool "Reset the board on DDR training failure instead of hanging" + depends on ARMADA_38X || ARMADA_XP + help + If DDR training fails in SPL, reset the board instead of hanging. + Some boards are known to fail DDR training occasionally and an + immediate reset may be preferable to waiting until the board is + reset by watchdog (if there even is one). + + Note that if booting via UART and the DDR training fails, the + device will still hang - it doesn't make sense to reset the board + in such a case. + config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 273ecb8bd6..5ad323f9d9 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -4,6 +4,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <dm.h> #include <fdtdec.h> #include <hang.h> @@ -330,7 +331,11 @@ void board_init_f(ulong dummy) ret = ddr3_init(); if (ret) { printf("ddr3_init() failed: %d\n", ret); - hang(); + if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) && + get_boot_device() != BOOT_DEVICE_UART) + reset_cpu(); + else + hang(); } #endif
From: Marek Behún marek.behun@nic.cz
The state of the current DDR training code for Armada 38x is such that we cannot be sure it will always train successfully - although after the last change we were yet unable to find a board that failed DDR training, from experience in the last 2 years we know that it is possible.
The experience also tells us that in many cases the board fails training only sometimes, and after a reset the training is successful.
Enable the new option that makes the board reset itself on DDR training failure immediately. Until now we called hang() in such a case, which meant that the board was reset by the MCU after 120 seconds.
Signed-off-by: Marek Behún marek.behun@nic.cz --- configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeaf..010d69adcc 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 CONFIG_ENV_SECT_SIZE=0x10000
On 2/17/22 13:54, Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
The state of the current DDR training code for Armada 38x is such that we cannot be sure it will always train successfully - although after the last change we were yet unable to find a board that failed DDR training, from experience in the last 2 years we know that it is possible.
The experience also tells us that in many cases the board fails training only sometimes, and after a reset the training is successful.
Enable the new option that makes the board reset itself on DDR training failure immediately. Until now we called hang() in such a case, which meant that the board was reset by the MCU after 120 seconds.
Signed-off-by: Marek Behún marek.behun@nic.cz
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeaf..010d69adcc 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 CONFIG_ENV_SECT_SIZE=0x10000
Viele Grüße, Stefan Roese
On Thursday 17 February 2022 13:54:43 Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
The state of the current DDR training code for Armada 38x is such that we cannot be sure it will always train successfully - although after the last change we were yet unable to find a board that failed DDR training, from experience in the last 2 years we know that it is possible.
The experience also tells us that in many cases the board fails training only sometimes, and after a reset the training is successful.
Enable the new option that makes the board reset itself on DDR training failure immediately. Until now we called hang() in such a case, which meant that the board was reset by the MCU after 120 seconds.
Signed-off-by: Marek Behún marek.behun@nic.cz
Reviewed-by: Pali Rohár pali@kernel.org
configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeaf..010d69adcc 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 CONFIG_ENV_SECT_SIZE=0x10000 -- 2.34.1
On 2/17/22 13:54, Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
The state of the current DDR training code for Armada 38x is such that we cannot be sure it will always train successfully - although after the last change we were yet unable to find a board that failed DDR training, from experience in the last 2 years we know that it is possible.
The experience also tells us that in many cases the board fails training only sometimes, and after a reset the training is successful.
Enable the new option that makes the board reset itself on DDR training failure immediately. Until now we called hang() in such a case, which meant that the board was reset by the MCU after 120 seconds.
Signed-off-by: Marek Behún marek.behun@nic.cz
Applied to u-boot-marvell/master
Thanks, Stefan
configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeaf..010d69adcc 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 CONFIG_ENV_SECT_SIZE=0x10000
Viele Grüße, Stefan Roese
On Thursday 17 February 2022 13:54:42 Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
Some boards may occacionally fail DDR training. Currently we hang() in this case. Add an option that makes the board do an immediate reset in such a case, so that a new training is tried as soon as possible, instead of hanging and possibly waiting for watchdog to reset the board.
(If the DDR training fails while booting the image via UART, we will still hang - it doesn't make sense to reset in such a case, because after reset the board will try booting from another medium, and the UART booting utility does not expect that.)
Signed-off-by: Marek Behún marek.behun@nic.cz
Reviewed-by: Pali Rohár pali@kernel.org
Changes since v1:
- dont reset if booting via UART, as suggested by Pali
arch/arm/mach-mvebu/Kconfig | 13 +++++++++++++ arch/arm/mach-mvebu/spl.c | 7 ++++++- 2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d23cc0c760..7d487f270b 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -213,6 +213,19 @@ config DDR_LOG_LEVEL At level 3, rovides the windows margin of each DQ as a results of DQS centeralization.
+config DDR_RESET_ON_TRAINING_FAILURE
- bool "Reset the board on DDR training failure instead of hanging"
- depends on ARMADA_38X || ARMADA_XP
- help
If DDR training fails in SPL, reset the board instead of hanging.Some boards are known to fail DDR training occasionally and animmediate reset may be preferable to waiting until the board isreset by watchdog (if there even is one).Note that if booting via UART and the DDR training fails, thedevice will still hang - it doesn't make sense to reset the boardin such a case.config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 273ecb8bd6..5ad323f9d9 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -4,6 +4,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <dm.h> #include <fdtdec.h> #include <hang.h> @@ -330,7 +331,11 @@ void board_init_f(ulong dummy) ret = ddr3_init(); if (ret) { printf("ddr3_init() failed: %d\n", ret);
hang();
if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&get_boot_device() != BOOT_DEVICE_UART)reset_cpu();elsehang();#endif
-- 2.34.1
On 2/17/22 13:54, Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
Some boards may occacionally fail DDR training. Currently we hang() in this case. Add an option that makes the board do an immediate reset in such a case, so that a new training is tried as soon as possible, instead of hanging and possibly waiting for watchdog to reset the board.
(If the DDR training fails while booting the image via UART, we will still hang - it doesn't make sense to reset in such a case, because after reset the board will try booting from another medium, and the UART booting utility does not expect that.)
Signed-off-by: Marek Behún marek.behun@nic.cz
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
Changes since v1:
- dont reset if booting via UART, as suggested by Pali
arch/arm/mach-mvebu/Kconfig | 13 +++++++++++++ arch/arm/mach-mvebu/spl.c | 7 ++++++- 2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d23cc0c760..7d487f270b 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -213,6 +213,19 @@ config DDR_LOG_LEVEL At level 3, rovides the windows margin of each DQ as a results of DQS centeralization.
+config DDR_RESET_ON_TRAINING_FAILURE
- bool "Reset the board on DDR training failure instead of hanging"
- depends on ARMADA_38X || ARMADA_XP
- help
If DDR training fails in SPL, reset the board instead of hanging.Some boards are known to fail DDR training occasionally and animmediate reset may be preferable to waiting until the board isreset by watchdog (if there even is one).Note that if booting via UART and the DDR training fails, thedevice will still hang - it doesn't make sense to reset the boardin such a case.- config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 273ecb8bd6..5ad323f9d9 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -4,6 +4,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <dm.h> #include <fdtdec.h> #include <hang.h> @@ -330,7 +331,11 @@ void board_init_f(ulong dummy) ret = ddr3_init(); if (ret) { printf("ddr3_init() failed: %d\n", ret);
hang();
if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&get_boot_device() != BOOT_DEVICE_UART)reset_cpu();elsehang();
Viele Grüße, Stefan Roese
On 2/17/22 13:54, Marek Behún wrote:
From: Marek Behún marek.behun@nic.cz
Some boards may occacionally fail DDR training. Currently we hang() in this case. Add an option that makes the board do an immediate reset in such a case, so that a new training is tried as soon as possible, instead of hanging and possibly waiting for watchdog to reset the board.
(If the DDR training fails while booting the image via UART, we will still hang - it doesn't make sense to reset in such a case, because after reset the board will try booting from another medium, and the UART booting utility does not expect that.)
Signed-off-by: Marek Behún marek.behun@nic.cz
Applied to u-boot-marvell/master
Thanks, Stefan
Changes since v1:
- dont reset if booting via UART, as suggested by Pali
arch/arm/mach-mvebu/Kconfig | 13 +++++++++++++ arch/arm/mach-mvebu/spl.c | 7 ++++++- 2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d23cc0c760..7d487f270b 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -213,6 +213,19 @@ config DDR_LOG_LEVEL At level 3, rovides the windows margin of each DQ as a results of DQS centeralization.
+config DDR_RESET_ON_TRAINING_FAILURE
- bool "Reset the board on DDR training failure instead of hanging"
- depends on ARMADA_38X || ARMADA_XP
- help
If DDR training fails in SPL, reset the board instead of hanging.Some boards are known to fail DDR training occasionally and animmediate reset may be preferable to waiting until the board isreset by watchdog (if there even is one).Note that if booting via UART and the DDR training fails, thedevice will still hang - it doesn't make sense to reset the boardin such a case.- config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 273ecb8bd6..5ad323f9d9 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -4,6 +4,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <dm.h> #include <fdtdec.h> #include <hang.h> @@ -330,7 +331,11 @@ void board_init_f(ulong dummy) ret = ddr3_init(); if (ret) { printf("ddr3_init() failed: %d\n", ret);
hang();
if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&get_boot_device() != BOOT_DEVICE_UART)reset_cpu();elsehang();
Viele Grüße, Stefan Roese
participants (3)
-
Marek Behún -
Pali Rohár -
Stefan Roese