From: Gabe Black gabeblack@chromium.org

If we have SPI support, make sure that we init it.

Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Simon Glass sjg@chromium.org Signed-off-by: Vic Yang victoryang@chromium.org --- arch/x86/include/asm/init_helpers.h | 1 + arch/x86/lib/board.c | 3 +++ arch/x86/lib/init_helpers.c | 9 +++++++++ 3 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h index 8afb443..4ea6536 100644 --- a/arch/x86/include/asm/init_helpers.h +++ b/arch/x86/include/asm/init_helpers.h @@ -38,5 +38,6 @@ int init_bd_struct_r(void); int flash_init_r(void); int status_led_set_r(void); int set_load_addr_r(void); +int init_func_spi(void);

#endif /* !_INIT_HELPERS_H_ */ diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index e5caf13..e0c5419 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -154,6 +154,9 @@ init_fnc_t *init_sequence_r[] = { #ifndef CONFIG_SYS_NO_FLASH flash_init_r, #endif +#ifdef CONFIG_SPI + init_func_spi; +#endif env_relocate_r, #ifdef CONFIG_PCI pci_init_r, diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 1863209..4a6d9f3 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -28,6 +28,7 @@ #include <net.h> #include <ide.h> #include <serial.h> +#include <spi.h> #include <status_led.h> #include <asm/processor.h> #include <asm/u-boot-x86.h> @@ -196,3 +197,11 @@ int set_load_addr_r(void)

return 0; } + +int init_func_spi(void) +{ + puts("SPI: "); + spi_init(); + puts("ready\n"); + return 0; +}

From: Gabe Black gabeblack@chromium.org

This seems to be a bug.

Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/lib/relocate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index c0b9b29..23edca9 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -80,7 +80,7 @@ int do_elf_reloc_fixups(void)

/* Check that the target points into .text */ if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE && - *offset_ptr_ram < + *offset_ptr_ram <= (CONFIG_SYS_TEXT_BASE + size)) { *offset_ptr_ram += gd->reloc_off; }

From: Gabe Black gabeblack@chromium.org

Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB.

Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't.

Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/sdram.c | 53 +++++++++++++++++++++++++++++++++++++--- 1 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 5d3da99..611f554 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -51,6 +51,55 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) return num_entries; }

+/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. It + * overrides the default implementation found elsewhere which simply picks the + * end of ram, wherever that may be. The location of the stack, the relocation + * address, and how far U-Boot is moved by relocation are set in the global + * data structure. + */ +int calculate_relocation_address(void) +{ + const uint64_t uboot_size = &__bss_end - &__text_start; + const uint64_t total_size = uboot_size + CONFIG_SYS_MALLOC_LEN + + CONFIG_SYS_STACK_SIZE; + uintptr_t dest_addr = 0; + int i; + + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + /* Force U-Boot to relocate to a page aligned address. */ + uint64_t start = roundup(memrange->base, 1 << 12); + uint64_t end = memrange->base + memrange->size; + + /* Ignore non-memory regions. */ + if (memrange->type != CB_MEM_RAM) + continue; + + /* Filter memory over 4GB. */ + if (end > 0xffffffffULL) + end = 0x100000000ULL; + /* Skip this region if it's too small. */ + if (end - start < total_size) + continue; + + /* Use this address if it's the largest so far. */ + if (end - uboot_size > dest_addr) + dest_addr = (end - uboot_size) & ~((1 << 12) - 1); + } + + /* If no suitable area was found, return an error. */ + if (!dest_addr) + return 1; + + gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN; + gd->relocaddr = dest_addr; + gd->reloc_off = dest_addr - (uintptr_t)&__text_start; + + return 0; +} + int dram_init_f(void) { int i; @@ -60,10 +109,6 @@ int dram_init_f(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size;

- /* Ignore memory over 4GB, we can't use it. */ - if (memrange->base > 0xffffffff) - continue; - if (memrange->type == CB_MEM_RAM && end > ram_size) ram_size = end; }

From: Gabe Black gabeblack@chromium.org

These were removed, but actually are useful.

Cold means that we started from a reset/power on. Warm means that we started from another U-Boot.

We determine whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point). We plumb the result through to the global data structure.

Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/start.S | 10 +++++++++- arch/x86/cpu/start16.S | 3 +++ arch/x86/include/asm/global_data.h | 6 ++++++ 3 files changed, 18 insertions(+), 1 deletions(-)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index ee0dabe..acdd054 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -55,8 +55,16 @@ _x86boot_start: movl %eax, %cr0 wbinvd

+ /* Tell 32-bit code it is being entered from an in-RAM copy */ + movw $GD_FLG_WARM_BOOT, %bx + jmp 1f _start: - /* This is the 32-bit cold-reset entry point */ + /* + * This is the 32-bit cold-reset entry point. Initialize %bx to 0 + * in case we're preceeded by some sort of boot stub. + */ + movw $GD_FLG_COLD_BOOT, %bx +1:

/* Load the segement registes to match the gdt loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index cc393ff..603bf1d 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -37,6 +37,9 @@ .code16 .globl start16 start16: + /* Set the Cold Boot / Hard Reset flag */ + movl $GD_FLG_COLD_BOOT, %ebx + /* * First we let the BSP do some early initialization * this code have to map the flash to its final position diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index d3b6031..b3a6b50 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -77,6 +77,12 @@ static inline gd_t *get_fs_gd_ptr(void)

#include <asm-generic/global_data_flags.h>

+/* + * Our private Global Data Flags + */ +#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ +#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ + #define DECLARE_GLOBAL_DATA_PTR

#endif /* __ASM_GBL_DATA_H */

From: Gabe Black gabeblack@chromium.org

Allow a device tree to be provided through the standard mechanisms.

Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/lib/board.c | 7 +++++++ arch/x86/lib/init_helpers.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index e0c5419..3093ea5 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -98,10 +98,17 @@ typedef int (init_fnc_t) (void); init_fnc_t *init_sequence_f[] = { cpu_init_f, board_early_init_f, +#ifdef CONFIG_OF_CONTROL + find_fdt, + fdtdec_check_fdt, +#endif env_init, init_baudrate_f, serial_init, console_init_f, +#ifdef CONFIG_OF_CONTROL + prepare_fdt, +#endif dram_init_f, calculate_relocation_address,

diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index fc28af7..4a94d96 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -205,3 +205,32 @@ int init_func_spi(void) puts("ready\n"); return 0; } + +#ifdef CONFIG_OF_CONTROL +int find_fdt(void) +{ +#ifdef CONFIG_OF_EMBED + /* Get a pointer to the FDT */ + gd->fdt_blob = _binary_dt_dtb_start; +#elif defined CONFIG_OF_SEPARATE + /* FDT is at end of image */ + gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); +#endif + /* Allow the early environment to override the fdt address */ + gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, + (uintptr_t)gd->fdt_blob); + + return 0; +} + +int prepare_fdt(void) +{ + /* For now, put this check after the console is ready */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } + + return 0; +} +#endif

This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/dts/coreboot.dtsi | 16 ++++++++++++++++ arch/x86/dts/skeleton.dtsi | 13 +++++++++++++ 2 files changed, 29 insertions(+), 0 deletions(-) create mode 100644 arch/x86/dts/coreboot.dtsi create mode 100644 arch/x86/dts/skeleton.dtsi

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi new file mode 100644 index 0000000..4862a59 --- /dev/null +++ b/arch/x86/dts/coreboot.dtsi @@ -0,0 +1,16 @@ +/include/ "skeleton.dtsi" + +/ { + aliases { + console = "/serial"; + }; + + serial { + compatible = "ns16550"; + reg-shift = <1>; + io-mapped = <1>; + multiplier = <1>; + baudrate = <115200>; + status = "disabled"; + }; +}; diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi new file mode 100644 index 0000000..b41d241 --- /dev/null +++ b/arch/x86/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +};

From: Stefan Reinauer reinauer@chromium.org

This helps us monitor boot progress and determine where U-Boot dies if there are any problems.

Signed-off-by: Stefan Reinauer reinauer@google.com

Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/coreboot.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d1be8ff..2912443 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/msr.h> #include <asm/cache.h> +#include <asm/io.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> #include <asm/arch/timestamp.h> @@ -68,6 +69,7 @@ int board_early_init_r(void)

void show_boot_progress(int val) { + outb(val, 0x80); }

From: Duncan Laurie dlaurie@chromium.org

Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie dlaurie@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/coreboot.c | 19 +++++++++++++++---- 1 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 2912443..ff42661 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -94,6 +94,8 @@ void setup_pcat_compatibility() { }

+#define MTRR_TYPE_WP 5 +#define MTRRcap_MSR 0xfe #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

@@ -101,11 +103,20 @@ int board_final_cleanup(void) { /* Un-cache the ROM so the kernel has one * more MTRR available. + * + * Coreboot should have assigned this to the + * top available variable MTRR. */ - disable_cache(); - wrmsr(MTRRphysBase_MSR(7), 0); - wrmsr(MTRRphysMask_MSR(7), 0); - enable_cache(); + u8 top_mtrr = (rdmsr(MTRRcap_MSR) & 0xff) - 1; + u8 top_type = rdmsr(MTRRphysBase_MSR(top_mtrr)) & 0xff; + + /* Make sure this MTRR is the correct Write-Protected type */ + if (top_type == MTRR_TYPE_WP) { + disable_cache(); + wrmsr(MTRRphysBase_MSR(top_mtrr), 0); + wrmsr(MTRRphysMask_MSR(top_mtrr), 0); + enable_cache(); + }

return 0; }

From: Duncan Laurie dlaurie@chromium.org

This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie dlaurie@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/coreboot.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index ff42661..59d730e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -118,5 +118,9 @@ int board_final_cleanup(void) enable_cache(); }

+ /* Issue SMI to Coreboot to lock down ME and registers */ + printf("Finalizing Coreboot\n"); + outb(0xcb, 0xb2); + return 0; }

From: Stefan Reinauer reinauer@chromium.org

... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/Makefile | 3 +-- arch/x86/cpu/coreboot/{coreboot_car.S => car.S} | 0 2 files changed, 1 insertions(+), 2 deletions(-) rename arch/x86/cpu/coreboot/{coreboot_car.S => car.S} (100%)

diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 4612a3e..b1d3e95 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -33,6 +33,7 @@ include $(TOPDIR)/config.mk

LIB := $(obj)lib$(SOC).o

+SOBJS-$(CONFIG_SYS_COREBOOT) += car.o COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o COBJS-$(CONFIG_SYS_COREBOOT) += tables.o COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o @@ -40,8 +41,6 @@ COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o COBJS-$(CONFIG_SYS_COREBOOT) += timestamp.o COBJS-$(CONFIG_PCI) += pci.o

-SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o - SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

diff --git a/arch/x86/cpu/coreboot/coreboot_car.S b/arch/x86/cpu/coreboot/car.S similarity index 100% rename from arch/x86/cpu/coreboot/coreboot_car.S rename to arch/x86/cpu/coreboot/car.S

From: Duncan Laurie dlaurie@chromium.org

This command will start erasing at memory address zero if there is not a valid framebuffer address that was found during video_init().

This is a common case with Chrome OS devices in normal mode when we do not execute the video option rom in coreboot.

Signed-off-by: Duncan Laurie dlaurie@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- drivers/video/cfb_console.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index c8d3e42..2b1f604 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1976,6 +1976,7 @@ int video_get_screen_columns(void)

void video_clear(void) { - memsetl(video_fb_address, - (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), 0); + if (video_fb_address) + memsetl(video_fb_address, + (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), 0); }

Enable the display on coreboot, using CFB.

Signed-off-by: Simon Glass sjg@chromium.org --- include/configs/coreboot.h | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 7c9c7e4..e62d7aa 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -59,6 +59,7 @@ */ #define CONFIG_RTC_MC146818 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS

/*----------------------------------------------------------------------- * Serial Configuration @@ -108,8 +109,13 @@ /*----------------------------------------------------------------------- * Video Configuration */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO +#define CONFIG_VIDEO_COREBOOT +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_INFO_QUIET

/*----------------------------------------------------------------------- * Command line configuration.